## Fleeterpreter ##############################################################################
-ifeq ($(impl),ml509)
+ifeq ($(impl),ml509.large)
java = java -Xmx500m -Dfleet.impl='edu.berkeley.fleet.fpga.ML509$$Large'
effort = high
opt_for = area
package = ff1136
board = ml505 # ??
runhost=goliath
+mergesort_mem=DDR2
else
ifeq ($(impl),bee2)
java = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.fpga.Bee2
xil_ver=9.1i
remote_ise = /tools/xilinx/ISE${xil_ver}_lin/
remote_edk = /tools/xilinx/EDK${xil_ver}/
-effort = high
+effort = std
opt_for = area
part = xc2vp70
package = ff1704
speed_grade=6
-runhost=bee2-tunnel
+runhost=bee2
+mergesort_mem=Memory
else
ifeq ($(impl),java)
java = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.interpreter.Interpreter
+mergesort_mem=Memory
else
-ifeq ($(impl),small)
+ifeq ($(impl),ml509.small)
java = java -Xmx500m -Dfleet.impl='edu.berkeley.fleet.fpga.ML509$$Small'
effort = std
opt_for = area
package = ff1136
board = ml505 # ??
runhost=goliath
+mergesort_mem=Memory
else
java = java -Xmx500m
endif
remote_dir = /scratch/megacz/fleet/
-
#host = mm2.millennium.berkeley.edu
#remote_ise = /scratch/megacz/xilinx/ise/
#remote_edk = /scratch/megacz/xilinx/edk/
#remote_dir = /scratch/megacz/fleet/
-xilinx = cd build/fpga;
+xilinx = cd build/${impl};
xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
xilinx += PATH=$$PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
#xilinx += XST_VERSION=9.2i
device = ${part}-${package}-${speed_grade}
rsync = rsync --exclude=.git --exclude=chips/marina/images -zare ssh --progress --verbose
-upload: fleet.jar build/fpga/main.bit
+upload: fleet.jar build/${impl}/main.bit
mkdir -p build
chmod +x misc/program.sh
- ${rsync} fleet.jar build/fpga/main.bit misc root@${runhost}:fleet/
+ifneq ($(impl),bee2)
+ ${rsync} fleet.jar build/${impl}/main.bit misc root@${runhost}:fleet/
+endif
-build/fpga/main.bit: $(java_files) $(ship_files)
+build/${impl}/main.bit: $(java_files) $(ship_files)
make fleet.jar impl=${impl}
- mkdir -p build/fpga
- $(java) $(cp) edu.berkeley.fleet.fpga.Fpga build/fpga/
- cp src/edu/berkeley/fleet/fpga/* build/fpga || true
+ mkdir -p build/${impl}
+ $(java) $(cp) edu.berkeley.fleet.fpga.Fpga build/${impl}/
+ cp src/edu/berkeley/fleet/fpga/* build/${impl} || true
for A in `find ships -name \*.ship`;\
do $(java) -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
done
ssh ${host} 'mkdir -p ${remote_dir}'
${rsync} --delete ./ ${host}:${remote_dir}
time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk} impl=${impl}'
- scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
- scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/ || true
+ scp ${host}:${remote_dir}/build/${impl}/main.bit build/${impl}/
+ scp ${host}:${remote_dir}/build/${impl}/main.ace build/${impl}/ || true
pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
intstyle = -intstyle xflow
synth:
- cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
- cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
- cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
- cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
- cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
- cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/bee2/* .
- rm -f build/fpga/main.lso
- echo work >> build/fpga/main.lso
- rm -f build/fpga/main.prj
- cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done >> main.prj
- cd build/fpga; for A in *.vhd; do echo vhdl work \""$$A"\"; done >> main.prj
- cd build/fpga; touch main.ini
- cd build/fpga; mkdir -p tmp
- cd build/fpga; mkdir -p xst
- rm -rf build/fpga/_ngo
+ cd build/${impl}; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
+ cd build/${impl}; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
+ cd build/${impl}; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
+ cd build/${impl}; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
+ cd build/${impl}; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
+ cd build/${impl}; ln -sf ../../src/edu/berkeley/fleet/fpga/bee2/* .
+ rm -f build/${impl}/main.lso
+ echo work >> build/${impl}/main.lso
+ rm -f build/${impl}/main.prj
+ cd build/${impl}; for A in *.v; do echo verilog work \""$$A"\"; done >> main.prj
+ cd build/${impl}; for A in *.vhd; do echo vhdl work \""$$A"\"; done >> main.prj
+ cd build/${impl}; touch main.ini
+ cd build/${impl}; mkdir -p tmp
+ cd build/${impl}; mkdir -p xst
+ rm -rf build/${impl}/_ngo
skill xst_original
- rm -f build/fpga/main.xst
- echo "set -tmpdir ./tmp" >> build/fpga/main.xst
- echo "set -xsthdpdir ./xst" >> build/fpga/main.xst
- echo "set -xsthdpini main.ini" >> build/fpga/main.xst
- echo -n "run" >> build/fpga/main.xst
- echo -n " -ifn main.prj" >> build/fpga/main.xst
- echo -n " -ifmt mixed" >> build/fpga/main.xst
- echo -n " -ofn main" >> build/fpga/main.xst
- echo -n " -ofmt NGC" >> build/fpga/main.xst
- echo -n " -p ${device}" >> build/fpga/main.xst
- echo -n " -top main" >> build/fpga/main.xst
- echo -n " -opt_mode ${opt_for}" >> build/fpga/main.xst
- echo -n " -opt_level 2" >> build/fpga/main.xst
- echo -n " -iuc NO" >> build/fpga/main.xst
- echo -n " -lso main.lso" >> build/fpga/main.xst
- echo -n " -keep_hierarchy NO" >> build/fpga/main.xst
- echo -n " -rtlview Yes" >> build/fpga/main.xst
- echo -n " -glob_opt AllClockNets" >> build/fpga/main.xst
- echo -n " -read_cores YES" >> build/fpga/main.xst
- echo -n " -write_timing_constraints NO" >> build/fpga/main.xst
- echo -n " -cross_clock_analysis YES" >> build/fpga/main.xst
- echo -n " -hierarchy_separator /" >> build/fpga/main.xst
- echo -n " -bus_delimiter <>" >> build/fpga/main.xst
- echo -n " -case maintain" >> build/fpga/main.xst
- echo -n " -slice_utilization_ratio 100" >> build/fpga/main.xst
- echo -n " -verilog2001 YES" >> build/fpga/main.xst
- echo -n " -fsm_extract Yes" >> build/fpga/main.xst
- echo -n " -fsm_encoding Auto" >> build/fpga/main.xst
- echo -n " -safe_implementation No" >> build/fpga/main.xst
- echo -n " -fsm_style lut" >> build/fpga/main.xst
- echo -n " -ram_extract Yes" >> build/fpga/main.xst
- echo -n " -ram_style Auto" >> build/fpga/main.xst
- echo -n " -rom_extract Yes" >> build/fpga/main.xst
- echo -n " -mux_style Auto" >> build/fpga/main.xst
- echo -n " -decoder_extract YES" >> build/fpga/main.xst
- echo -n " -priority_extract YES" >> build/fpga/main.xst
- echo -n " -shreg_extract YES" >> build/fpga/main.xst
- echo -n " -shift_extract YES" >> build/fpga/main.xst
- echo -n " -xor_collapse YES" >> build/fpga/main.xst
- echo -n " -rom_style Auto" >> build/fpga/main.xst
- echo -n " -mux_extract YES" >> build/fpga/main.xst
- echo -n " -resource_sharing YES" >> build/fpga/main.xst
- echo -n " -mult_style auto" >> build/fpga/main.xst
- echo -n " -iobuf YES" >> build/fpga/main.xst
- echo -n " -max_fanout 10000" >> build/fpga/main.xst
- echo -n " -bufg 1" >> build/fpga/main.xst
- echo -n " -register_duplication YES" >> build/fpga/main.xst
- echo -n " -register_balancing Yes" >> build/fpga/main.xst
- echo -n " -slice_packing Yes" >> build/fpga/main.xst
- echo -n " -optimize_primitives Yes" >> build/fpga/main.xst
- echo -n " -tristate2logic Yes" >> build/fpga/main.xst
- echo -n " -use_clock_enable Yes" >> build/fpga/main.xst
- echo -n " -use_sync_set Yes" >> build/fpga/main.xst
- echo -n " -use_sync_reset Yes" >> build/fpga/main.xst
- echo -n " -iob auto" >> build/fpga/main.xst
- echo -n " -equivalent_register_removal YES" >> build/fpga/main.xst
- echo -n " -slice_utilization_ratio_maxmargin 5" >> build/fpga/main.xst
- echo >> build/fpga/main.xst
-
- rm -f build/fpga/main.ut
+ rm -f build/${impl}/main.xst
+ echo "set -tmpdir ./tmp" >> build/${impl}/main.xst
+ echo "set -xsthdpdir ./xst" >> build/${impl}/main.xst
+ echo "set -xsthdpini main.ini" >> build/${impl}/main.xst
+ echo -n "run" >> build/${impl}/main.xst
+ echo -n " -ifn main.prj" >> build/${impl}/main.xst
+ echo -n " -ifmt mixed" >> build/${impl}/main.xst
+ echo -n " -ofn main" >> build/${impl}/main.xst
+ echo -n " -ofmt NGC" >> build/${impl}/main.xst
+ echo -n " -p ${device}" >> build/${impl}/main.xst
+ echo -n " -top main" >> build/${impl}/main.xst
+ echo -n " -opt_mode ${opt_for}" >> build/${impl}/main.xst
+ echo -n " -opt_level 2" >> build/${impl}/main.xst
+ echo -n " -iuc NO" >> build/${impl}/main.xst
+ echo -n " -lso main.lso" >> build/${impl}/main.xst
+ echo -n " -keep_hierarchy NO" >> build/${impl}/main.xst
+ echo -n " -rtlview Yes" >> build/${impl}/main.xst
+ echo -n " -glob_opt AllClockNets" >> build/${impl}/main.xst
+ echo -n " -read_cores YES" >> build/${impl}/main.xst
+ echo -n " -write_timing_constraints NO" >> build/${impl}/main.xst
+ echo -n " -cross_clock_analysis YES" >> build/${impl}/main.xst
+ echo -n " -hierarchy_separator /" >> build/${impl}/main.xst
+ echo -n " -bus_delimiter <>" >> build/${impl}/main.xst
+ echo -n " -case maintain" >> build/${impl}/main.xst
+ echo -n " -slice_utilization_ratio 100" >> build/${impl}/main.xst
+ echo -n " -verilog2001 YES" >> build/${impl}/main.xst
+ echo -n " -fsm_extract Yes" >> build/${impl}/main.xst
+ echo -n " -fsm_encoding Auto" >> build/${impl}/main.xst
+ echo -n " -safe_implementation No" >> build/${impl}/main.xst
+ echo -n " -fsm_style lut" >> build/${impl}/main.xst
+ echo -n " -ram_extract Yes" >> build/${impl}/main.xst
+ echo -n " -ram_style Auto" >> build/${impl}/main.xst
+ echo -n " -rom_extract Yes" >> build/${impl}/main.xst
+ echo -n " -mux_style Auto" >> build/${impl}/main.xst
+ echo -n " -decoder_extract YES" >> build/${impl}/main.xst
+ echo -n " -priority_extract YES" >> build/${impl}/main.xst
+ echo -n " -shreg_extract YES" >> build/${impl}/main.xst
+ echo -n " -shift_extract YES" >> build/${impl}/main.xst
+ echo -n " -xor_collapse YES" >> build/${impl}/main.xst
+ echo -n " -rom_style Auto" >> build/${impl}/main.xst
+ echo -n " -mux_extract YES" >> build/${impl}/main.xst
+ echo -n " -resource_sharing YES" >> build/${impl}/main.xst
+ echo -n " -mult_style auto" >> build/${impl}/main.xst
+ echo -n " -iobuf YES" >> build/${impl}/main.xst
+ echo -n " -max_fanout 10000" >> build/${impl}/main.xst
+ echo -n " -bufg 1" >> build/${impl}/main.xst
+ echo -n " -register_duplication YES" >> build/${impl}/main.xst
+ echo -n " -register_balancing Yes" >> build/${impl}/main.xst
+ echo -n " -slice_packing Yes" >> build/${impl}/main.xst
+ echo -n " -optimize_primitives Yes" >> build/${impl}/main.xst
+ echo -n " -tristate2logic Yes" >> build/${impl}/main.xst
+ echo -n " -use_clock_enable Yes" >> build/${impl}/main.xst
+ echo -n " -use_sync_set Yes" >> build/${impl}/main.xst
+ echo -n " -use_sync_reset Yes" >> build/${impl}/main.xst
+ echo -n " -iob auto" >> build/${impl}/main.xst
+ echo -n " -equivalent_register_removal YES" >> build/${impl}/main.xst
+ echo -n " -slice_utilization_ratio_maxmargin 5" >> build/${impl}/main.xst
+ echo >> build/${impl}/main.xst
+
+ rm -f build/${impl}/main.ut
ifneq ($(impl),bee2)
- echo '-w' >> build/fpga/main.ut
- echo '-g CclkPin:PULLUP' >> build/fpga/main.ut
- echo '-g TdoPin:PULLNONE' >> build/fpga/main.ut
- echo '-g M1Pin:PULLDOWN' >> build/fpga/main.ut
- echo '-g DonePin:PULLUP' >> build/fpga/main.ut
- echo '-g DriveDone:No' >> build/fpga/main.ut
- echo '-g StartUpClk:JTAGCLK' >> build/fpga/main.ut
- echo '-g DONE_cycle:4' >> build/fpga/main.ut
- echo '-g GTS_cycle:5' >> build/fpga/main.ut
- echo '-g M0Pin:PULLUP' >> build/fpga/main.ut
- echo '-g M2Pin:PULLUP' >> build/fpga/main.ut
- echo '-g ProgPin:PULLUP' >> build/fpga/main.ut
- echo '-g TckPin:PULLUP' >> build/fpga/main.ut
- echo '-g TdiPin:PULLUP' >> build/fpga/main.ut
- echo '-g TmsPin:PULLUP' >> build/fpga/main.ut
- echo '-g DonePipe:No' >> build/fpga/main.ut
- echo '-g GWE_cycle:6' >> build/fpga/main.ut
- echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
- echo '-g Security:NONE' >> build/fpga/main.ut
- echo '-g Persist:No' >> build/fpga/main.ut
+ echo '-w' >> build/${impl}/main.ut
+ echo '-g CclkPin:PULLUP' >> build/${impl}/main.ut
+ echo '-g TdoPin:PULLNONE' >> build/${impl}/main.ut
+ echo '-g M1Pin:PULLDOWN' >> build/${impl}/main.ut
+ echo '-g DonePin:PULLUP' >> build/${impl}/main.ut
+ echo '-g DriveDone:No' >> build/${impl}/main.ut
+ echo '-g StartUpClk:JTAGCLK' >> build/${impl}/main.ut
+ echo '-g DONE_cycle:4' >> build/${impl}/main.ut
+ echo '-g GTS_cycle:5' >> build/${impl}/main.ut
+ echo '-g M0Pin:PULLUP' >> build/${impl}/main.ut
+ echo '-g M2Pin:PULLUP' >> build/${impl}/main.ut
+ echo '-g ProgPin:PULLUP' >> build/${impl}/main.ut
+ echo '-g TckPin:PULLUP' >> build/${impl}/main.ut
+ echo '-g TdiPin:PULLUP' >> build/${impl}/main.ut
+ echo '-g TmsPin:PULLUP' >> build/${impl}/main.ut
+ echo '-g DonePipe:No' >> build/${impl}/main.ut
+ echo '-g GWE_cycle:6' >> build/${impl}/main.ut
+ echo '-g LCK_cycle:NoWait' >> build/${impl}/main.ut
+ echo '-g Security:NONE' >> build/${impl}/main.ut
+ echo '-g Persist:No' >> build/${impl}/main.ut
endif
ifeq ($(impl),bee2)
- echo '-w' >> build/fpga/main.ut
- echo '-g DebugBitstream:No' >> build/fpga/main.ut
- echo '-g Binary:no' >> build/fpga/main.ut
- echo '-g CRC:Enable' >> build/fpga/main.ut
- echo '-g ConfigRate:4' >> build/fpga/main.ut
- echo '-g CclkPin:PullUp' >> build/fpga/main.ut
- echo '-g M0Pin:PullUp' >> build/fpga/main.ut
- echo '-g M1Pin:PullUp' >> build/fpga/main.ut
- echo '-g M2Pin:PullUp' >> build/fpga/main.ut
- echo '-g ProgPin:PullUp' >> build/fpga/main.ut
- echo '-g DonePin:PullUp' >> build/fpga/main.ut
- echo '-g PowerdownPin:PullUp' >> build/fpga/main.ut
- echo '-g TckPin:PullUp' >> build/fpga/main.ut
- echo '-g TdiPin:PullUp' >> build/fpga/main.ut
- echo '-g TdoPin:PullNone' >> build/fpga/main.ut
- echo '-g TmsPin:PullUp' >> build/fpga/main.ut
- echo '-g UnusedPin:PullDown' >> build/fpga/main.ut
- echo '-g UserID:0xFFFFFFFF' >> build/fpga/main.ut
- echo '-g DCMShutdown:Disable' >> build/fpga/main.ut
- echo '-g DisableBandgap:No' >> build/fpga/main.ut
- echo '-g DCIUpdateMode:AsRequired' >> build/fpga/main.ut
- echo '-g StartUpClk:CClk' >> build/fpga/main.ut
- echo '-g DONE_cycle:4' >> build/fpga/main.ut
- echo '-g GTS_cycle:5' >> build/fpga/main.ut
- echo '-g GWE_cycle:6' >> build/fpga/main.ut
- echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
- echo '-g Security:None' >> build/fpga/main.ut
- echo '-g DonePipe:No' >> build/fpga/main.ut
- echo '-g DriveDone:No' >> build/fpga/main.ut
- echo '-g Encrypt:No' >> build/fpga/main.ut
+ echo '-w' >> build/${impl}/main.ut
+ echo '-g DebugBitstream:No' >> build/${impl}/main.ut
+ echo '-g Binary:no' >> build/${impl}/main.ut
+ echo '-g CRC:Enable' >> build/${impl}/main.ut
+ echo '-g ConfigRate:4' >> build/${impl}/main.ut
+ echo '-g CclkPin:PullUp' >> build/${impl}/main.ut
+ echo '-g M0Pin:PullUp' >> build/${impl}/main.ut
+ echo '-g M1Pin:PullUp' >> build/${impl}/main.ut
+ echo '-g M2Pin:PullUp' >> build/${impl}/main.ut
+ echo '-g ProgPin:PullUp' >> build/${impl}/main.ut
+ echo '-g DonePin:PullUp' >> build/${impl}/main.ut
+ echo '-g PowerdownPin:PullUp' >> build/${impl}/main.ut
+ echo '-g TckPin:PullUp' >> build/${impl}/main.ut
+ echo '-g TdiPin:PullUp' >> build/${impl}/main.ut
+ echo '-g TdoPin:PullNone' >> build/${impl}/main.ut
+ echo '-g TmsPin:PullUp' >> build/${impl}/main.ut
+ echo '-g UnusedPin:PullDown' >> build/${impl}/main.ut
+ echo '-g UserID:0xFFFFFFFF' >> build/${impl}/main.ut
+ echo '-g DCMShutdown:Disable' >> build/${impl}/main.ut
+ echo '-g DisableBandgap:No' >> build/${impl}/main.ut
+ echo '-g DCIUpdateMode:AsRequired' >> build/${impl}/main.ut
+ echo '-g StartUpClk:CClk' >> build/${impl}/main.ut
+ echo '-g DONE_cycle:4' >> build/${impl}/main.ut
+ echo '-g GTS_cycle:5' >> build/${impl}/main.ut
+ echo '-g GWE_cycle:6' >> build/${impl}/main.ut
+ echo '-g LCK_cycle:NoWait' >> build/${impl}/main.ut
+ echo '-g Security:None' >> build/${impl}/main.ut
+ echo '-g DonePipe:No' >> build/${impl}/main.ut
+ echo '-g DriveDone:No' >> build/${impl}/main.ut
+ echo '-g Encrypt:No' >> build/${impl}/main.ut
endif
$(xilinx_ise)xst ${intstyle} -ifn main.xst -ofn main.syr < main.xst \
| grep --line-buffered -v 'been backward balanced into' \
| grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
| grep --line-buffered -v 'WARNING:Xst:616 - Invalid property'
- cat build/fpga/*.ucf > build/fpga/main.ucf
+ cat build/${impl}/*.ucf > build/${impl}/main.ucf
$(xilinx_ise)ngdbuild ${intstyle} -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
$(xilinx_ise)map ${intstyle} -ol ${effort} -p $(device) -pr b -cm ${opt_for} -o main_map.ncd main.ngd main.pcf
$(xilinx_ise)par ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
$(xilinx_ise)bitgen ${intstyle} -f main.ut main.ncd
ifneq ($(impl),bee2)
$(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
- mv build/fpga/mainx.ace build/fpga/main.ace # genace throws a fit if the filename prefix is the same?
+ mv build/${impl}/mainx.ace build/${impl}/main.ace # genace throws a fit if the filename prefix is the same?
endif
runserver: fleet.jar
test: fleet.jar
$(java) -jar fleet.jar test ships/*.ship tests
- $(java) -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort Memory 0 256
+ $(java) -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort ${mergesort_mem} 0 256
demo: fleet.jar
$(java) -cp fleet.jar edu.berkeley.fleet.dataflow.SortingDemo
all_electric_files = $(shell find chips/marina/electric/ -name \*.jelib -or -path \*.delib\*)
modname = fakeMarinaPadframe
-sun_server = simmons-tunnel
+sun_dir = /home/am77536/fleet
+sun_fs_server = ivans
+sun_server = simmons
#sun_server = frehley # electric team uses frehley
#sun_server = simmons
#sun_server = criss # criss is used for nohupped nanosim
#sun_server = stanley # stanley is used for nohupped hsim
-testnum = 0
+#testnum = 3025
+#testnum = 3040
+#testnum = 0
+#testnum = 999
+testnum = 8888
runtest: fleet.jar chips/marina/testCode/marina.xml chips/marina/testCode/marina.v chips/marina/testCode/marina.schematic-parasitics.spi
- ${rsync} --delete ./ ${sun_server}:~/fleet/
- time ssh -t -Y ${sun_server} 'cd ~/fleet/; make testlocal impl=${impl}'
-
-silicon: fleet.jar chips/marina/testCode/marina.xml
- ${rsync} --delete ./ ${sun_server}:~/fleet/
- time ssh -t -Y ${sun_server} 'cd ~/fleet/; make siliconlocal impl=${impl}'
+ ${rsync} --delete ./ ${sun_fs_server}:${sun_dir}/
+ time ssh -t -Y ${sun_fs_server} 'ssh -t am77536@${sun_server} "cd ${sun_dir}/; make testlocal impl=${impl}"'
spice: fleet.jar
cp ~/omegaCounter.spi chips/marina/testCode/omegaCounter.spi
cp ~/omegaCounter-extracted.spi chips/marina/testCode/omegaCounter-extracted.spi
- rsync -azre ssh --delete --progress --verbose ./ ${sun_server}:~/fleet/
- ssh -t -Y ${sun_server} 'cd ~/fleet/chips/marina/testCode/; export PATH=/proj/async/cad/linux/bin/:$$PATH; echo -e "rcf commands\n" | hsim64 -time 90000 go.spi -o go.spi'
+ rsync -azre ssh --delete --progress --verbose ./ ${sun_fs_server}:${sun_dir}/
+ ssh -t -Y ${sun_fs_server} 'cd ${sun_dir}/chips/marina/testCode/; export PATH=/proj/async/cad/linux/bin/:$$PATH; echo -e "rcf commands\n" | hsim64 -time 90000 go.spi -o go.spi'
-testlocal: fleet.jar
- cd chips/marina/testCode; \
- export PATH=/proj/async/cad/linux/bin/:$$PATH; \
- /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java \
- -cp `pwd`/../../../lib/com.sun.async.test.jar:`pwd`/../../../fleet.jar \
- -Dfleet.impl=com.sun.vlsi.chips.marina.test.Marina \
- com.sun.vlsi.chips.marina.test.MarinaTest \
- -hsim \
- -testNum ${testnum} || tail -n 20 marina.spi.run
+ifeq ($(impl),silicon)
+testarg=-silicon
+else
+testarg=-hsim
+endif
-siliconlocal: fleet.jar
+testlocal: fleet.jar
cd chips/marina/testCode; \
export PATH=/proj/async/cad/linux/bin/:$$PATH; \
- /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java \
+ export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/proj/async/cad/test/; \
+ /proj/async/cad/linux/lib/jdk1.6/bin/java \
-cp `pwd`/../../../lib/com.sun.async.test.jar:`pwd`/../../../fleet.jar \
-Djava.library.path=/proj/async/cad/test/ \
-Dfleet.impl=com.sun.vlsi.chips.marina.test.Marina \
com.sun.vlsi.chips.marina.test.MarinaTest \
- -silicon \
- -testNum ${testnum}
+ ${testarg} \
+ -testNum ${testnum} || tail -n 20 marina.spi.run
chips/marina/testCode/marina.xml \
chips/marina/testCode/marina.v \
${electric} chips/marina/electric/aMarinaM.jelib
sync:
- ${rsync} ${sun_server}:fleet/chips/marina/testCode/marina\*.dump ~/ || true
- ${rsync} ${sun_server}:fleet/chips/marina/testCode/marina.spi.out ~/${modname}.out || true
+ ${rsync} ${sun_fs_server}:${sun_dir}/chips/marina/testCode/marina\*.dump ~/ || true
+ ${rsync} ${sun_fs_server}:${sun_dir}/chips/marina/testCode/marina.spi.out ~/${modname}.out || true
copyin:
cp ~/${modname}.spi chips/marina/testCode/marina.schematic-parasitics.spi || true
cp ~/${modname}.v chips/marina/testCode/marina.v || true
chips/marina/testCode/omegaCounter-extracted.spi: ${all_electric_files} chips/marina/testCode/rcx.bsh
@echo
@echo == Extracting Layout ===========================================================
- ssh ${sun_server} 'rm -rf /tmp/am77536; mkdir /tmp/am77536'
+ ssh ${sun_fs_server} 'rm -rf /tmp/am77536; mkdir /tmp/am77536'
cd chips/marina/testCode; \
nice -n 19 ${electric_headless} -s rcx.bsh ../electric/omegaCounter.jelib
mv chips/marina/electric/starrcxt/omegaCounter.sp $@
projects / fleet.git / commitdiff