+++ /dev/null
-*** SPICE deck for cell marinaOutDock{sch} from library aMarinaM
-*** Created on Mon Nov 17, 2008 08:47:24
-*** Last revised on Sat May 02, 2009 06:16:53
-*** Written on Tue May 12, 2009 17:08:00 by Electric VLSI Design System,
-*version 8.08k
-*** Layout tech: cmos90, foundry TSMC
-*** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
-.OPTIONS NOMOD NOPAGE
-* Model cards are described in this file:
-.include '../testCode/header.hsp'
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_40 d g s
-MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2'
-+DELVTO='AVT0N/sqrt(120*2)'
-.ENDS NMOSx-X_40
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_40 d g s
-MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2'
-+DELVTO='AVT0P/sqrt(240*2)'
-.ENDS PMOSx-X_40
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_40 in out
-XNMOS@0 out in gnd NMOSx-X_40
-XPMOS@0 out in vdd PMOSx-X_40
-.ENDS inv-X_40
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_10 d g s
-MPMOSf@0 d g s vdd pch W='60*(1+ABP/sqrt(60*2))' L='2'
-+DELVTO='AVT0P/sqrt(60*2)'
-.ENDS PMOSx-X_10
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_20 d g s
-MNMOSf@0 d g s gnd nch W='60*(1+ABN/sqrt(60*2))' L='2'
-+DELVTO='AVT0N/sqrt(60*2)'
-.ENDS NMOSx-X_20
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_10 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_20
-XNMOS@1 net@0 g gnd NMOSx-X_20
-.ENDS nms2-X_10
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_10 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_10
-XPMOS@1 out inb vdd PMOSx-X_10
-Xnms2@0 out ina inb nms2-X_10
-.ENDS nand2-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-506_4-R_34_667m a b
-Ccap@0 gnd net@14 1.857f
-Ccap@1 gnd net@8 1.857f
-Ccap@2 gnd net@11 1.857f
-Rres@0 net@14 a 2.926
-Rres@1 net@11 net@14 5.852
-Rres@2 b net@8 2.926
-Rres@3 net@8 net@11 5.852
-.ENDS wire-C_0_011f-506_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-506_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-506_4-R_34_667m
-.ENDS wire90-506_4-layer_1-width_3
-
-*** CELL: countersL:cntShift{sch}
-.SUBCKT cntShift ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
-+sid[7] sid[8] sid[9] sin
-Xinv@3 net@98 myp1p inv-X_40
-Xinv@4 net@100 myp2p inv-X_40
-Xnand2@4 ctgLO sid[2] net@99 nand2-X_10
-Xnand2@5 ctgLO sid[3] net@97 nand2-X_10
-Xwire90@9 net@98 net@97 wire90-506_4-layer_1-width_3
-Xwire90@10 net@100 net@99 wire90-506_4-layer_1-width_3
-.ENDS cntShift
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_10 d g s
-MNMOSf@0 d g s gnd nch W='30*(1+ABN/sqrt(30*2))' L='2'
-+DELVTO='AVT0N/sqrt(30*2)'
-.ENDS NMOSx-X_10
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_10 in out
-XNMOS@0 out in gnd NMOSx-X_10
-XPMOS@0 out in vdd PMOSx-X_10
-.ENDS inv-X_10
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_5 d g s
-MPMOSf@0 d g s vdd pch W='30*(1+ABP/sqrt(30*2))' L='2'
-+DELVTO='AVT0P/sqrt(30*2)'
-.ENDS PMOSx-X_5
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_5 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_10
-XNMOS@1 net@0 g gnd NMOSx-X_10
-.ENDS nms2-X_5
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_5 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_5
-XPMOS@1 out inb vdd PMOSx-X_5
-Xnms2@0 out ina inb nms2-X_5
-.ENDS nand2-X_5
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_20 d g s
-MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2'
-+DELVTO='AVT0P/sqrt(120*2)'
-.ENDS PMOSx-X_20
-
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_20 d g g2
-Xnms2@0 d g g2 nms2-X_10
-Xnms2@1 d g2 g nms2-X_10
-.ENDS nms2_sy-X_20
-
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_20 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_20
-XPMOS@1 out ina vdd PMOSx-X_20
-Xnms2_sy@0 out ina inb nms2_sy-X_20
-.ENDS nand2_sy-X_20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-243_7-R_34_667m a b
-Ccap@0 gnd net@14 0.894f
-Ccap@1 gnd net@8 0.894f
-Ccap@2 gnd net@11 0.894f
-Rres@0 net@14 a 1.408
-Rres@1 net@11 net@14 2.816
-Rres@2 b net@8 1.408
-Rres@3 net@8 net@11 2.816
-.ENDS wire-C_0_011f-243_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-243_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-243_7-R_34_667m
-.ENDS wire90-243_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-504-R_34_667m a b
-Ccap@0 gnd net@14 1.848f
-Ccap@1 gnd net@8 1.848f
-Ccap@2 gnd net@11 1.848f
-Rres@0 net@14 a 2.912
-Rres@1 net@11 net@14 5.824
-Rres@2 b net@8 2.912
-Rres@3 net@8 net@11 5.824
-.ENDS wire-C_0_011f-504-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-504-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-504-R_34_667m
-.ENDS wire90-504-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-403_5-R_34_667m a b
-Ccap@0 gnd net@14 1.479f
-Ccap@1 gnd net@8 1.479f
-Ccap@2 gnd net@11 1.479f
-Rres@0 net@14 a 2.331
-Rres@1 net@11 net@14 4.663
-Rres@2 b net@8 2.331
-Rres@3 net@8 net@11 4.663
-.ENDS wire-C_0_011f-403_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-403_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-403_5-R_34_667m
-.ENDS wire90-403_5-layer_1-width_3
-
-*** CELL: countersL:cntFreq{sch}
-.SUBCKT cntFreq count ctgLO fin fout myFin
-Xinv@0 ctgLO net@17 inv-X_10
-Xinv@1 count ctgLO inv-X_40
-Xnand2@0 net@18 myFin net@72 nand2-X_5
-Xnand2@1 ctgLO fin net@33 nand2-X_5
-Xnand2_sy@0 net@34 net@39 fout nand2_sy-X_20
-Xwire90@2 net@17 net@18 wire90-243_7-layer_1-width_3
-Xwire90@4 net@34 net@33 wire90-504-layer_1-width_3
-Xwire90@5 net@39 net@72 wire90-403_5-layer_1-width_3
-.ENDS cntFreq
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_5 d g s
-MNMOSf@0 d g s gnd nch W='15*(1+ABN/sqrt(15*2))' L='2'
-+DELVTO='AVT0N/sqrt(15*2)'
-.ENDS NMOSx-X_5
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_5 in out
-XNMOS@0 out in gnd NMOSx-X_5
-XPMOS@0 out in vdd PMOSx-X_5
-.ENDS inv-X_5
-
-*** CELL: orangeTSMC090nm:NMOSxwk{sch}
-.SUBCKT NMOSxwk-X_1_733 d g s
-MNMOSfwk@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2'
-+DELVTO='AVT0N/sqrt(5.199*2)'
-.ENDS NMOSxwk-X_1_733
-
-*** CELL: orangeTSMC090nm:PMOSxwk{sch}
-.SUBCKT PMOSxwk-X_1 d g s
-MPMOSfwk@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'
-+DELVTO='AVT0P/sqrt(6*2)'
-.ENDS PMOSxwk-X_1
-
-*** CELL: orangeTSMC090nm:PMOSxwk{sch}
-.SUBCKT PMOSxwk-X_4 d g s
-MPMOSfwk@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2'
-+DELVTO='AVT0P/sqrt(24*2)'
-.ENDS PMOSxwk-X_4
-
-*** CELL: latchPartsK:latchKeep{sch}
-.SUBCKT latchKeep out[B] out[s]
-XNMOSxwk@0 out[s] out[B] gnd NMOSxwk-X_1_733
-XNMOSxwk@1 out[B] out[s] gnd NMOSxwk-X_1_733
-XPMOSxwk@0 out[s] out[B] vdd PMOSxwk-X_1
-XPMOSxwk@1 out[B] out[s] vdd PMOSxwk-X_4
-.ENDS latchKeep
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_3 d g s
-MNMOSf@0 d g s gnd nch W='9*(1+ABN/sqrt(9*2))' L='2' DELVTO='AVT0N/sqrt(9*2)'
-.ENDS NMOSx-X_3
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_6 d g s
-MNMOSf@0 d g s gnd nch W='18*(1+ABN/sqrt(18*2))' L='2'
-+DELVTO='AVT0N/sqrt(18*2)'
-.ENDS NMOSx-X_6
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_5 in out
-XNMOS@0 out in gnd NMOSx-X_10
-XPMOS@0 out in vdd PMOSx-X_5
-.ENDS invLT-X_5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-124_4-R_34_667m a b
-Ccap@0 gnd net@14 0.456f
-Ccap@1 gnd net@8 0.456f
-Ccap@2 gnd net@11 0.456f
-Rres@0 net@14 a 0.719
-Rres@1 net@11 net@14 1.438
-Rres@2 b net@8 0.719
-Rres@3 net@8 net@11 1.438
-.ENDS wire-C_0_011f-124_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-124_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-124_4-R_34_667m
-.ENDS wire90-124_4-layer_1-width_3
-
-*** CELL: latchPartsK:latchPointF{sch}
-.SUBCKT latchPointF hcl in[1] x[F] x[T]
-XPMOSx@0 in[1] hcl x[T] NMOSx-X_3
-XPMOSx@1 net@8 hcl x[F] NMOSx-X_6
-Xinv@0 in[1] net@105 invLT-X_5
-Xwire90@0 net@105 net@8 wire90-124_4-layer_1-width_3
-.ENDS latchPointF
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-145_9-R_34_667m a b
-Ccap@0 gnd net@14 0.535f
-Ccap@1 gnd net@8 0.535f
-Ccap@2 gnd net@11 0.535f
-Rres@0 net@14 a 0.843
-Rres@1 net@11 net@14 1.686
-Rres@2 b net@8 0.843
-Rres@3 net@8 net@11 1.686
-.ENDS wire-C_0_011f-145_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-145_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-145_9-R_34_667m
-.ENDS wire90-145_9-layer_1-width_3
-
-*** CELL: latchesK:raw2inLatchF{sch}
-.SUBCKT raw2inLatchF hcl[A] hcl[B] inA[1] inB[1] out[F]
-XlatchKee@0 out[F] net@63 latchKeep
-XlatchPoi@0 hcl[A] inA[1] out[F] net@45 latchPointF
-XlatchPoi@1 hcl[B] inB[1] out[F] net@45 latchPointF
-Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
-.ENDS raw2inLatchF
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-242_1-R_34_667m a b
-Ccap@0 gnd net@14 0.888f
-Ccap@1 gnd net@8 0.888f
-Ccap@2 gnd net@11 0.888f
-Rres@0 net@14 a 1.399
-Rres@1 net@11 net@14 2.798
-Rres@2 b net@8 1.399
-Rres@3 net@8 net@11 2.798
-.ENDS wire-C_0_011f-242_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-242_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-242_1-R_34_667m
-.ENDS wire90-242_1-layer_1-width_3
-
-*** CELL: latchesK:latch2in10A{sch}
-.SUBCKT latch2in10A hcl[A] hcl[B] inA[1] inB[1] out[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
-XinvLT@1 net@16 out[1] inv-X_10
-Xwire90@1 dataBar net@16 wire90-242_1-layer_1-width_3
-.ENDS latch2in10A
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_2_5 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_5
-XPMOS@1 d g2 net@2 PMOSx-X_5
-.ENDS pms2-X_2_5
-
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_5 d g g2
-Xpms2@0 d g g2 pms2-X_2_5
-Xpms2@1 d g2 g pms2-X_2_5
-.ENDS pms2_sy-X_5
-
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_5 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_5
-XNMOS@1 out ina gnd NMOSx-X_5
-Xpms2_sy@0 out ina inb pms2_sy-X_5
-.ENDS nor2_sy-X_5
-
-*** CELL: redFive:nor2n_sy{sch}
-.SUBCKT nor2n_sy-X_5 ina inb out
-Xnor2@0 ina inb out nor2_sy-X_5
-.ENDS nor2n_sy-X_5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-214_2-R_34_667m a b
-Ccap@0 gnd net@14 0.785f
-Ccap@1 gnd net@8 0.785f
-Ccap@2 gnd net@11 0.785f
-Rres@0 net@14 a 1.238
-Rres@1 net@11 net@14 2.475
-Rres@2 b net@8 1.238
-Rres@3 net@8 net@11 2.475
-.ENDS wire-C_0_011f-214_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-214_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-214_2-R_34_667m
-.ENDS wire90-214_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-413_4-R_34_667m a b
-Ccap@0 gnd net@14 1.516f
-Ccap@1 gnd net@8 1.516f
-Ccap@2 gnd net@11 1.516f
-Rres@0 net@14 a 2.389
-Rres@1 net@11 net@14 4.777
-Rres@2 b net@8 2.389
-Rres@3 net@8 net@11 4.777
-.ENDS wire-C_0_011f-413_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-413_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-413_4-R_34_667m
-.ENDS wire90-413_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-231_2-R_34_667m a b
-Ccap@0 gnd net@14 0.848f
-Ccap@1 gnd net@8 0.848f
-Ccap@2 gnd net@11 0.848f
-Rres@0 net@14 a 1.336
-Rres@1 net@11 net@14 2.672
-Rres@2 b net@8 1.336
-Rres@3 net@8 net@11 2.672
-.ENDS wire-C_0_011f-231_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-231_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-231_2-R_34_667m
-.ENDS wire90-231_2-layer_1-width_3
-
-*** CELL: countersL:cntScnOne{sch}
-.SUBCKT cntScnOne cin ctgLO out p1p p2p sin
-Xinv@0 out net@14 inv-X_5
-Xlatch2in@0 cB p1p net@3 net@3 out latch2in10A
-Xlatch2in@1 cA p2p net@15 sin net@6 latch2in10A
-Xnor2n_sy@0 ctgLO cB net@20 nor2n_sy-X_5
-Xnor2n_sy@2 ctgLO cin net@25 nor2n_sy-X_5
-Xwire90@0 net@15 net@14 wire90-214_2-layer_1-width_3
-Xwire90@1 net@6 net@3 wire90-506_4-layer_1-width_3
-Xwire90@2 net@20 cA wire90-413_4-layer_1-width_3
-Xwire90@3 net@25 cB wire90-231_2-layer_1-width_3
-.ENDS cntScnOne
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-668_5-R_34_667m a b
-Ccap@0 gnd net@14 2.451f
-Ccap@1 gnd net@8 2.451f
-Ccap@2 gnd net@11 2.451f
-Rres@0 net@14 a 3.862
-Rres@1 net@11 net@14 7.725
-Rres@2 b net@8 3.862
-Rres@3 net@8 net@11 7.725
-.ENDS wire-C_0_011f-668_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-668_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-668_5-R_34_667m
-.ENDS wire90-668_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-680_5-R_34_667m a b
-Ccap@0 gnd net@14 2.495f
-Ccap@1 gnd net@8 2.495f
-Ccap@2 gnd net@11 2.495f
-Rres@0 net@14 a 3.932
-Rres@1 net@11 net@14 7.864
-Rres@2 b net@8 3.932
-Rres@3 net@8 net@11 7.864
-.ENDS wire-C_0_011f-680_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-680_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-680_5-R_34_667m
-.ENDS wire90-680_5-layer_1-width_3
-
-*** CELL: countersL:cntScnFour{sch}
-.SUBCKT cntScnFour cin ctgLO out p1p p2p sin
-XcntScnOn@0 net@88 ctgLO net@40 p1p p2p net@88 cntScnOne
-XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
-XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
-XcntScnOn@3 net@94 ctgLO out p1p p2p net@94 cntScnOne
-Xwire90@4 net@40 net@94 wire90-668_5-layer_1-width_3
-Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
-Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
-.ENDS cntScnFour
-
-*** CELL: countersL:cntScnThree{sch}
-.SUBCKT cntScnThree cin ctgLO out p1p p2p sin
-XcntScnOn@0 net@88 ctgLO out p1p p2p net@88 cntScnOne
-XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
-XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
-Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
-Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
-.ENDS cntScnThree
-
-*** CELL: countersL:cntScnTwelve{sch}
-.SUBCKT cntScnTwelve cin ctgLO out p1p p2p sin
-XcntScnFo@0 net@60 ctgLO out p1p p2p net@60 cntScnFour
-XcntScnFo@1 cin ctgLO net@43 p1p p2p sin cntScnFour
-XcntScnFo@2 net@61 ctgLO net@46 p1p p2p net@61 cntScnFour
-Xwire90@5 net@43 net@61 wire90-668_5-layer_1-width_3
-Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3
-.ENDS cntScnTwelve
-
-*** CELL: countersL:instructionCount{sch}
-.SUBCKT instructionCount cin count fin fout sid[1] sid[2] sid[3] sid[4]
-+sid[5] sid[6] sid[7] sid[8] sid[9] sod[1]
-XcntContr@0 ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
-+sid[7] sid[8] sid[9] sod[1] cntShift
-XcntFreq@0 count ctgLO fin fout net@77 cntFreq
-XcntScnFo@1 cin ctgLO net@1 myp1p myp2p sid[1] cntScnFour
-XcntScnTh@0 net@77 ctgLO net@78 myp1p myp2p net@77 cntScnThree
-XcntScnTw@3 net@2 ctgLO net@124 myp1p myp2p net@2 cntScnTwelve
-XcntScnTw@5 net@136 ctgLO net@144 myp1p myp2p net@136 cntScnTwelve
-Xwire90@0 net@1 net@2 wire90-506_4-layer_1-width_3
-Xwire90@1 net@124 net@77 wire90-506_4-layer_1-width_3
-Xwire90@2 net@78 net@136 wire90-506_4-layer_1-width_3
-Xwire90@3 net@144 sod[1] wire90-506_4-layer_1-width_3
-.ENDS instructionCount
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-146_1-R_34_667m a b
-Ccap@0 gnd net@14 0.536f
-Ccap@1 gnd net@8 0.536f
-Ccap@2 gnd net@11 0.536f
-Rres@0 net@14 a 0.844
-Rres@1 net@11 net@14 1.688
-Rres@2 b net@8 0.844
-Rres@3 net@8 net@11 1.688
-.ENDS wire-C_0_011f-146_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-146_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-146_1-R_34_667m
-.ENDS wire90-146_1-layer_1-width_3
-
-*** CELL: latchesK:raw1inLatchF{sch}
-.SUBCKT raw1inLatchF hcl in[1] out[F]
-XlatchFlo@0 out[F] net@58 latchKeep
-XlatchPoi@0 hcl in[1] out[F] net@45 latchPointF
-Xwire90@0 net@45 net@58 wire90-146_1-layer_1-width_3
-.ENDS raw1inLatchF
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_20 in out
-XNMOS@0 out in gnd NMOSx-X_20
-XPMOS@0 out in vdd PMOSx-X_20
-.ENDS inv-X_20
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_60 d g s
-MNMOSf@0 d g s gnd nch W='180*(1+ABN/sqrt(180*2))' L='2'
-+DELVTO='AVT0N/sqrt(180*2)'
-.ENDS NMOSx-X_60
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_60 d g s
-MPMOSf@0 d g s vdd pch W='360*(1+ABP/sqrt(360*2))' L='2'
-+DELVTO='AVT0P/sqrt(360*2)'
-.ENDS PMOSx-X_60
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_60 in out
-XNMOS@0 out in gnd NMOSx-X_60
-XPMOS@0 out in vdd PMOSx-X_60
-.ENDS inv-X_60
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-294_8-R_34_667m a b
-Ccap@0 gnd net@14 1.081f
-Ccap@1 gnd net@8 1.081f
-Ccap@2 gnd net@11 1.081f
-Rres@0 net@14 a 1.703
-Rres@1 net@11 net@14 3.407
-Rres@2 b net@8 1.703
-Rres@3 net@8 net@11 3.407
-.ENDS wire-C_0_011f-294_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-294_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-294_8-R_34_667m
-.ENDS wire90-294_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-546_2-R_34_667m a b
-Ccap@0 gnd net@14 2.003f
-Ccap@1 gnd net@8 2.003f
-Ccap@2 gnd net@11 2.003f
-Rres@0 net@14 a 3.156
-Rres@1 net@11 net@14 6.312
-Rres@2 b net@8 3.156
-Rres@3 net@8 net@11 6.312
-.ENDS wire-C_0_011f-546_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-546_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-546_2-R_34_667m
-.ENDS wire90-546_2-layer_1-width_3
-
-*** CELL: latchesK:latch1in60C{sch}
-.SUBCKT latch1in60C hcl inS[1] outS[1]
-Xhi2inLat@0 hcl inS[1] net@14 raw1inLatchF
-XinvLT@0 net@15 net@18 invLT-X_5
-XinvLT@1 net@16 net@19 inv-X_20
-XinvLT@2 net@17 outS[1] inv-X_60
-Xwire90@0 net@14 net@15 wire90-294_8-layer_1-width_3
-Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
-Xwire90@2 net@19 net@17 wire90-546_2-layer_1-width_3
-.ENDS latch1in60C
-
-*** CELL: registersM:addr1in60Cx7{sch}
-.SUBCKT addr1in60Cx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire
-Xlat[1] fire ain[1] aout[1] latch1in60C
-Xlat[2] fire ain[2] aout[2] latch1in60C
-Xlat[3] fire ain[3] aout[3] latch1in60C
-Xlat[4] fire ain[4] aout[4] latch1in60C
-Xlat[5] fire ain[5] aout[5] latch1in60C
-Xlat[6] fire ain[6] aout[6] latch1in60C
-Xlat[7] fire ain[7] aout[7] latch1in60C
-.ENDS addr1in60Cx7
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2330-R_34_667m a b
-Ccap@0 gnd net@14 8.543f
-Ccap@1 gnd net@8 8.543f
-Ccap@2 gnd net@11 8.543f
-Rres@0 net@14 a 13.462
-Rres@1 net@11 net@14 26.924
-Rres@2 b net@8 13.462
-Rres@3 net@8 net@11 26.924
-.ENDS wire-C_0_011f-2330-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2330-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2330-R_34_667m
-.ENDS wire90-2330-layer_1-width_3
-
-*** CELL: registersM:addr1in60Cx15{sch}
-.SUBCKT addr1in60Cx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fire
-Xaddr1in6@0 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
-+aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in60Cx7
-Xaddr1in6@1 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in60Cx7
-Xlatch1in@0 fire ain[TT] aout[TT] latch1in60C
-Xwire90@0 net@19 fire wire90-2330-layer_1-width_3
-Xwire90@1 fire net@17 wire90-2330-layer_1-width_3
-.ENDS addr1in60Cx15
-
-*** CELL: registersM:data1in60Cx18{sch}
-.SUBCKT data1in60Cx18 dcl in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xlat[1] dcl in[1] out[1] latch1in60C
-Xlat[2] dcl in[2] out[2] latch1in60C
-Xlat[3] dcl in[3] out[3] latch1in60C
-Xlat[4] dcl in[4] out[4] latch1in60C
-Xlat[5] dcl in[5] out[5] latch1in60C
-Xlat[6] dcl in[6] out[6] latch1in60C
-Xlat[7] dcl in[7] out[7] latch1in60C
-Xlat[8] dcl in[8] out[8] latch1in60C
-Xlat[9] dcl in[9] out[9] latch1in60C
-Xlat[10] dcl in[10] out[10] latch1in60C
-Xlat[11] dcl in[11] out[11] latch1in60C
-Xlat[12] dcl in[12] out[12] latch1in60C
-Xlat[13] dcl in[13] out[13] latch1in60C
-Xlat[14] dcl in[14] out[14] latch1in60C
-Xlat[15] dcl in[15] out[15] latch1in60C
-Xlat[16] dcl in[16] out[16] latch1in60C
-Xlat[17] dcl in[17] out[17] latch1in60C
-Xlat[18] dcl in[18] out[18] latch1in60C
-.ENDS data1in60Cx18
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2550-R_34_667m a b
-Ccap@0 gnd net@14 9.35f
-Ccap@1 gnd net@8 9.35f
-Ccap@2 gnd net@11 9.35f
-Rres@0 net@14 a 14.733
-Rres@1 net@11 net@14 29.467
-Rres@2 b net@8 14.733
-Rres@3 net@8 net@11 29.467
-.ENDS wire-C_0_011f-2550-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2550-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2550-R_34_667m
-.ENDS wire90-2550-layer_1-width_3
-
-*** CELL: registersM:data1in60Cx37{sch}
-.SUBCKT data1in60Cx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
-+out[5] out[6] out[7] out[8] out[9] take
-Xdata1in6@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] data1in60Cx18
-Xdata1in6@2 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] data1in60Cx18
-Xlatch1in@0 take in[19] out[19] latch1in60C
-Xwire90@2 take net@17 wire90-2550-layer_1-width_3
-Xwire90@3 net@19 take wire90-2550-layer_1-width_3
-.ENDS data1in60Cx37
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_25 d g s
-MPMOSf@0 d g s vdd pch W='150*(1+ABP/sqrt(150*2))' L='2'
-+DELVTO='AVT0P/sqrt(150*2)'
-.ENDS PMOSx-X_25
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_50 d g s
-MNMOSf@0 d g s gnd nch W='150*(1+ABN/sqrt(150*2))' L='2'
-+DELVTO='AVT0N/sqrt(150*2)'
-.ENDS NMOSx-X_50
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_25 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_50
-XNMOS@1 net@0 g gnd NMOSx-X_50
-.ENDS nms2-X_25
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_25 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_25
-XPMOS@1 out inb vdd PMOSx-X_25
-Xnms2@0 out ina inb nms2-X_25
-.ENDS nand2-X_25
-
-*** CELL: arbiterM:half2inArb{sch}
-.SUBCKT half2inArb cross grant[B] inA req[B]
-XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10
-XPMOSx@0 cross inA grant[B] NMOSx-X_10
-Xnor2n@0 inA req[B] cross nand2-X_25
-.ENDS half2inArb
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-830_7-R_34_667m a b
-Ccap@0 gnd net@14 3.046f
-Ccap@1 gnd net@8 3.046f
-Ccap@2 gnd net@11 3.046f
-Rres@0 net@14 a 4.8
-Rres@1 net@11 net@14 9.599
-Rres@2 b net@8 4.8
-Rres@3 net@8 net@11 9.599
-.ENDS wire-C_0_011f-830_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-830_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-830_7-R_34_667m
-.ENDS wire90-830_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-834_6-R_34_667m a b
-Ccap@0 gnd net@14 3.06f
-Ccap@1 gnd net@8 3.06f
-Ccap@2 gnd net@11 3.06f
-Rres@0 net@14 a 4.822
-Rres@1 net@11 net@14 9.644
-Rres@2 b net@8 4.822
-Rres@3 net@8 net@11 9.644
-.ENDS wire-C_0_011f-834_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-834_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-834_6-R_34_667m
-.ENDS wire90-834_6-layer_1-width_3
-
-*** CELL: arbiterM:arbiter2{sch}
-.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B]
-XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb
-XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb
-Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3
-Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3
-.ENDS arbiter2
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_100 d g s
-MNMOSf@0 d g s gnd nch W='300*(1+ABN/sqrt(300*2))' L='2'
-+DELVTO='AVT0N/sqrt(300*2)'
-.ENDS NMOSx-X_100
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_100 d g s
-MPMOSf@0 d g s vdd pch W='600*(1+ABP/sqrt(600*2))' L='2'
-+DELVTO='AVT0P/sqrt(600*2)'
-.ENDS PMOSx-X_100
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_100 in out
-XNMOS@0 out in gnd NMOSx-X_100
-XPMOS@0 out in vdd PMOSx-X_100
-.ENDS inv-X_100
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_15 d g s
-MPMOSf@0 d g s vdd pch W='90*(1+ABP/sqrt(90*2))' L='2'
-+DELVTO='AVT0P/sqrt(90*2)'
-.ENDS PMOSx-X_15
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_30 d g s
-MNMOSf@0 d g s gnd nch W='90*(1+ABN/sqrt(90*2))' L='2'
-+DELVTO='AVT0N/sqrt(90*2)'
-.ENDS NMOSx-X_30
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_15 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_30
-XNMOS@1 net@0 g gnd NMOSx-X_30
-.ENDS nms2-X_15
-
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_30 d g g2
-Xnms2@0 d g g2 nms2-X_15
-Xnms2@1 d g2 g nms2-X_15
-.ENDS nms2_sy-X_30
-
-*** CELL: redFive:nand2LT_sy{sch}
-.SUBCKT nand2LT_sy-X_30 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_15
-XPMOS@1 out inb vdd PMOSx-X_15
-Xnms2_sy@0 out ina inb nms2_sy-X_30
-.ENDS nand2LT_sy-X_30
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-399_2-R_34_667m a b
-Ccap@0 gnd net@14 1.464f
-Ccap@1 gnd net@8 1.464f
-Ccap@2 gnd net@11 1.464f
-Rres@0 net@14 a 2.306
-Rres@1 net@11 net@14 4.613
-Rres@2 b net@8 2.306
-Rres@3 net@8 net@11 4.613
-.ENDS wire-C_0_011f-399_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-399_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-399_2-R_34_667m
-.ENDS wire90-399_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1013_8-R_34_667m a b
-Ccap@0 gnd net@14 3.717f
-Ccap@1 gnd net@8 3.717f
-Ccap@2 gnd net@11 3.717f
-Rres@0 net@14 a 5.858
-Rres@1 net@11 net@14 11.715
-Rres@2 b net@8 5.858
-Rres@3 net@8 net@11 11.715
-.ENDS wire-C_0_011f-1013_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1013_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1013_8-R_34_667m
-.ENDS wire90-1013_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-468_3-R_34_667m a b
-Ccap@0 gnd net@14 1.717f
-Ccap@1 gnd net@8 1.717f
-Ccap@2 gnd net@11 1.717f
-Rres@0 net@14 a 2.706
-Rres@1 net@11 net@14 5.411
-Rres@2 b net@8 2.706
-Rres@3 net@8 net@11 5.411
-.ENDS wire-C_0_011f-468_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-468_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-468_3-R_34_667m
-.ENDS wire90-468_3-layer_1-width_3
-
-*** CELL: centersJ:ctrAND2in100LT{sch}
-.SUBCKT ctrAND2in100LT inA inB out
-Xinv@8 inB net@135 inv-X_10
-Xinv@9 inA net@139 inv-X_10
-Xinv@10 net@146 out inv-X_100
-Xnand2LT_@0 net@140 net@136 net@144 nand2LT_sy-X_30
-Xwire90@4 net@135 net@136 wire90-399_2-layer_1-width_3
-Xwire90@5 net@144 net@146 wire90-1013_8-layer_1-width_3
-Xwire90@6 net@139 net@140 wire90-468_3-layer_1-width_3
-.ENDS ctrAND2in100LT
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_20 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_40
-XNMOS@1 net@0 g gnd NMOSx-X_40
-.ENDS nms2-X_20
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_20 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_20
-XPMOS@1 out inb vdd PMOSx-X_20
-Xnms2@0 out ina inb nms2-X_20
-.ENDS nand2-X_20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-698_4-R_34_667m a b
-Ccap@0 gnd net@14 2.561f
-Ccap@1 gnd net@8 2.561f
-Ccap@2 gnd net@11 2.561f
-Rres@0 net@14 a 4.035
-Rres@1 net@11 net@14 8.07
-Rres@2 b net@8 4.035
-Rres@3 net@8 net@11 8.07
-.ENDS wire-C_0_011f-698_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-698_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-698_4-R_34_667m
-.ENDS wire90-698_4-layer_1-width_3
-
-*** CELL: driversM:dataDriver60{sch}
-.SUBCKT dataDriver60 inA inB out
-Xinv@0 net@8 out inv-X_60
-Xnand2@1 inA inB net@7 nand2-X_20
-Xwire90@0 net@7 net@8 wire90-698_4-layer_1-width_3
-.ENDS dataDriver60
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_9_999 d g s
-MPMOSf@0 d g s vdd pch W='59.994*(1+ABP/sqrt(59.994*2))' L='2'
-+DELVTO='AVT0P/sqrt(59.994*2)'
-.ENDS PMOSx-X_9_999
-
-*** CELL: redFive:pms3{sch}
-.SUBCKT pms3-X_3_333 d g g2 g3
-XPMOS@0 d g3 net@2 PMOSx-X_9_999
-XPMOS@1 net@2 g2 net@5 PMOSx-X_9_999
-XPMOS@2 net@5 g vdd PMOSx-X_9_999
-.ENDS pms3-X_3_333
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-243_6-R_34_667m a b
-Ccap@0 gnd net@14 0.893f
-Ccap@1 gnd net@8 0.893f
-Ccap@2 gnd net@11 0.893f
-Rres@0 net@14 a 1.407
-Rres@1 net@11 net@14 2.815
-Rres@2 b net@8 1.407
-Rres@3 net@8 net@11 2.815
-.ENDS wire-C_0_011f-243_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-243_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-243_6-R_34_667m
-.ENDS wire90-243_6-layer_1-width_3
-
-*** CELL: driversM:predDri60wMC{sch}
-.SUBCKT predDri60wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_60
-XNMOSx@1 pred mc gnd NMOSx-X_10
-Xinv@0 pred net@145 inv-X_10
-Xpms3@0 pred mc in net@174 pms3-X_3_333
-Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
-.ENDS predDri60wMC
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_16 d g s
-MNMOSf@0 d g s gnd nch W='48*(1+ABN/sqrt(48*2))' L='2'
-+DELVTO='AVT0N/sqrt(48*2)'
-.ENDS NMOSx-X_16
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_8 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_16
-XNMOS@1 net@0 g gnd NMOSx-X_16
-.ENDS nms2-X_8
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-627_9-R_34_667m a b
-Ccap@0 gnd net@14 2.302f
-Ccap@1 gnd net@8 2.302f
-Ccap@2 gnd net@11 2.302f
-Rres@0 net@14 a 3.628
-Rres@1 net@11 net@14 7.256
-Rres@2 b net@8 3.628
-Rres@3 net@8 net@11 7.256
-.ENDS wire-C_0_011f-627_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-627_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-627_9-R_34_667m
-.ENDS wire90-627_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-124_7-R_34_667m a b
-Ccap@0 gnd net@14 0.457f
-Ccap@1 gnd net@8 0.457f
-Ccap@2 gnd net@11 0.457f
-Rres@0 net@14 a 0.72
-Rres@1 net@11 net@14 1.441
-Rres@2 b net@8 0.72
-Rres@3 net@8 net@11 1.441
-.ENDS wire-C_0_011f-124_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-124_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-124_7-R_34_667m
-.ENDS wire90-124_7-layer_1-width_3
-
-*** CELL: driversM:sucANDdri60{sch}
-.SUBCKT sucANDdri60 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_60
-Xinv@0 succ net@71 inv-X_5
-Xnand2@0 inA inB net@67 nand2-X_10
-Xnms2@0 succ net@51 net@72 nms2-X_8
-Xwire90@0 net@67 net@51 wire90-627_9-layer_1-width_3
-Xwire90@1 net@72 net@71 wire90-124_7-layer_1-width_3
-.ENDS sucANDdri60
-
-*** CELL: wiresL:tranCap{sch}
-.SUBCKT tranCap
-MNMOSf@1 gnd vdd gnd gnd nch W='360*(1+ABN/sqrt(360*3))' L='3'
-+DELVTO='AVT0N/sqrt(360*3)'
-MPMOSf@2 vdd gnd vdd vdd pch W='720*(1+ABP/sqrt(720*3))' L='3'
-+DELVTO='AVT0P/sqrt(720*3)'
-.ENDS tranCap
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-175-R_34_667m a b
-Ccap@0 gnd net@14 0.642f
-Ccap@1 gnd net@8 0.642f
-Ccap@2 gnd net@11 0.642f
-Rres@0 net@14 a 1.011
-Rres@1 net@11 net@14 2.022
-Rres@2 b net@8 1.011
-Rres@3 net@8 net@11 2.022
-.ENDS wire-C_0_011f-175-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-175-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-175-R_34_667m
-.ENDS wire90-175-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-516_9-R_34_667m a b
-Ccap@0 gnd net@14 1.895f
-Ccap@1 gnd net@8 1.895f
-Ccap@2 gnd net@11 1.895f
-Rres@0 net@14 a 2.987
-Rres@1 net@11 net@14 5.973
-Rres@2 b net@8 2.987
-Rres@3 net@8 net@11 5.973
-.ENDS wire-C_0_011f-516_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-516_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-516_9-R_34_667m
-.ENDS wire90-516_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-160_4-R_34_667m a b
-Ccap@0 gnd net@14 0.588f
-Ccap@1 gnd net@8 0.588f
-Ccap@2 gnd net@11 0.588f
-Rres@0 net@14 a 0.927
-Rres@1 net@11 net@14 1.854
-Rres@2 b net@8 0.927
-Rres@3 net@8 net@11 1.854
-.ENDS wire-C_0_011f-160_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-160_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-160_4-R_34_667m
-.ENDS wire90-160_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-130_1-R_34_667m a b
-Ccap@0 gnd net@14 0.477f
-Ccap@1 gnd net@8 0.477f
-Ccap@2 gnd net@11 0.477f
-Rres@0 net@14 a 0.752
-Rres@1 net@11 net@14 1.503
-Rres@2 b net@8 0.752
-Rres@3 net@8 net@11 1.503
-.ENDS wire-C_0_011f-130_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-130_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-130_1-R_34_667m
-.ENDS wire90-130_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-142_6-R_34_667m a b
-Ccap@0 gnd net@14 0.523f
-Ccap@1 gnd net@8 0.523f
-Ccap@2 gnd net@11 0.523f
-Rres@0 net@14 a 0.824
-Rres@1 net@11 net@14 1.648
-Rres@2 b net@8 0.824
-Rres@3 net@8 net@11 1.648
-.ENDS wire-C_0_011f-142_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-142_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-142_6-R_34_667m
-.ENDS wire90-142_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-350_6-R_34_667m a b
-Ccap@0 gnd net@14 1.286f
-Ccap@1 gnd net@8 1.286f
-Ccap@2 gnd net@11 1.286f
-Rres@0 net@14 a 2.026
-Rres@1 net@11 net@14 4.051
-Rres@2 b net@8 2.026
-Rres@3 net@8 net@11 4.051
-.ENDS wire-C_0_011f-350_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-350_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-350_6-R_34_667m
-.ENDS wire90-350_6-layer_1-width_3
-
-*** CELL: gaspM:gaspDrain{sch}
-.SUBCKT gaspDrain clear fire go pred s[1] s[2] silent succ take tok
-Xarbiter2@0 net@374 net@353 pred net@375 arbiter2
-XctrAND2i@5 net@241 succ fire ctrAND2in100LT
-XdataDriv@0 tok fire take dataDriver60
-Xinv@1 go net@360 inv-X_10
-Xinv@4 pred net@472 inv-X_5
-Xinv@5 silent net@463 inv-X_10
-XinvI@0 net@357 net@409 inv-X_10
-XinvI@1 net@475 s[1] inv-X_10
-XpredDri6@1 fire clear pred predDri60wMC
-XsucANDdr@4 net@499 fire succ sucANDdri60
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xwire90@1 net@374 net@241 wire90-175-layer_1-width_3
-Xwire90@7 net@375 net@360 wire90-516_9-layer_1-width_3
-Xwire90@10 net@357 net@353 wire90-160_4-layer_1-width_3
-Xwire90@11 s[2] net@409 wire90-130_1-layer_1-width_3
-Xwire90@15 net@472 net@475 wire90-142_6-layer_1-width_3
-Xwire90@16 net@463 net@499 wire90-350_6-layer_1-width_3
-.ENDS gaspDrain
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_10 in out
-XNMOS@0 out in gnd NMOSx-X_20
-XPMOS@0 out in vdd PMOSx-X_10
-.ENDS invLT-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-282-R_34_667m a b
-Ccap@0 gnd net@14 1.034f
-Ccap@1 gnd net@8 1.034f
-Ccap@2 gnd net@11 1.034f
-Rres@0 net@14 a 1.629
-Rres@1 net@11 net@14 3.259
-Rres@2 b net@8 1.629
-Rres@3 net@8 net@11 3.259
-.ENDS wire-C_0_011f-282-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-282-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-282-R_34_667m
-.ENDS wire90-282-layer_1-width_3
-
-*** CELL: latchesK:latch1in10A{sch}
-.SUBCKT latch1in10A hcl in[1] out[1]
-Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
-XinvLT@0 net@18 out[1] invLT-X_10
-Xwire90@0 net@19 net@18 wire90-282-layer_1-width_3
-.ENDS latch1in10A
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-311_7-R_34_667m a b
-Ccap@0 gnd net@14 1.143f
-Ccap@1 gnd net@8 1.143f
-Ccap@2 gnd net@11 1.143f
-Rres@0 net@14 a 1.801
-Rres@1 net@11 net@14 3.602
-Rres@2 b net@8 1.801
-Rres@3 net@8 net@11 3.602
-.ENDS wire-C_0_011f-311_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-311_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-311_7-R_34_667m
-.ENDS wire90-311_7-layer_1-width_3
-
-*** CELL: latchesK:latch2in10Alo{sch}
-.SUBCKT latch2in10Alo hcl[A] hcl[B] inA[1] inB[1] out[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
-XinvLT@0 net@15 out[1] invLT-X_10
-Xwire90@0 dataBar net@15 wire90-311_7-layer_1-width_3
-.ENDS latch2in10Alo
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-218_4-R_34_667m a b
-Ccap@0 gnd net@14 0.801f
-Ccap@1 gnd net@8 0.801f
-Ccap@2 gnd net@11 0.801f
-Rres@0 net@14 a 1.262
-Rres@1 net@11 net@14 2.524
-Rres@2 b net@8 1.262
-Rres@3 net@8 net@11 2.524
-.ENDS wire-C_0_011f-218_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-218_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-218_4-R_34_667m
-.ENDS wire90-218_4-layer_1-width_3
-
-*** CELL: scanM:scanCellE{sch}
-.SUBCKT scanCellE dIn[1] p1p p2p rd sin sout
-Xlatch1in@0 p2p sin net@2 latch1in10A
-Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo
-Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3
-.ENDS scanCellE
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-297_6-R_34_667m a b
-Ccap@0 gnd net@14 1.091f
-Ccap@1 gnd net@8 1.091f
-Ccap@2 gnd net@11 1.091f
-Rres@0 net@14 a 1.719
-Rres@1 net@11 net@14 3.439
-Rres@2 b net@8 1.719
-Rres@3 net@8 net@11 3.439
-.ENDS wire-C_0_011f-297_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-297_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-297_6-R_34_667m
-.ENDS wire90-297_6-layer_1-width_3
-
-*** CELL: scanM:scanEx2{sch}
-.SUBCKT scanEx2 dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sor[1]
-XscanCell@3 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE
-XscanCell@4 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanCellE
-Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
-.ENDS scanEx2
-
-*** CELL: latchPartsK:latchPointFmcHI{sch}
-.SUBCKT latchPointFmcHI mc x[F] x[T]
-XPMOSx@0 gnd mc x[T] NMOSx-X_3
-XPMOSx@1 vdd mc x[F] NMOSx-X_6
-.ENDS latchPointFmcHI
-
-*** CELL: latchesK:raw2inLatchFmc{sch}
-.SUBCKT raw2inLatchFmc hcl inA[1] mc out[F]
-XlatchKee@0 out[F] net@63 latchKeep
-XlatchPoi@0 hcl inA[1] out[F] net@45 latchPointF
-XlatchPoi@1 mc out[F] net@45 latchPointFmcHI
-Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
-.ENDS raw2inLatchFmc
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-283-R_34_667m a b
-Ccap@0 gnd net@14 1.038f
-Ccap@1 gnd net@8 1.038f
-Ccap@2 gnd net@11 1.038f
-Rres@0 net@14 a 1.635
-Rres@1 net@11 net@14 3.27
-Rres@2 b net@8 1.635
-Rres@3 net@8 net@11 3.27
-.ENDS wire-C_0_011f-283-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-283-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-283-R_34_667m
-.ENDS wire90-283-layer_1-width_3
-
-*** CELL: latchesK:latch2in10Alomc{sch}
-.SUBCKT latch2in10Alomc hcl inA[1] mc out[1]
-Xhi2inLat@0 hcl inA[1] mc dataBar raw2inLatchFmc
-XinvLT@0 net@20 out[1] invLT-X_10
-Xwire90@0 dataBar net@20 wire90-283-layer_1-width_3
-.ENDS latch2in10Alomc
-
-*** CELL: scanM:scanCellF{sch}
-.SUBCKT scanCellF dout[1] mc p1p p2p rd sin sout wr
-Xlatch1in@0 p2p sin net@2 latch1in10A
-Xlatch2in@0 p1p rd net@10 dout[1] sout latch2in10Alo
-Xlatch2in@1 wr sout mc dout[1] latch2in10Alomc
-Xwire90@0 net@2 net@10 wire90-297_6-layer_1-width_3
-.ENDS scanCellF
-
-*** CELL: scanM:scanFx3{sch}
-.SUBCKT scanFx3 dout[1] dout[2] dout[3] sic[1] sic[2] sic[3] sic[4] sic[5]
-+sic[6] sic[7] sic[8] sic[9] soc[1]
-XscanCell@4 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4]
-+scanCellF
-XscanCell@5 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 net@31 sic[4]
-+scanCellF
-XscanCell@6 dout[3] sic[9] sic[3] sic[2] sic[5] net@33 soc[1] sic[4]
-+scanCellF
-Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3
-Xwire90@1 net@31 net@33 wire90-297_6-layer_1-width_3
-.ENDS scanFx3
-
-*** CELL: stagesM:drainStage{sch}
-.SUBCKT drainStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
-+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2]
-+sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4]
-+sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ
-Xaddr1in6@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@4 addr1in60Cx15
-Xdata1in6@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] net@5 data1in60Cx37
-XgaspDrai@0 clear net@4 go pred net@17[1] net@17[0] silent succ net@5 ain[TT]
-+gaspDrain
-XscanEx2v@1 net@17[1] net@17[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1] scanEx2
-XscanFx3@0 go clear silent sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] soc[1] scanFx3
-Xtc[1] tranCap
-Xtc[2] tranCap
-.ENDS drainStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-295_8-R_34_667m a b
-Ccap@0 gnd net@14 1.085f
-Ccap@1 gnd net@8 1.085f
-Ccap@2 gnd net@11 1.085f
-Rres@0 net@14 a 1.709
-Rres@1 net@11 net@14 3.418
-Rres@2 b net@8 1.709
-Rres@3 net@8 net@11 3.418
-.ENDS wire-C_0_011f-295_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-295_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-295_8-R_34_667m
-.ENDS wire90-295_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-555_8-R_34_667m a b
-Ccap@0 gnd net@14 2.038f
-Ccap@1 gnd net@8 2.038f
-Ccap@2 gnd net@11 2.038f
-Rres@0 net@14 a 3.211
-Rres@1 net@11 net@14 6.423
-Rres@2 b net@8 3.211
-Rres@3 net@8 net@11 6.423
-.ENDS wire-C_0_011f-555_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-555_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-555_8-R_34_667m
-.ENDS wire90-555_8-layer_1-width_3
-
-*** CELL: latchesK:latch2in60C{sch}
-.SUBCKT latch2in60C hcl[A] hcl[B] inA[1] inB[1] outS[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@14 raw2inLatchF
-XinvLT@0 net@15 net@18 invLT-X_5
-XinvLT@1 net@16 net@19 inv-X_20
-XinvLT@2 net@17 outS[1] inv-X_60
-Xwire90@0 net@14 net@15 wire90-295_8-layer_1-width_3
-Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
-Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3
-.ENDS latch2in60C
-
-*** CELL: latchGroupsK:latchWscM2{sch}
-.SUBCKT latchWscM2 hcl in[1] out[1] p1p p2p rd sin sout wr
-Xhi2inLat@1 hcl wr in[1] sout out[1] latch2in60C
-XscanCell@3 out[1] p1p p2p rd sin sout scanCellE
-.ENDS latchWscM2
-
-*** CELL: registersM:addr1in60Cx7scan{sch}
-.SUBCKT addr1in60Cx7scan ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7]
-+aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire p1p p2p rd sin
-+sout wr[A]
-Xla[1] fire ain[1] aout[1] p1p p2p rd sin xin[2] wr[A] latchWscM2
-Xla[2] fire ain[2] aout[2] p1p p2p rd xin[2] xin[3] wr[A] latchWscM2
-Xla[3] fire ain[3] aout[3] p1p p2p rd xin[3] xin[4] wr[A] latchWscM2
-Xla[4] fire ain[4] aout[4] p1p p2p rd xin[4] xin[5] wr[A] latchWscM2
-Xla[5] fire ain[5] aout[5] p1p p2p rd xin[5] xin[6] wr[A] latchWscM2
-Xla[6] fire ain[6] aout[6] p1p p2p rd xin[6] xin[7] wr[A] latchWscM2
-Xla[7] fire ain[7] aout[7] p1p p2p rd xin[7] sout wr[A] latchWscM2
-.ENDS addr1in60Cx7scan
-
-*** CELL: registersM:data1in60Cx18scan{sch}
-.SUBCKT data1in60Cx18scan dcl in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd sin
-+sout wr[D]
-Xla[1] dcl in[1] out[1] p1p p2p rd sin xin[2] wr[D] latchWscM2
-Xla[2] dcl in[2] out[2] p1p p2p rd xin[2] xin[3] wr[D] latchWscM2
-Xla[3] dcl in[3] out[3] p1p p2p rd xin[3] xin[4] wr[D] latchWscM2
-Xla[4] dcl in[4] out[4] p1p p2p rd xin[4] xin[5] wr[D] latchWscM2
-Xla[5] dcl in[5] out[5] p1p p2p rd xin[5] xin[6] wr[D] latchWscM2
-Xla[6] dcl in[6] out[6] p1p p2p rd xin[6] xin[7] wr[D] latchWscM2
-Xla[7] dcl in[7] out[7] p1p p2p rd xin[7] xin[8] wr[D] latchWscM2
-Xla[8] dcl in[8] out[8] p1p p2p rd xin[8] xin[9] wr[D] latchWscM2
-Xla[9] dcl in[9] out[9] p1p p2p rd xin[9] xin[10] wr[D] latchWscM2
-Xla[10] dcl in[10] out[10] p1p p2p rd xin[10] xin[11] wr[D] latchWscM2
-Xla[11] dcl in[11] out[11] p1p p2p rd xin[11] xin[12] wr[D] latchWscM2
-Xla[12] dcl in[12] out[12] p1p p2p rd xin[12] xin[13] wr[D] latchWscM2
-Xla[13] dcl in[13] out[13] p1p p2p rd xin[13] xin[14] wr[D] latchWscM2
-Xla[14] dcl in[14] out[14] p1p p2p rd xin[14] xin[15] wr[D] latchWscM2
-Xla[15] dcl in[15] out[15] p1p p2p rd xin[15] xin[16] wr[D] latchWscM2
-Xla[16] dcl in[16] out[16] p1p p2p rd xin[16] xin[17] wr[D] latchWscM2
-Xla[17] dcl in[17] out[17] p1p p2p rd xin[17] xin[18] wr[D] latchWscM2
-Xla[18] dcl in[18] out[18] p1p p2p rd xin[18] sout wr[D] latchWscM2
-.ENDS data1in60Cx18scan
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_4 d g s
-MNMOSf@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2'
-+DELVTO='AVT0N/sqrt(12*2)'
-.ENDS NMOSx-X_4
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_4 d g s
-MPMOSf@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2'
-+DELVTO='AVT0P/sqrt(24*2)'
-.ENDS PMOSx-X_4
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_4 in out
-XNMOS@0 out in gnd NMOSx-X_4
-XPMOS@0 out in vdd PMOSx-X_4
-.ENDS inv-X_4
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_30 d g s
-MPMOSf@0 d g s vdd pch W='180*(1+ABP/sqrt(180*2))' L='2'
-+DELVTO='AVT0P/sqrt(180*2)'
-.ENDS PMOSx-X_30
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_30 in out
-XNMOS@0 out in gnd NMOSx-X_30
-XPMOS@0 out in vdd PMOSx-X_30
-.ENDS inv-X_30
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_2_5 d g s
-MNMOSf@0 d g s gnd nch W='7.5*(1+ABN/sqrt(7.5*2))' L='2'
-+DELVTO='AVT0N/sqrt(7.5*2)'
-.ENDS NMOSx-X_2_5
-
-*** CELL: redFive:nor2HT_sy{sch}
-.SUBCKT nor2HT_sy-X_5 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_2_5
-XNMOS@1 out ina gnd NMOSx-X_2_5
-Xpms2_sy@0 out ina inb pms2_sy-X_5
-.ENDS nor2HT_sy-X_5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-252_6-R_34_667m a b
-Ccap@0 gnd net@14 0.926f
-Ccap@1 gnd net@8 0.926f
-Ccap@2 gnd net@11 0.926f
-Rres@0 net@14 a 1.459
-Rres@1 net@11 net@14 2.919
-Rres@2 b net@8 1.459
-Rres@3 net@8 net@11 2.919
-.ENDS wire-C_0_011f-252_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-252_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-252_6-R_34_667m
-.ENDS wire90-252_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-366_8-R_34_667m a b
-Ccap@0 gnd net@14 1.345f
-Ccap@1 gnd net@8 1.345f
-Ccap@2 gnd net@11 1.345f
-Rres@0 net@14 a 2.119
-Rres@1 net@11 net@14 4.239
-Rres@2 b net@8 2.119
-Rres@3 net@8 net@11 4.239
-.ENDS wire-C_0_011f-366_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-366_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-366_8-R_34_667m
-.ENDS wire90-366_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-176_4-R_34_667m a b
-Ccap@0 gnd net@14 0.647f
-Ccap@1 gnd net@8 0.647f
-Ccap@2 gnd net@11 0.647f
-Rres@0 net@14 a 1.019
-Rres@1 net@11 net@14 2.038
-Rres@2 b net@8 1.019
-Rres@3 net@8 net@11 2.038
-.ENDS wire-C_0_011f-176_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-176_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-176_4-R_34_667m
-.ENDS wire90-176_4-layer_1-width_3
-
-*** CELL: centersJ:ctrAND3in30{sch}
-.SUBCKT ctrAND3in30 inA inB inC out
-Xinv@4 inC net@30 inv-X_4
-Xinv@5 net@9 out inv-X_30
-Xnand2@0 net@19 net@15 net@27 nand2-X_10
-Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
-Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
-Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
-Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
-.ENDS ctrAND3in30
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_30 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_60
-XNMOS@1 net@0 g gnd NMOSx-X_60
-.ENDS nms2-X_30
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_30 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_30
-XPMOS@1 out inb vdd PMOSx-X_30
-Xnms2@0 out ina inb nms2-X_30
-.ENDS nand2-X_30
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_5 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_10
-XPMOS@1 d g2 net@2 PMOSx-X_10
-.ENDS pms2-X_5
-
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_10 d g g2
-Xpms2@0 d g g2 pms2-X_5
-Xpms2@1 d g2 g pms2-X_5
-.ENDS pms2_sy-X_10
-
-*** CELL: redFive:nor2HT_sy{sch}
-.SUBCKT nor2HT_sy-X_10 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_5
-XNMOS@1 out ina gnd NMOSx-X_5
-Xpms2_sy@0 out ina inb pms2_sy-X_10
-.ENDS nor2HT_sy-X_10
-
-*** CELL: centersJ:ctrAND3in100A{sch}
-.SUBCKT ctrAND3in100A inA inB inC out
-Xinv@4 inC net@30 inv-X_10
-Xinv@5 net@9 out inv-X_100
-Xnand2@0 net@19 net@15 net@27 nand2-X_30
-Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_10
-Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
-Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
-Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
-.ENDS ctrAND3in100A
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-918_6-R_34_667m a b
-Ccap@0 gnd net@14 3.368f
-Ccap@1 gnd net@8 3.368f
-Ccap@2 gnd net@11 3.368f
-Rres@0 net@14 a 5.307
-Rres@1 net@11 net@14 10.615
-Rres@2 b net@8 5.307
-Rres@3 net@8 net@11 10.615
-.ENDS wire-C_0_011f-918_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-918_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-918_6-R_34_667m
-.ENDS wire90-918_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1177-R_34_667m a b
-Ccap@0 gnd net@14 4.316f
-Ccap@1 gnd net@8 4.316f
-Ccap@2 gnd net@11 4.316f
-Rres@0 net@14 a 6.8
-Rres@1 net@11 net@14 13.601
-Rres@2 b net@8 6.8
-Rres@3 net@8 net@11 13.601
-.ENDS wire-C_0_011f-1177-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1177-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1177-R_34_667m
-.ENDS wire90-1177-layer_1-width_3
-
-*** CELL: gaspM:fillScanControl{sch}
-.SUBCKT fillScanControl si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9]
-+so[1] wr[A] wr[D]
-XdataDriv@2 so[1] si[4] wr[D] dataDriver60
-XdataDriv@3 net@4 net@21 wr[A] dataDriver60
-XscanCell@2 scanCell@2_dIn[1] si[3] si[2] si[5] si[1] net@7 scanCellE
-XscanCell@3 scanCell@3_dIn[1] si[3] si[2] si[5] net@4 so[1] scanCellE
-Xwire90@0 net@7 net@4 wire90-918_6-layer_1-width_3
-Xwire90@1 net@21 si[4] wire90-1177-layer_1-width_3
-.ENDS fillScanControl
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-544_2-R_34_667m a b
-Ccap@0 gnd net@14 1.995f
-Ccap@1 gnd net@8 1.995f
-Ccap@2 gnd net@11 1.995f
-Rres@0 net@14 a 3.144
-Rres@1 net@11 net@14 6.289
-Rres@2 b net@8 3.144
-Rres@3 net@8 net@11 6.289
-.ENDS wire-C_0_011f-544_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-544_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-544_2-R_34_667m
-.ENDS wire90-544_2-layer_1-width_3
-
-*** CELL: driversM:latchDriver60{sch}
-.SUBCKT latchDriver60 in out
-Xinv@1 in net@16 inv-X_20
-XinvI@2 net@17 out inv-X_60
-Xwire90@0 net@16 net@17 wire90-544_2-layer_1-width_3
-.ENDS latchDriver60
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_10 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_20
-XPMOS@1 d g2 net@2 PMOSx-X_20
-.ENDS pms2-X_10
-
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_20 d g g2
-Xpms2@0 d g g2 pms2-X_10
-Xpms2@1 d g2 g pms2-X_10
-.ENDS pms2_sy-X_20
-
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_20 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_20
-XNMOS@1 out ina gnd NMOSx-X_20
-Xpms2_sy@0 out ina inb pms2_sy-X_20
-.ENDS nor2_sy-X_20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1001_8-R_34_667m a b
-Ccap@0 gnd net@14 3.673f
-Ccap@1 gnd net@8 3.673f
-Ccap@2 gnd net@11 3.673f
-Rres@0 net@14 a 5.788
-Rres@1 net@11 net@14 11.576
-Rres@2 b net@8 5.788
-Rres@3 net@8 net@11 11.576
-.ENDS wire-C_0_011f-1001_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1001_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1001_8-R_34_667m
-.ENDS wire90-1001_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-209-R_34_667m a b
-Ccap@0 gnd net@14 0.766f
-Ccap@1 gnd net@8 0.766f
-Ccap@2 gnd net@11 0.766f
-Rres@0 net@14 a 1.208
-Rres@1 net@11 net@14 2.415
-Rres@2 b net@8 1.208
-Rres@3 net@8 net@11 2.415
-.ENDS wire-C_0_011f-209-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-209-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-209-R_34_667m
-.ENDS wire90-209-layer_1-width_3
-
-*** CELL: driversM:sucORdri60{sch}
-.SUBCKT sucORdri60 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_60
-Xinv@0 succ net@71 inv-X_5
-Xnms2@0 succ net@51 net@72 nms2-X_8
-Xnor2_sy@0 inA inB net@67 nor2_sy-X_20
-Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
-Xwire90@1 net@72 net@71 wire90-209-layer_1-width_3
-.ENDS sucORdri60
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-602_3-R_34_667m a b
-Ccap@0 gnd net@14 2.208f
-Ccap@1 gnd net@8 2.208f
-Ccap@2 gnd net@11 2.208f
-Rres@0 net@14 a 3.48
-Rres@1 net@11 net@14 6.96
-Rres@2 b net@8 3.48
-Rres@3 net@8 net@11 6.96
-.ENDS wire-C_0_011f-602_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-602_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-602_3-R_34_667m
-.ENDS wire90-602_3-layer_1-width_3
-
-*** CELL: gaspM:gaspFill{sch}
-.SUBCKT gaspFill block fill fire pred s[1] s[2] si[1] si[2] si[3] si[4] si[5]
-+si[6] si[7] si[8] si[9] so[1] succ take wr[A] wr[D]
-XctrAND3i@1 net@602 succ fire fire[B] ctrAND3in30
-XctrAND3i@3 net@454 succ block fire ctrAND3in100A
-XfillScan@1 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] wr[A]
-+wr[D] fillScanControl
-Xinv@0 pred net@533 inv-X_5
-Xinv@1 fill net@537 inv-X_5
-XinvI@0 net@454 s[1] inv-X_10
-XinvI@1 net@602 s[2] inv-X_10
-XlatchDri@1 fire take latchDriver60
-XpredDri6@2 fire si[9] pred predDri60wMC
-XsucORdri@2 fire net@320 succ sucORdri60
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3
-Xwire90@12 net@533 net@454 wire90-602_3-layer_1-width_3
-Xwire90@15 fire[B] net@320 wire90-602_3-layer_1-width_3
-.ENDS gaspFill
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-185_4-R_34_667m a b
-Ccap@0 gnd net@14 0.68f
-Ccap@1 gnd net@8 0.68f
-Ccap@2 gnd net@11 0.68f
-Rres@0 net@14 a 1.071
-Rres@1 net@11 net@14 2.142
-Rres@2 b net@8 1.071
-Rres@3 net@8 net@11 2.142
-.ENDS wire-C_0_011f-185_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-185_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-185_4-R_34_667m
-.ENDS wire90-185_4-layer_1-width_3
-
-*** CELL: scanM:scanAmp{sch}
-.SUBCKT scanAmp in[1] out[1]
-Xinv@0 in[1] net@1 inv-X_5
-Xinv@1 net@2 out[1] inv-X_20
-Xwire90@0 net@1 net@2 wire90-185_4-layer_1-width_3
-.ENDS scanAmp
-
-*** CELL: scanM:scanAMPx5{sch}
-.SUBCKT scanAMPx5 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1]
-+so[2] so[3] so[4] so[5]
-Xsa[1] si[1] so[1] scanAmp
-Xsa[2] si[2] so[2] scanAmp
-Xsa[3] si[3] so[3] scanAmp
-Xsa[4] si[4] so[4] scanAmp
-Xsa[5] si[5] so[5] scanAmp
-.ENDS scanAMPx5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2500-R_34_667m a b
-Ccap@0 gnd net@14 9.167f
-Ccap@1 gnd net@8 9.167f
-Ccap@2 gnd net@11 9.167f
-Rres@0 net@14 a 14.444
-Rres@1 net@11 net@14 28.889
-Rres@2 b net@8 14.444
-Rres@3 net@8 net@11 28.889
-.ENDS wire-C_0_011f-2500-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2500-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2500-R_34_667m
-.ENDS wire90-2500-layer_1-width_3
-
-*** CELL: stagesM:fillStage{sch}
-.SUBCKT fillStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
-+sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
-Xaddr1in6@0 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] net@13 sx[3] sx[2] sx[5] net@61
-+net@62 sx[A] addr1in60Cx7scan
-Xaddr1in6@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
-+aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@16 sx[3] sx[2] sx[5]
-+net@62 net@66 sx[A] addr1in60Cx7scan
-Xdata1in6@0 net@3 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] sx[3] sx[2] sx[5] net@66 net@65
-+sx[D] data1in60Cx18scan
-Xdata1in6@1 net@0 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] sx[3] sx[2]
-+sx[5] net@64 sz[1] sx[D] data1in60Cx18scan
-XgaspFill@0 block fill fire pred s[1] s[2] sx[1] sx[2] sx[3] sx[4] sx[5]
-+sid[6] sid[7] sid[8] sid[9] sy[1] succ net@8 sx[A] sx[D] gaspFill
-XlatchWsc@0 net@0 in[19] out[19] sx[3] sx[2] sx[5] net@65 net@64 sx[D]
-+latchWscM2
-XlatchWsc@1 net@13 ain[TT] aout[TT] sx[3] sx[2] sx[5] sy[1] net@61 sx[A]
-+latchWscM2
-XscanAMPx@2 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9]
-+sx[1] sx[2] sx[3] sx[4] sx[5] scanAMPx5
-XscanAMPx@3 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1]
-+sod[2] sod[3] sod[4] sod[5] scanAMPx5
-XscanAMPx@4 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9]
-+net@139[8] soc[2] soc[3] soc[4] soc[5] scanAMPx5
-XscanAMPx@5 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+net@142[8] sor[2] sor[3] sor[4] sor[5] scanAMPx5
-XscanEx2@0 s[1] s[2] sir[9] net@142[8] sor[2] sor[3] sor[4] sor[5] sir[6]
-+sir[7] sir[8] sor[1] scanEx2
-XscanFx3@0 block extra fill net@139[8] soc[2] soc[3] soc[4] soc[5] sic[6]
-+sic[7] sic[8] sic[9] soc[1] scanFx3
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xwire90@1 net@8 net@0 wire90-2550-layer_1-width_3
-Xwire90@3 fire net@16 wire90-2500-layer_1-width_3
-Xwire90@4 net@3 net@8 wire90-2550-layer_1-width_3
-Xwire90@5 net@13 fire wire90-2500-layer_1-width_3
-.ENDS fillStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2080_4-R_34_667m a b
-Ccap@0 gnd net@14 7.628f
-Ccap@1 gnd net@8 7.628f
-Ccap@2 gnd net@11 7.628f
-Rres@0 net@14 a 12.02
-Rres@1 net@11 net@14 24.04
-Rres@2 b net@8 12.02
-Rres@3 net@8 net@11 24.04
-.ENDS wire-C_0_011f-2080_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2080_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2080_4-R_34_667m
-.ENDS wire90-2080_4-layer_1-width_3
-
-*** CELL: stageGroupsM:properStopper{sch}
-.SUBCKT properStopper ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
-+sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
-XdrainSta@1 net@65[41] net@65[40] net@65[39] net@65[38] net@65[37] net@65[50]
-+net@65[49] net@65[48] net@65[47] net@65[46] net@65[45] net@65[44] net@65[43]
-+net@65[42] net@65[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
-+net@65[27] net@65[26] net@65[25] net@65[24] net@65[23] net@65[22] net@65[21]
-+net@65[20] net@65[19] net@65[18] net@65[36] net@65[17] net@65[16] net@65[15]
-+net@65[14] net@65[13] net@65[12] net@65[11] net@65[10] net@65[9] net@65[8]
-+net@65[35] net@65[7] net@65[6] net@65[5] net@65[4] net@65[3] net@65[2]
-+net@65[1] net@65[0] net@65[34] net@65[33] net@65[32] net@65[31] net@65[30]
-+net@65[29] net@65[28] out[10] out[11] out[12] out[13] out[14] out[15] out[16]
-+out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24]
-+out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32]
-+out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7]
-+out[8] out[9] net@42 net@3[8] soc[2] soc[3] soc[4] soc[5] sic[6] sic[7]
-+sic[8] sic[9] net@2[8] sor[2] sor[3] sor[4] sor[5] sir[6] sir[7] sir[8]
-+sir[9] soc[1] sor[1] succ drainStage
-XfillStag@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@65[41] net@65[40]
-+net@65[39] net@65[38] net@65[37] net@65[50] net@65[49] net@65[48] net@65[47]
-+net@65[46] net@65[45] net@65[44] net@65[43] net@65[42] net@65[51] extra fire
-+in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1]
-+in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2]
-+in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] in[4] in[5]
-+in[6] in[7] in[8] in[9] net@65[27] net@65[26] net@65[25] net@65[24]
-+net@65[23] net@65[22] net@65[21] net@65[20] net@65[19] net@65[18] net@65[36]
-+net@65[17] net@65[16] net@65[15] net@65[14] net@65[13] net@65[12] net@65[11]
-+net@65[10] net@65[9] net@65[8] net@65[35] net@65[7] net@65[6] net@65[5]
-+net@65[4] net@65[3] net@65[2] net@65[1] net@65[0] net@65[34] net@65[33]
-+net@65[32] net@65[31] net@65[30] net@65[29] net@65[28] pred sic[1] sic[2]
-+sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4]
-+sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] net@3[8] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
-+sod[3] sod[4] sod[5] net@2[8] sor[2] sor[3] sor[4] sor[5] net@41 fillStage
-Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3
-.ENDS properStopper
-
-*** CELL: stageGroupsM:fillDrainCount{sch}
-.SUBCKT fillDrainCount ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14]
-+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
-+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
-+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
-+sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
-Xinstruct@0 net@53 net@48 fin fout net@61[8] sod[2] sod[3] sod[4] sod[5]
-+sid[6] sid[7] sid[8] sid[9] sod[1] instructionCount
-XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@86 net@53 in[10] in[11] in[12] in[13] in[14]
-+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
-+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
-+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] net@61[8]
-+sod[2] sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
-+properStopper
-Xwire90@1 net@86 net@48 wire90-2080_4-layer_1-width_3
-.ENDS fillDrainCount
-
-*** CELL: scanM:scanCap{sch}
-.SUBCKT scanCap si[1] si[2] si[3] si[4] si[5] si[9]
-.ENDS scanCap
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-123_7-R_34_667m a b
-Ccap@0 gnd net@14 0.454f
-Ccap@1 gnd net@8 0.454f
-Ccap@2 gnd net@11 0.454f
-Rres@0 net@14 a 0.715
-Rres@1 net@11 net@14 1.429
-Rres@2 b net@8 0.715
-Rres@3 net@8 net@11 1.429
-.ENDS wire-C_0_011f-123_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-123_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-123_7-R_34_667m
-.ENDS wire90-123_7-layer_1-width_3
-
-*** CELL: latchPartsK:latchPointT{sch}
-.SUBCKT latchPointT hcl in[1] x[F] x[T]
-XPMOSx@0 in[1] hcl x[T] NMOSx-X_6
-XPMOSx@1 net@8 hcl x[F] NMOSx-X_3
-Xinv@0 in[1] net@105 invLT-X_5
-Xwire90@0 net@105 net@8 wire90-123_7-layer_1-width_3
-.ENDS latchPointT
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-180_9-R_34_667m a b
-Ccap@0 gnd net@14 0.663f
-Ccap@1 gnd net@8 0.663f
-Ccap@2 gnd net@11 0.663f
-Rres@0 net@14 a 1.045
-Rres@1 net@11 net@14 2.09
-Rres@2 b net@8 1.045
-Rres@3 net@8 net@11 2.09
-.ENDS wire-C_0_011f-180_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-180_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-180_9-R_34_667m
-.ENDS wire90-180_9-layer_1-width_3
-
-*** CELL: latchesK:raw1inLatchT{sch}
-.SUBCKT raw1inLatchT hcl[A] inA[1] out[T]
-XlatchFlo@0 out[T] net@29 latchKeep
-XlatchPoi@0 hcl[A] inA[1] net@7 out[T] latchPointT
-Xwire90@0 net@7 net@29 wire90-180_9-layer_1-width_3
-.ENDS raw1inLatchT
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-250_9-R_34_667m a b
-Ccap@0 gnd net@14 0.92f
-Ccap@1 gnd net@8 0.92f
-Ccap@2 gnd net@11 0.92f
-Rres@0 net@14 a 1.45
-Rres@1 net@11 net@14 2.899
-Rres@2 b net@8 1.45
-Rres@3 net@8 net@11 2.899
-.ENDS wire-C_0_011f-250_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-250_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-250_9-R_34_667m
-.ENDS wire90-250_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-214_6-R_34_667m a b
-Ccap@0 gnd net@14 0.787f
-Ccap@1 gnd net@8 0.787f
-Ccap@2 gnd net@11 0.787f
-Rres@0 net@14 a 1.24
-Rres@1 net@11 net@14 2.48
-Rres@2 b net@8 1.24
-Rres@3 net@8 net@11 2.48
-.ENDS wire-C_0_011f-214_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-214_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-214_6-R_34_667m
-.ENDS wire90-214_6-layer_1-width_3
-
-*** CELL: latchesK:latch1in20B{sch}
-.SUBCKT latch1in20B hcl in[1] out[1]
-Xhi2inLat@0 hcl in[1] net@19 raw1inLatchT
-Xinv@0 net@23 out[1] inv-X_20
-XinvLT@0 net@18 net@25 inv-X_5
-Xwire90@0 net@19 net@18 wire90-250_9-layer_1-width_3
-Xwire90@1 net@25 net@23 wire90-214_6-layer_1-width_3
-.ENDS latch1in20B
-
-*** CELL: registersM:addr1in20Bx7{sch}
-.SUBCKT addr1in20Bx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire
-Xlat[1] fire ain[1] aout[1] latch1in20B
-Xlat[2] fire ain[2] aout[2] latch1in20B
-Xlat[3] fire ain[3] aout[3] latch1in20B
-Xlat[4] fire ain[4] aout[4] latch1in20B
-Xlat[5] fire ain[5] aout[5] latch1in20B
-Xlat[6] fire ain[6] aout[6] latch1in20B
-Xlat[7] fire ain[7] aout[7] latch1in20B
-.ENDS addr1in20Bx7
-
-*** CELL: registersM:addr1in20Bx15{sch}
-.SUBCKT addr1in20Bx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fire
-Xaddr1in2@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
-+aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in20Bx7
-Xaddr1in2@2 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in20Bx7
-Xlatch1in@1 fire ain[TT] aout[TT] latch1in20B
-Xwire90@0 net@19 fire wire90-2330-layer_1-width_3
-Xwire90@1 fire net@17 wire90-2330-layer_1-width_3
-.ENDS addr1in20Bx15
-
-*** CELL: registersM:ins1in20Bx18{sch}
-.SUBCKT ins1in20Bx18 hcl in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xlx[1] hcl in[1] out[1] latch1in20B
-Xlx[2] hcl in[2] out[2] latch1in20B
-Xlx[3] hcl in[3] out[3] latch1in20B
-Xlx[4] hcl in[4] out[4] latch1in20B
-Xlx[5] hcl in[5] out[5] latch1in20B
-Xlx[6] hcl in[6] out[6] latch1in20B
-Xlx[7] hcl in[7] out[7] latch1in20B
-Xlx[8] hcl in[8] out[8] latch1in20B
-Xlx[9] hcl in[9] out[9] latch1in20B
-Xlx[10] hcl in[10] out[10] latch1in20B
-Xlx[11] hcl in[11] out[11] latch1in20B
-Xlx[12] hcl in[12] out[12] latch1in20B
-Xlx[13] hcl in[13] out[13] latch1in20B
-Xlx[14] hcl in[14] out[14] latch1in20B
-Xlx[15] hcl in[15] out[15] latch1in20B
-Xlx[16] hcl in[16] out[16] latch1in20B
-Xlx[17] hcl in[17] out[17] latch1in20B
-Xlx[18] hcl in[18] out[18] latch1in20B
-.ENDS ins1in20Bx18
-
-*** CELL: registersM:data1in20Bx37{sch}
-.SUBCKT data1in20Bx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
-+out[5] out[6] out[7] out[8] out[9] take
-Xins1in20@0 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] ins1in20Bx18
-Xins1in20@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18
-Xlatch1in@1 take in[19] out[19] latch1in20B
-Xwire90@2 take net@17 wire90-2550-layer_1-width_3
-Xwire90@3 net@19 take wire90-2550-layer_1-width_3
-.ENDS data1in20Bx37
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_3_999 d g s
-MPMOSf@0 d g s vdd pch W='23.994*(1+ABP/sqrt(23.994*2))' L='2'
-+DELVTO='AVT0P/sqrt(23.994*2)'
-.ENDS PMOSx-X_3_999
-
-*** CELL: redFive:pms3{sch}
-.SUBCKT pms3-X_1_333 d g g2 g3
-XPMOS@0 d g3 net@2 PMOSx-X_3_999
-XPMOS@1 net@2 g2 net@5 PMOSx-X_3_999
-XPMOS@2 net@5 g vdd PMOSx-X_3_999
-.ENDS pms3-X_1_333
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-106_7-R_34_667m a b
-Ccap@0 gnd net@14 0.391f
-Ccap@1 gnd net@8 0.391f
-Ccap@2 gnd net@11 0.391f
-Rres@0 net@14 a 0.616
-Rres@1 net@11 net@14 1.233
-Rres@2 b net@8 0.616
-Rres@3 net@8 net@11 1.233
-.ENDS wire-C_0_011f-106_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-106_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-106_7-R_34_667m
-.ENDS wire90-106_7-layer_1-width_3
-
-*** CELL: driversM:predDri20wMC{sch}
-.SUBCKT predDri20wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_20
-XNMOSx@1 pred mc gnd NMOSx-X_4
-Xinv@0 pred net@145 inv-X_4
-Xpms3@0 pred net@177 in mc pms3-X_1_333
-Xwire90@0 net@177 net@145 wire90-106_7-layer_1-width_3
-.ENDS predDri20wMC
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_6 d g s
-MPMOSf@0 d g s vdd pch W='36*(1+ABP/sqrt(36*2))' L='2'
-+DELVTO='AVT0P/sqrt(36*2)'
-.ENDS PMOSx-X_6
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_6 in out
-XNMOS@0 out in gnd NMOSx-X_6
-XPMOS@0 out in vdd PMOSx-X_6
-.ENDS inv-X_6
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_2 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_4
-XNMOS@1 net@0 g gnd NMOSx-X_4
-.ENDS nms2-X_2
-
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_20 d g
-XPMOS@0 d g vdd PMOSx-X_20
-.ENDS pms1-X_20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-503_4-R_34_667m a b
-Ccap@0 gnd net@14 1.846f
-Ccap@1 gnd net@8 1.846f
-Ccap@2 gnd net@11 1.846f
-Rres@0 net@14 a 2.909
-Rres@1 net@11 net@14 5.817
-Rres@2 b net@8 2.909
-Rres@3 net@8 net@11 5.817
-.ENDS wire-C_0_011f-503_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-503_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-503_4-R_34_667m
-.ENDS wire90-503_4-layer_1-width_3
-
-*** CELL: driversM:sucDri20{sch}
-.SUBCKT sucDri20 in succ
-Xinv@1 succ net@94 inv-X_4
-Xinv@2 in net@110 inv-X_6
-Xnms2@0 succ net@117 net@109 nms2-X_2
-Xpms1@0 succ net@109 pms1-X_20
-Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
-Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3
-.ENDS sucDri20
-
-*** CELL: gaspM:gaspWeak{sch}
-.SUBCKT gaspWeak fire mc pred s[1] succ take tok
-XctrAND2i@0 net@10 succ fire ctrAND2in100LT
-XdataDriv@0 tok fire take dataDriver60
-Xinv@0 pred net@8 inv-X_5
-XinvI@0 net@10 s[1] inv-X_10
-XpredDri2@0 net@30 mc pred predDri20wMC
-XsucDri20@0 fire succ sucDri20
-Xwire90@0 net@8 net@10 wire90-602_3-layer_1-width_3
-Xwire90@1 net@30 fire wire90-602_3-layer_1-width_3
-.ENDS gaspWeak
-
-*** CELL: scanM:scanEx1{sch}
-.SUBCKT scanEx1 dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1]
-XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanCellE
-.ENDS scanEx1
-
-*** CELL: stagesM:weakStage{sch}
-.SUBCKT weakStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
-+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sir[1] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ
-Xaddr1in2@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@59 addr1in20Bx15
-Xdata1in2@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] net@47 data1in20Bx37
-XgaspWeak@0 net@59 sir[9] pred net@39 succ net@47 ain[TT] gaspWeak
-XscanEx1@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-.ENDS weakStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1243_9-R_34_667m a b
-Ccap@0 gnd net@14 4.561f
-Ccap@1 gnd net@8 4.561f
-Ccap@2 gnd net@11 4.561f
-Rres@0 net@14 a 7.187
-Rres@1 net@11 net@14 14.374
-Rres@2 b net@8 7.187
-Rres@3 net@8 net@11 14.374
-.ENDS wire-C_0_011f-1243_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1243_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1243_9-R_34_667m
-.ENDS wire90-1243_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1185_9-R_34_667m a b
-Ccap@0 gnd net@14 4.348f
-Ccap@1 gnd net@8 4.348f
-Ccap@2 gnd net@11 4.348f
-Rres@0 net@14 a 6.852
-Rres@1 net@11 net@14 13.704
-Rres@2 b net@8 6.852
-Rres@3 net@8 net@11 13.704
-.ENDS wire-C_0_011f-1185_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1185_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1185_9-R_34_667m
-.ENDS wire90-1185_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1249_9-R_34_667m a b
-Ccap@0 gnd net@14 4.583f
-Ccap@1 gnd net@8 4.583f
-Ccap@2 gnd net@11 4.583f
-Rres@0 net@14 a 7.222
-Rres@1 net@11 net@14 14.443
-Rres@2 b net@8 7.222
-Rres@3 net@8 net@11 14.443
-.ENDS wire-C_0_011f-1249_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1249_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1249_9-R_34_667m
-.ENDS wire90-1249_9-layer_1-width_3
-
-*** CELL: stageGroupsM:upDown8weak{sch}
-.SUBCKT upDown8weak ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1]
-+ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT]
-+ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] ainU[3] ainU[4]
-+ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] aoutD[10] aoutD[11]
-+aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5]
-+aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[TT] aoutU[10] aoutU[11] aoutU[12]
-+aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6]
-+aoutU[7] aoutU[8] aoutU[9] aoutU[TT] inD[10] inD[11] inD[12] inD[13] inD[14]
-+inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22]
-+inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30]
-+inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5]
-+inD[6] inD[7] inD[8] inD[9] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15]
-+inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23]
-+inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31]
-+inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6]
-+inU[7] inU[8] inU[9] outD[10] outD[11] outD[12] outD[13] outD[14] outD[15]
-+outD[16] outD[17] outD[18] outD[19] outD[1] outD[20] outD[21] outD[22]
-+outD[23] outD[24] outD[25] outD[26] outD[27] outD[28] outD[29] outD[2]
-+outD[30] outD[31] outD[32] outD[33] outD[34] outD[35] outD[36] outD[37]
-+outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] outU[10] outU[11]
-+outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19]
-+outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26]
-+outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33]
-+outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7]
-+outU[8] outU[9] predD predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1] succD succU
-XweakStag@18 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2]
-+ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] net@189[41]
-+net@189[40] net@189[39] net@189[38] net@189[37] net@189[50] net@189[49]
-+net@189[48] net@189[47] net@189[46] net@189[45] net@189[44] net@189[43]
-+net@189[42] net@189[51] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15]
-+inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23]
-+inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31]
-+inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6]
-+inU[7] inU[8] inU[9] net@189[27] net@189[26] net@189[25] net@189[24]
-+net@189[23] net@189[22] net@189[21] net@189[20] net@189[19] net@189[18]
-+net@189[36] net@189[17] net@189[16] net@189[15] net@189[14] net@189[13]
-+net@189[12] net@189[11] net@189[10] net@189[9] net@189[8] net@189[35]
-+net@189[7] net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1]
-+net@189[0] net@189[34] net@189[33] net@189[32] net@189[31] net@189[30]
-+net@189[29] net@189[28] predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] net@117[8] net@28 weakStage
-XweakStag@19 net@189[41] net@189[40] net@189[39] net@189[38] net@189[37]
-+net@189[50] net@189[49] net@189[48] net@189[47] net@189[46] net@189[45]
-+net@189[44] net@189[43] net@189[42] net@189[51] net@190[41] net@190[40]
-+net@190[39] net@190[38] net@190[37] net@190[50] net@190[49] net@190[48]
-+net@190[47] net@190[46] net@190[45] net@190[44] net@190[43] net@190[42]
-+net@190[51] net@189[27] net@189[26] net@189[25] net@189[24] net@189[23]
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-+net@256[17] net@256[16] net@256[15] net@256[14] net@256[13] net@256[12]
-+net@256[11] net@256[10] net@256[9] net@256[8] net@256[35] net@256[7]
-+net@256[6] net@256[5] net@256[4] net@256[3] net@256[2] net@256[1] net@256[0]
-+net@256[34] net@256[33] net@256[32] net@256[31] net@256[30] net@256[29]
-+net@256[28] net@229 predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@254[8] succD net@264 upDown8weak
-Xwire90@6 net@229 net@267 wire90-1185_9-layer_1-width_3
-Xwire90@18 net@264 net@263 wire90-1185_9-layer_1-width_3
-.ENDS northFifo
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_2 d g s
-MNMOSf@0 d g s gnd nch W='6*(1+ABN/sqrt(6*2))' L='2' DELVTO='AVT0N/sqrt(6*2)'
-.ENDS NMOSx-X_2
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_2 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_4
-XPMOS@1 d g2 net@2 PMOSx-X_4
-.ENDS pms2-X_2
-
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_4 d g g2
-Xpms2@0 d g g2 pms2-X_2
-Xpms2@1 d g2 g pms2-X_2
-.ENDS pms2_sy-X_4
-
-*** CELL: redFive:nor2HT_sy{sch}
-.SUBCKT nor2HT_sy-X_4 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_2
-XNMOS@1 out ina gnd NMOSx-X_2
-Xpms2_sy@0 out ina inb pms2_sy-X_4
-.ENDS nor2HT_sy-X_4
-
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_5 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_5
-XNMOS@1 out inb gnd NMOSx-X_5
-Xpms2@0 out ina inb pms2-X_5
-.ENDS nor2-X_5
-
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_5 ina inb out
-Xnor2@0 ina inb out nor2-X_5
-.ENDS nor2n-X_5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-238_2-R_34_667m a b
-Ccap@0 gnd net@14 0.873f
-Ccap@1 gnd net@8 0.873f
-Ccap@2 gnd net@11 0.873f
-Rres@0 net@14 a 1.376
-Rres@1 net@11 net@14 2.753
-Rres@2 b net@8 1.376
-Rres@3 net@8 net@11 2.753
-.ENDS wire-C_0_011f-238_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-238_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-238_2-R_34_667m
-.ENDS wire90-238_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-520-R_34_667m a b
-Ccap@0 gnd net@14 1.907f
-Ccap@1 gnd net@8 1.907f
-Ccap@2 gnd net@11 1.907f
-Rres@0 net@14 a 3.004
-Rres@1 net@11 net@14 6.009
-Rres@2 b net@8 3.004
-Rres@3 net@8 net@11 6.009
-.ENDS wire-C_0_011f-520-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-520-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-520-R_34_667m
-.ENDS wire90-520-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-222_3-R_34_667m a b
-Ccap@0 gnd net@14 0.815f
-Ccap@1 gnd net@8 0.815f
-Ccap@2 gnd net@11 0.815f
-Rres@0 net@14 a 1.284
-Rres@1 net@11 net@14 2.569
-Rres@2 b net@8 1.284
-Rres@3 net@8 net@11 2.569
-.ENDS wire-C_0_011f-222_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-222_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-222_3-R_34_667m
-.ENDS wire90-222_3-layer_1-width_3
-
-*** CELL: centersJ:ctrAND4in30{sch}
-.SUBCKT ctrAND4in30 inA inB inC inD out
-Xinv@1 net@3 out inv-X_30
-Xnand2@1 net@43 net@58 net@67 nand2-X_10
-Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
-Xnor2n@0 inD inC net@64 nor2n-X_5
-Xwire90@0 net@64 net@43 wire90-238_2-layer_1-width_3
-Xwire90@1 net@67 net@3 wire90-520-layer_1-width_3
-Xwire90@2 net@61 net@58 wire90-222_3-layer_1-width_3
-.ENDS ctrAND4in30
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_3 d g s
-MPMOSf@0 d g s vdd pch W='18*(1+ABP/sqrt(18*2))' L='2'
-+DELVTO='AVT0P/sqrt(18*2)'
-.ENDS PMOSx-X_3
-
-*** CELL: redFive:pms3{sch}
-.SUBCKT pms3-X_1 d g g2 g3
-XPMOS@0 d g3 net@2 PMOSx-X_3
-XPMOS@1 net@2 g2 net@5 PMOSx-X_3
-XPMOS@2 net@5 g vdd PMOSx-X_3
-.ENDS pms3-X_1
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-162_4-R_34_667m a b
-Ccap@0 gnd net@14 0.595f
-Ccap@1 gnd net@8 0.595f
-Ccap@2 gnd net@11 0.595f
-Rres@0 net@14 a 0.938
-Rres@1 net@11 net@14 1.877
-Rres@2 b net@8 0.938
-Rres@3 net@8 net@11 1.877
-.ENDS wire-C_0_011f-162_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-162_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-162_4-R_34_667m
-.ENDS wire90-162_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-228_5-R_34_667m a b
-Ccap@0 gnd net@14 0.838f
-Ccap@1 gnd net@8 0.838f
-Ccap@2 gnd net@11 0.838f
-Rres@0 net@14 a 1.32
-Rres@1 net@11 net@14 2.64
-Rres@2 b net@8 1.32
-Rres@3 net@8 net@11 2.64
-.ENDS wire-C_0_011f-228_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-228_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-228_5-R_34_667m
-.ENDS wire90-228_5-layer_1-width_3
-
-*** CELL: latchesK:rsLatchA{sch}
-.SUBCKT rsLatchA mc out outBar reset set
-XNMOSx@0 net@193 reset gnd NMOSx-X_10
-XNMOSx@1 net@188 mc gnd NMOSx-X_4
-XPMOSx@3 net@188 net@177 vdd PMOSx-X_10
-Xinv@0 net@193 outBar inv-X_10
-Xinv@1 set net@213 inv-X_4
-Xinv@2 outBar out inv-X_10
-Xnms2@0 net@188 outBar net@177 nms2-X_2
-Xpms3@0 net@193 mc outBar reset pms3-X_1
-Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3
-Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3
-.ENDS rsLatchA
-
-*** CELL: driversM:sucORdri20{sch}
-.SUBCKT sucORdri20 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_20
-Xinv@0 succ net@71 inv-X_4
-Xnms2@0 succ net@73 net@51 nms2-X_2
-Xnor2_sy@0 inA inB net@67 nor2_sy-X_5
-Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
-Xwire90@1 net@73 net@71 wire90-209-layer_1-width_3
-.ENDS sucORdri20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-468-R_34_667m a b
-Ccap@0 gnd net@14 1.716f
-Ccap@1 gnd net@8 1.716f
-Ccap@2 gnd net@11 1.716f
-Rres@0 net@14 a 2.704
-Rres@1 net@11 net@14 5.408
-Rres@2 b net@8 2.704
-Rres@3 net@8 net@11 5.408
-.ENDS wire-C_0_011f-468-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-468-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-468-R_34_667m
-.ENDS wire90-468-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-347_9-R_34_667m a b
-Ccap@0 gnd net@14 1.276f
-Ccap@1 gnd net@8 1.276f
-Ccap@2 gnd net@11 1.276f
-Rres@0 net@14 a 2.01
-Rres@1 net@11 net@14 4.02
-Rres@2 b net@8 2.01
-Rres@3 net@8 net@11 4.02
-.ENDS wire-C_0_011f-347_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-347_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-347_9-R_34_667m
-.ENDS wire90-347_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-450_6-R_34_667m a b
-Ccap@0 gnd net@14 1.652f
-Ccap@1 gnd net@8 1.652f
-Ccap@2 gnd net@11 1.652f
-Rres@0 net@14 a 2.603
-Rres@1 net@11 net@14 5.207
-Rres@2 b net@8 2.603
-Rres@3 net@8 net@11 5.207
-.ENDS wire-C_0_011f-450_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-450_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-450_6-R_34_667m
-.ENDS wire90-450_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-603_6-R_34_667m a b
-Ccap@0 gnd net@14 2.213f
-Ccap@1 gnd net@8 2.213f
-Ccap@2 gnd net@11 2.213f
-Rres@0 net@14 a 3.487
-Rres@1 net@11 net@14 6.975
-Rres@2 b net@8 3.487
-Rres@3 net@8 net@11 6.975
-.ENDS wire-C_0_011f-603_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-603_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-603_6-R_34_667m
-.ENDS wire90-603_6-layer_1-width_3
-
-*** CELL: gaspM:anAltEnd{sch}
-.SUBCKT anAltEnd fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ
-XctrAND4i@2 net@1013 succ net@1133 fire[B] fire[A] ctrAND4in30
-XctrAND4i@3 net@1007 succ fire[A] net@1155 fire[B] ctrAND4in30
-Xinv@3 net@822 s[1] inv-X_10
-Xinv@4 net@824 s[3] inv-X_10
-Xinv@5 predA net@822 inv-X_5
-Xinv@6 predB net@824 inv-X_5
-Xinv@7 net@1133 s[2] inv-X_10
-XpredDri2@0 fire[A] mc predA predDri20wMC
-XpredDri2@1 fire[B] mc predB predDri20wMC
-XrsLatchA@1 mc net@1040 net@1082 fire[B] fire[A] rsLatchA
-XsucORdri@0 fire[A] fire[B] succ sucORdri20
-Xwire90@34 net@824 net@1007 wire90-468-layer_1-width_3
-Xwire90@35 net@822 net@1013 wire90-347_9-layer_1-width_3
-Xwire90@36 net@1155 net@1082 wire90-450_6-layer_1-width_3
-Xwire90@37 net@1133 net@1040 wire90-603_6-layer_1-width_3
-.ENDS anAltEnd
-
-*** CELL: latchesK:latch2in20A{sch}
-.SUBCKT latch2in20A hcl[A] hcl[B] inA[1] inB[1] out[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@36 raw2inLatchF
-XinvLT@1 net@16 out[1] inv-X_20
-Xwire90@1 net@36 net@16 wire90-242_1-layer_1-width_3
-.ENDS latch2in20A
-
-*** CELL: registersM:ins2in20Ax18{sch}
-.SUBCKT ins2in20Ax18 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
-+inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
-+inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
-+inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xlx[1] hcl[A] hcl[B] inA[1] inB[1] out[1] latch2in20A
-Xlx[2] hcl[A] hcl[B] inA[2] inB[2] out[2] latch2in20A
-Xlx[3] hcl[A] hcl[B] inA[3] inB[3] out[3] latch2in20A
-Xlx[4] hcl[A] hcl[B] inA[4] inB[4] out[4] latch2in20A
-Xlx[5] hcl[A] hcl[B] inA[5] inB[5] out[5] latch2in20A
-Xlx[6] hcl[A] hcl[B] inA[6] inB[6] out[6] latch2in20A
-Xlx[7] hcl[A] hcl[B] inA[7] inB[7] out[7] latch2in20A
-Xlx[8] hcl[A] hcl[B] inA[8] inB[8] out[8] latch2in20A
-Xlx[9] hcl[A] hcl[B] inA[9] inB[9] out[9] latch2in20A
-Xlx[10] hcl[A] hcl[B] inA[10] inB[10] out[10] latch2in20A
-Xlx[11] hcl[A] hcl[B] inA[11] inB[11] out[11] latch2in20A
-Xlx[12] hcl[A] hcl[B] inA[12] inB[12] out[12] latch2in20A
-Xlx[13] hcl[A] hcl[B] inA[13] inB[13] out[13] latch2in20A
-Xlx[14] hcl[A] hcl[B] inA[14] inB[14] out[14] latch2in20A
-Xlx[15] hcl[A] hcl[B] inA[15] inB[15] out[15] latch2in20A
-Xlx[16] hcl[A] hcl[B] inA[16] inB[16] out[16] latch2in20A
-Xlx[17] hcl[A] hcl[B] inA[17] inB[17] out[17] latch2in20A
-Xlx[18] hcl[A] hcl[B] inA[18] inB[18] out[18] latch2in20A
-.ENDS ins2in20Ax18
-
-*** CELL: registersM:ins2in20Ax36{sch}
-.SUBCKT ins2in20Ax36 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
-+inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22]
-+inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30]
-+inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6]
-+inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
-+inB[17] inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24]
-+inB[25] inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32]
-+inB[33] inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xins2in20@2 net@178 net@162 inA[28] inA[29] inA[30] inA[31] inA[32] inA[33]
-+inA[34] inA[35] inA[36] inA[19] inA[20] inA[21] inA[22] inA[23] inA[24]
-+inA[25] inA[26] inA[27] inB[28] inB[29] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[19] inB[20] inB[21] inB[22] inB[23] inB[24]
-+inB[25] inB[26] inB[27] out[28] out[29] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[19] out[20] out[21] out[22] out[23] out[24]
-+out[25] out[26] out[27] ins2in20Ax18
-Xins2in20@3 net@157 net@177 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax18
-Xwire90@0 net@178 hcl[A] wire90-2550-layer_1-width_3
-Xwire90@1 hcl[A] net@157 wire90-2550-layer_1-width_3
-Xwire90@2 net@162 hcl[B] wire90-2550-layer_1-width_3
-Xwire90@3 hcl[B] net@177 wire90-2550-layer_1-width_3
-.ENDS ins2in20Ax36
-
-*** CELL: scanM:scanEx3{sch}
-.SUBCKT scanEx3 dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1]
-XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE
-XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanCellE
-XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanCellE
-Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
-Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3
-.ENDS scanEx3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1336_2-R_34_667m a b
-Ccap@0 gnd net@14 4.899f
-Ccap@1 gnd net@8 4.899f
-Ccap@2 gnd net@11 4.899f
-Rres@0 net@14 a 7.72
-Rres@1 net@11 net@14 15.441
-Rres@2 b net@8 7.72
-Rres@3 net@8 net@11 15.441
-.ENDS wire-C_0_011f-1336_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1336_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1336_2-R_34_667m
-.ENDS wire90-1336_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1307-R_34_667m a b
-Ccap@0 gnd net@14 4.792f
-Ccap@1 gnd net@8 4.792f
-Ccap@2 gnd net@11 4.792f
-Rres@0 net@14 a 7.552
-Rres@1 net@11 net@14 15.103
-Rres@2 b net@8 7.552
-Rres@3 net@8 net@11 15.103
-.ENDS wire-C_0_011f-1307-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1307-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1307-R_34_667m
-.ENDS wire90-1307-layer_1-width_3
-
-*** CELL: stagesM:altEndDockStage{sch}
-.SUBCKT altEndDockStage inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23]
-+inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31]
-+inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
-+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
-+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] predA predB
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ
-XanAltEnd@1 fire[A] fire[B] sir[9] predA predB s[1] s[2] s[3] succ anAltEnd
-Xins2in20@0 take[A] take[B] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23]
-+inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31]
-+inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
-+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
-+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36
-XlatchDri@2 net@3 net@27 latchDriver60
-XlatchDri@3 net@7 net@23 latchDriver60
-XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sor[1] scanEx3
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-Xtc[10] tranCap
-Xtc[11] tranCap
-Xtc[12] tranCap
-Xtc[13] tranCap
-Xtc[14] tranCap
-Xtc[15] tranCap
-Xtc[16] tranCap
-Xtc[17] tranCap
-Xtc[18] tranCap
-Xtc[19] tranCap
-Xtc[20] tranCap
-Xtc[21] tranCap
-Xwire90@0 net@7 fire[B] wire90-1336_2-layer_1-width_3
-Xwire90@1 net@3 fire[A] wire90-1307-layer_1-width_3
-Xwire90@2 net@23 take[B] wire90-1336_2-layer_1-width_3
-Xwire90@3 net@27 take[A] wire90-1307-layer_1-width_3
-.ENDS altEndDockStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-237_2-R_34_667m a b
-Ccap@0 gnd net@14 0.87f
-Ccap@1 gnd net@8 0.87f
-Ccap@2 gnd net@11 0.87f
-Rres@0 net@14 a 1.37
-Rres@1 net@11 net@14 2.741
-Rres@2 b net@8 1.37
-Rres@3 net@8 net@11 2.741
-.ENDS wire-C_0_011f-237_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-237_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-237_2-R_34_667m
-.ENDS wire90-237_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-221_8-R_34_667m a b
-Ccap@0 gnd net@14 0.813f
-Ccap@1 gnd net@8 0.813f
-Ccap@2 gnd net@11 0.813f
-Rres@0 net@14 a 1.282
-Rres@1 net@11 net@14 2.563
-Rres@2 b net@8 1.282
-Rres@3 net@8 net@11 2.563
-.ENDS wire-C_0_011f-221_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-221_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-221_8-R_34_667m
-.ENDS wire90-221_8-layer_1-width_3
-
-*** CELL: centersJ:ctrAND4in30M{sch}
-.SUBCKT ctrAND4in30M inA inB inC inD out outM
-Xinv@1 outM out inv-X_30
-Xnand2@1 net@43 net@58 outM nand2-X_10
-Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
-Xnor2n@0 inD inC net@64 nor2n-X_5
-Xwire90@0 net@64 net@43 wire90-237_2-layer_1-width_3
-Xwire90@2 net@61 net@58 wire90-221_8-layer_1-width_3
-.ENDS ctrAND4in30M
-
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_10 d g g2
-Xnms2@0 d g g2 nms2-X_5
-Xnms2@1 d g2 g nms2-X_5
-.ENDS nms2_sy-X_10
-
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_10 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_10
-XPMOS@1 out ina vdd PMOSx-X_10
-Xnms2_sy@0 out ina inb nms2_sy-X_10
-.ENDS nand2_sy-X_10
-
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_10 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_10
-.ENDS nand2n_sy-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-700-R_34_667m a b
-Ccap@0 gnd net@14 2.567f
-Ccap@1 gnd net@8 2.567f
-Ccap@2 gnd net@11 2.567f
-Rres@0 net@14 a 4.044
-Rres@1 net@11 net@14 8.089
-Rres@2 b net@8 4.044
-Rres@3 net@8 net@11 8.089
-.ENDS wire-C_0_011f-700-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-700-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-700-R_34_667m
-.ENDS wire90-700-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-839_6-R_34_667m a b
-Ccap@0 gnd net@14 3.079f
-Ccap@1 gnd net@8 3.079f
-Ccap@2 gnd net@11 3.079f
-Rres@0 net@14 a 4.851
-Rres@1 net@11 net@14 9.702
-Rres@2 b net@8 4.851
-Rres@3 net@8 net@11 9.702
-.ENDS wire-C_0_011f-839_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-839_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-839_6-R_34_667m
-.ENDS wire90-839_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-438_2-R_34_667m a b
-Ccap@0 gnd net@14 1.607f
-Ccap@1 gnd net@8 1.607f
-Ccap@2 gnd net@11 1.607f
-Rres@0 net@14 a 2.532
-Rres@1 net@11 net@14 5.064
-Rres@2 b net@8 2.532
-Rres@3 net@8 net@11 5.064
-.ENDS wire-C_0_011f-438_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-438_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-438_2-R_34_667m
-.ENDS wire90-438_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-257_4-R_34_667m a b
-Ccap@0 gnd net@14 0.944f
-Ccap@1 gnd net@8 0.944f
-Ccap@2 gnd net@11 0.944f
-Rres@0 net@14 a 1.487
-Rres@1 net@11 net@14 2.974
-Rres@2 b net@8 1.487
-Rres@3 net@8 net@11 2.974
-.ENDS wire-C_0_011f-257_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-257_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-257_4-R_34_667m
-.ENDS wire90-257_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-458_8-R_34_667m a b
-Ccap@0 gnd net@14 1.682f
-Ccap@1 gnd net@8 1.682f
-Ccap@2 gnd net@11 1.682f
-Rres@0 net@14 a 2.651
-Rres@1 net@11 net@14 5.302
-Rres@2 b net@8 2.651
-Rres@3 net@8 net@11 5.302
-.ENDS wire-C_0_011f-458_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-458_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-458_8-R_34_667m
-.ENDS wire90-458_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-744_5-R_34_667m a b
-Ccap@0 gnd net@14 2.73f
-Ccap@1 gnd net@8 2.73f
-Ccap@2 gnd net@11 2.73f
-Rres@0 net@14 a 4.302
-Rres@1 net@11 net@14 8.603
-Rres@2 b net@8 4.302
-Rres@3 net@8 net@11 8.603
-.ENDS wire-C_0_011f-744_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-744_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-744_5-R_34_667m
-.ENDS wire90-744_5-layer_1-width_3
-
-*** CELL: gaspM:anAltStart{sch}
-.SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB
-XctrAND4i@1 net@634 succA fire[B] net@912 fire[A] net@866 ctrAND4in30M
-XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M
-Xinv@3 net@634 s[1] inv-X_10
-Xinv@4 pred net@787 inv-X_10
-Xinv@5 net@912 s[2] inv-X_10
-Xnand2n_s@0 net@143 net@410 net@422 nand2n_sy-X_10
-XpredDri2@0 net@815 mc pred predDri20wMC
-XrsLatchA@1 mc net@905 net@911 fire[B] fire[A] rsLatchA
-XsucDri20@0 fire[A] succA sucDri20
-XsucDri20@1 fire[B] succB sucDri20
-Xwire90@16 net@410 net@866 wire90-700-layer_1-width_3
-Xwire90@17 net@143 net@885 wire90-839_6-layer_1-width_3
-Xwire90@19 net@912 net@905 wire90-438_2-layer_1-width_3
-Xwire90@20 net@815 net@422 wire90-257_4-layer_1-width_3
-Xwire90@27 net@909 net@911 wire90-458_8-layer_1-width_3
-Xwire90@28 net@787 net@634 wire90-744_5-layer_1-width_3
-.ENDS anAltStart
-
-*** CELL: registersM:ins1in20Bx36{sch}
-.SUBCKT ins1in20Bx36 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9]
-Xins1in20@0 net@13 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18
-Xins1in20@1 net@11 in[28] in[29] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] out[28]
-+out[29] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[19]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ins1in20Bx18
-Xwire90@0 hcl[1] net@13 wire90-2550-layer_1-width_3
-Xwire90@1 hcl[1] net@11 wire90-2550-layer_1-width_3
-.ENDS ins1in20Bx36
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1300-R_34_667m a b
-Ccap@0 gnd net@14 4.767f
-Ccap@1 gnd net@8 4.767f
-Ccap@2 gnd net@11 4.767f
-Rres@0 net@14 a 7.511
-Rres@1 net@11 net@14 15.022
-Rres@2 b net@8 7.511
-Rres@3 net@8 net@11 15.022
-.ENDS wire-C_0_011f-1300-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1300-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1300-R_34_667m
-.ENDS wire90-1300-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1301_9-R_34_667m a b
-Ccap@0 gnd net@14 4.774f
-Ccap@1 gnd net@8 4.774f
-Ccap@2 gnd net@11 4.774f
-Rres@0 net@14 a 7.522
-Rres@1 net@11 net@14 15.044
-Rres@2 b net@8 7.522
-Rres@3 net@8 net@11 15.044
-.ENDS wire-C_0_011f-1301_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1301_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m
-.ENDS wire90-1301_9-layer_1-width_3
-
-*** CELL: stagesM:altStartDockStage{sch}
-.SUBCKT altStartDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13]
-+outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20]
-+outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28]
-+outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35]
-+outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] outB[10]
-+outB[11] outB[12] outB[13] outB[14] outB[15] outB[16] outB[17] outB[18]
-+outB[19] outB[1] outB[20] outB[21] outB[22] outB[23] outB[24] outB[25]
-+outB[26] outB[27] outB[28] outB[29] outB[2] outB[30] outB[31] outB[32]
-+outB[33] outB[34] outB[35] outB[36] outB[3] outB[4] outB[5] outB[6] outB[7]
-+outB[8] outB[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] sor[1] succA succB
-XanAltSta@1 fire[A] fire[B] sir[9] pred net@48[1] net@48[0] succA succB
-+anAltStart
-Xins1in20@0 net@23 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13]
-+outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20]
-+outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28]
-+outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35]
-+outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] ins1in20Bx36
-Xins1in20@1 net@25 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] outB[10] outB[11] outB[12] outB[13]
-+outB[14] outB[15] outB[16] outB[17] outB[18] outB[19] outB[1] outB[20]
-+outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28]
-+outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35]
-+outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] ins1in20Bx36
-XlatchDri@2 net@5 net@20 latchDriver60
-XlatchDri@3 net@6 net@22 latchDriver60
-XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1] scanEx2
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xwire90@0 fire[A] net@5 wire90-1300-layer_1-width_3
-Xwire90@1 fire[B] net@6 wire90-1301_9-layer_1-width_3
-Xwire90@2 net@20 net@23 wire90-1300-layer_1-width_3
-Xwire90@3 net@22 net@25 wire90-1300-layer_1-width_3
-.ENDS altStartDockStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-249_5-R_34_667m a b
-Ccap@0 gnd net@14 0.915f
-Ccap@1 gnd net@8 0.915f
-Ccap@2 gnd net@11 0.915f
-Rres@0 net@14 a 1.442
-Rres@1 net@11 net@14 2.883
-Rres@2 b net@8 1.442
-Rres@3 net@8 net@11 2.883
-.ENDS wire-C_0_011f-249_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-249_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-249_5-R_34_667m
-.ENDS wire90-249_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-355_8-R_34_667m a b
-Ccap@0 gnd net@14 1.305f
-Ccap@1 gnd net@8 1.305f
-Ccap@2 gnd net@11 1.305f
-Rres@0 net@14 a 2.056
-Rres@1 net@11 net@14 4.111
-Rres@2 b net@8 2.056
-Rres@3 net@8 net@11 4.111
-.ENDS wire-C_0_011f-355_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-355_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-355_8-R_34_667m
-.ENDS wire90-355_8-layer_1-width_3
-
-*** CELL: centersJ:ctrAND2in30{sch}
-.SUBCKT ctrAND2in30 inA inB out
-Xinv@3 net@9 out inv-X_30
-XinvI@1 net@7 net@8 inv-X_10
-Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4
-Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3
-Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3
-.ENDS ctrAND2in30
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-291_8-R_34_667m a b
-Ccap@0 gnd net@14 1.07f
-Ccap@1 gnd net@8 1.07f
-Ccap@2 gnd net@11 1.07f
-Rres@0 net@14 a 1.686
-Rres@1 net@11 net@14 3.372
-Rres@2 b net@8 1.686
-Rres@3 net@8 net@11 3.372
-.ENDS wire-C_0_011f-291_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-291_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-291_8-R_34_667m
-.ENDS wire90-291_8-layer_1-width_3
-
-*** CELL: gaspM:aStage{sch}
-.SUBCKT aStage fire mc pred s[1] succ
-XctrAND2i@4 net@494 succ fire ctrAND2in30
-Xinv@4 net@987 s[1] inv-X_10
-Xinv@5 pred net@987 inv-X_5
-XpredDri2@1 fire mc pred predDri20wMC
-XsucDri20@1 fire succ sucDri20
-Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3
-.ENDS aStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-791_7-R_34_667m a b
-Ccap@0 gnd net@14 2.903f
-Ccap@1 gnd net@8 2.903f
-Ccap@2 gnd net@11 2.903f
-Rres@0 net@14 a 4.574
-Rres@1 net@11 net@14 9.149
-Rres@2 b net@8 4.574
-Rres@3 net@8 net@11 9.149
-.ENDS wire-C_0_011f-791_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-791_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-791_7-R_34_667m
-.ENDS wire90-791_7-layer_1-width_3
-
-*** CELL: stagesM:plainDockStage{sch}
-.SUBCKT plainDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ take[1]
-XaStage@1 net@1 sir[9] pred net@41 succ aStage
-Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] ins1in20Bx36
-XlatchDri@1 fire[1] take[1] latchDriver60
-XscanEx1@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3
-.ENDS plainDockStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-414-R_34_667m a b
-Ccap@0 gnd net@14 1.518f
-Ccap@1 gnd net@8 1.518f
-Ccap@2 gnd net@11 1.518f
-Rres@0 net@14 a 2.392
-Rres@1 net@11 net@14 4.784
-Rres@2 b net@8 2.392
-Rres@3 net@8 net@11 4.784
-.ENDS wire-C_0_011f-414-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-414-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-414-R_34_667m
-.ENDS wire90-414-layer_1-width_3
-
-*** CELL: stageGroupsM:dockWagNine{sch}
-.SUBCKT dockWagNine in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1] succ take[4]
-XaltEndDo@0 net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21]
-+net@16[20] net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15]
-+net@16[14] net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8]
-+net@16[7] net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2]
-+net@16[1] net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29]
-+net@16[28] net@16[27] net@19[26] net@19[25] net@19[24] net@19[23] net@19[22]
-+net@19[21] net@19[20] net@19[19] net@19[18] net@19[17] net@19[35] net@19[16]
-+net@19[15] net@19[14] net@19[13] net@19[12] net@19[11] net@19[10] net@19[9]
-+net@19[8] net@19[7] net@19[34] net@19[6] net@19[5] net@19[4] net@19[3]
-+net@19[2] net@19[1] net@19[0] net@19[33] net@19[32] net@19[31] net@19[30]
-+net@19[29] net@19[28] net@19[27] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] net@69 net@58 net@134[8] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1] succ altEndDockStage
-XaltStart@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
-+in[5] in[6] in[7] in[8] in[9] net@21[26] net@21[25] net@21[24] net@21[23]
-+net@21[22] net@21[21] net@21[20] net@21[19] net@21[18] net@21[17] net@21[35]
-+net@21[16] net@21[15] net@21[14] net@21[13] net@21[12] net@21[11] net@21[10]
-+net@21[9] net@21[8] net@21[7] net@21[34] net@21[6] net@21[5] net@21[4]
-+net@21[3] net@21[2] net@21[1] net@21[0] net@21[33] net@21[32] net@21[31]
-+net@21[30] net@21[29] net@21[28] net@21[27] net@20[26] net@20[25] net@20[24]
-+net@20[23] net@20[22] net@20[21] net@20[20] net@20[19] net@20[18] net@20[17]
-+net@20[35] net@20[16] net@20[15] net@20[14] net@20[13] net@20[12] net@20[11]
-+net@20[10] net@20[9] net@20[8] net@20[7] net@20[34] net@20[6] net@20[5]
-+net@20[4] net@20[3] net@20[2] net@20[1] net@20[0] net@20[33] net@20[32]
-+net@20[31] net@20[30] net@20[29] net@20[28] net@20[27] pred sir[1] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@116[8] net@97 net@100
-+altStartDockStage
-XplainDoc@0 net@2[26] net@2[25] net@2[24] net@2[23] net@2[22] net@2[21]
-+net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16] net@2[15]
-+net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8] net@2[7]
-+net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1] net@2[0]
-+net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28] net@2[27]
-+net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21] net@3[20]
-+net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15] net@3[14]
-+net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] net@3[34]
-+net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0] net@3[33]
-+net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27] net@107
-+net@136[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@130[8]
-+net@106 take[5] plainDockStage
-XplainDoc@1 net@20[26] net@20[25] net@20[24] net@20[23] net@20[22] net@20[21]
-+net@20[20] net@20[19] net@20[18] net@20[17] net@20[35] net@20[16] net@20[15]
-+net@20[14] net@20[13] net@20[12] net@20[11] net@20[10] net@20[9] net@20[8]
-+net@20[7] net@20[34] net@20[6] net@20[5] net@20[4] net@20[3] net@20[2]
-+net@20[1] net@20[0] net@20[33] net@20[32] net@20[31] net@20[30] net@20[29]
-+net@20[28] net@20[27] net@2[26] net@2[25] net@2[24] net@2[23] net@2[22]
-+net@2[21] net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16]
-+net@2[15] net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8]
-+net@2[7] net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1]
-+net@2[0] net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28]
-+net@2[27] net@60 net@125[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@136[8] net@108 take[4] plainDockStage
-XplainDoc@2 net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21]
-+net@3[20] net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15]
-+net@3[14] net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7]
-+net@3[34] net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0]
-+net@3[33] net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27]
-+net@19[26] net@19[25] net@19[24] net@19[23] net@19[22] net@19[21] net@19[20]
-+net@19[19] net@19[18] net@19[17] net@19[35] net@19[16] net@19[15] net@19[14]
-+net@19[13] net@19[12] net@19[11] net@19[10] net@19[9] net@19[8] net@19[7]
-+net@19[34] net@19[6] net@19[5] net@19[4] net@19[3] net@19[2] net@19[1]
-+net@19[0] net@19[33] net@19[32] net@19[31] net@19[30] net@19[29] net@19[28]
-+net@19[27] net@105 net@130[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@134[8] net@104 take[6] plainDockStage
-XplainDoc@3 net@0[26] net@0[25] net@0[24] net@0[23] net@0[22] net@0[21]
-+net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16] net@0[15]
-+net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8] net@0[7]
-+net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1] net@0[0]
-+net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28] net@0[27]
-+net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21] net@1[20]
-+net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15] net@1[14]
-+net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[34]
-+net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[33]
-+net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27] net@109
-+net@127[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@128[8]
-+net@111 take[2] plainDockStage
-XplainDoc@4 net@21[26] net@21[25] net@21[24] net@21[23] net@21[22] net@21[21]
-+net@21[20] net@21[19] net@21[18] net@21[17] net@21[35] net@21[16] net@21[15]
-+net@21[14] net@21[13] net@21[12] net@21[11] net@21[10] net@21[9] net@21[8]
-+net@21[7] net@21[34] net@21[6] net@21[5] net@21[4] net@21[3] net@21[2]
-+net@21[1] net@21[0] net@21[33] net@21[32] net@21[31] net@21[30] net@21[29]
-+net@21[28] net@21[27] net@0[26] net@0[25] net@0[24] net@0[23] net@0[22]
-+net@0[21] net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16]
-+net@0[15] net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8]
-+net@0[7] net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1]
-+net@0[0] net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28]
-+net@0[27] net@64 net@116[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@127[8] net@110 take[1] plainDockStage
-XplainDoc@5 net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21]
-+net@1[20] net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15]
-+net@1[14] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7]
-+net@1[34] net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0]
-+net@1[33] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27]
-+net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21] net@16[20]
-+net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15] net@16[14]
-+net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8] net@16[7]
-+net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2] net@16[1]
-+net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29] net@16[28]
-+net@16[27] net@112 net@128[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@125[8] net@102 take[3] plainDockStage
-Xwire90@0 net@97 net@64 wire90-414-layer_1-width_3
-Xwire90@1 net@100 net@60 wire90-414-layer_1-width_3
-Xwire90@2 net@110 net@109 wire90-414-layer_1-width_3
-Xwire90@3 net@106 net@105 wire90-414-layer_1-width_3
-Xwire90@4 net@111 net@112 wire90-414-layer_1-width_3
-Xwire90@5 net@104 net@58 wire90-414-layer_1-width_3
-Xwire90@6 net@108 net@107 wire90-414-layer_1-width_3
-Xwire90@7 net@102 net@69 wire90-414-layer_1-width_3
-.ENDS dockWagNine
-
-*** CELL: centersJ:ctrAND3in30A{sch}
-.SUBCKT ctrAND3in30A inA inB inC out outM
-XinvI@1 outM out inv-X_30
-Xnand2_sy@0 net@15 inC outM nand2_sy-X_10
-Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
-Xwire90@0 net@6 net@15 wire90-414-layer_1-width_3
-.ENDS ctrAND3in30A
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_6_667 d g s
-MPMOSf@0 d g s vdd pch W='40.002*(1+ABP/sqrt(40.002*2))' L='2'
-+DELVTO='AVT0P/sqrt(40.002*2)'
-.ENDS PMOSx-X_6_667
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_20_001 d g s
-MNMOSf@0 d g s gnd nch W='60.003*(1+ABN/sqrt(60.003*2))' L='2'
-+DELVTO='AVT0N/sqrt(60.003*2)'
-.ENDS NMOSx-X_20_001
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_6_667 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_20_001
-XNMOS@1 net@7 g gnd NMOSx-X_20_001
-XNMOS@2 net@6 g2 net@7 NMOSx-X_20_001
-.ENDS nms3-X_6_667
-
-*** CELL: redFive:nand3{sch}
-.SUBCKT nand3-X_6_667 ina inb inc out
-XPMOS@0 out inc vdd PMOSx-X_6_667
-XPMOS@1 out inb vdd PMOSx-X_6_667
-XPMOS@2 out ina vdd PMOSx-X_6_667
-Xnms3@0 out ina inb inc nms3-X_6_667
-.ENDS nand3-X_6_667
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-309-R_34_667m a b
-Ccap@0 gnd net@14 1.133f
-Ccap@1 gnd net@8 1.133f
-Ccap@2 gnd net@11 1.133f
-Rres@0 net@14 a 1.785
-Rres@1 net@11 net@14 3.571
-Rres@2 b net@8 1.785
-Rres@3 net@8 net@11 3.571
-.ENDS wire-C_0_011f-309-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-309-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-309-R_34_667m
-.ENDS wire90-309-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-114_9-R_34_667m a b
-Ccap@0 gnd net@14 0.421f
-Ccap@1 gnd net@8 0.421f
-Ccap@2 gnd net@11 0.421f
-Rres@0 net@14 a 0.664
-Rres@1 net@11 net@14 1.328
-Rres@2 b net@8 0.664
-Rres@3 net@8 net@11 1.328
-.ENDS wire-C_0_011f-114_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-114_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-114_9-R_34_667m
-.ENDS wire90-114_9-layer_1-width_3
-
-*** CELL: driversM:suc3ANDdri20{sch}
-.SUBCKT suc3ANDdri20 inA inB inC succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_20
-Xinv@0 succ net@71 inv-X_4
-Xnand3@0 inA inB inC net@67 nand3-X_6_667
-Xnms2@0 succ net@75 net@51 nms2-X_2
-Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
-Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
-.ENDS suc3ANDdri20
-
-*** CELL: driversM:sucANDdri20{sch}
-.SUBCKT sucANDdri20 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_20
-Xinv@0 succ net@71 inv-X_4
-Xnand2@0 inA inB net@67 nand2-X_5
-Xnms2@0 succ net@75 net@51 nms2-X_2
-Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
-Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
-.ENDS sucANDdri20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-372_8-R_34_667m a b
-Ccap@0 gnd net@14 1.367f
-Ccap@1 gnd net@8 1.367f
-Ccap@2 gnd net@11 1.367f
-Rres@0 net@14 a 2.154
-Rres@1 net@11 net@14 4.308
-Rres@2 b net@8 2.154
-Rres@3 net@8 net@11 4.308
-.ENDS wire-C_0_011f-372_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-372_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-372_8-R_34_667m
-.ENDS wire90-372_8-layer_1-width_3
-
-*** CELL: gaspM:gaspEpi{sch}
-.SUBCKT gaspEpi epi[OTHER] epi[TAIL] epi[TORP] fire mc pred s[1] tailBit
-+tokenLO
-XctrAND3i@3 net@1068 epi[TORP] net@1082 fire net@1119 ctrAND3in30A
-Xinv@5 pred net@987 inv-X_5
-XinvI@0 net@987 s[1] inv-X_10
-XinvI@1 tokenLO net@1146 inv-X_5
-XinvI@3 tailBit net@1147 inv-X_5
-Xnor2n_sy@0 epi[TAIL] epi[OTHER] net@1079 nor2n_sy-X_5
-XpredDri2@0 fire mc pred predDri20wMC
-Xsuc3ANDd@0 tokenLO net@1148 fire epi[OTHER] suc3ANDdri20
-Xsuc3ANDd@1 tokenLO tailBit fire epi[TAIL] suc3ANDdri20
-XsucANDdr@1 net@1139 fire epi[TORP] sucANDdri20
-Xwire90@0 net@987 net@1068 wire90-372_8-layer_1-width_3
-Xwire90@3 net@1079 net@1082 wire90-372_8-layer_1-width_3
-Xwire90@4 net@1139 net@1146 wire90-372_8-layer_1-width_3
-Xwire90@6 net@1148 net@1147 wire90-372_8-layer_1-width_3
-.ENDS gaspEpi
-
-*** CELL: stagesM:epiDockStage{sch}
-.SUBCKT epiDockStage do[epi] epi[10] epi[11] epi[12] epi[13] epi[14] epi[15]
-+epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22] epi[23]
-+epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] epi[31]
-+epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] epi[7]
-+epi[8] epi[9] epi[OTHER] epi[TAIL] epi[TORP] in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] sir[1]
-+sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[epi]
-XanEpiSta@1 epi[OTHER] epi[TAIL] epi[TORP] net@5 sir[9] do[epi] net@47 in[28]
-+in[T] gaspEpi
-Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] epi[10] epi[11] epi[12] epi[13] epi[14]
-+epi[15] epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22]
-+epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30]
-+epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6]
-+epi[7] epi[8] epi[9] ins1in20Bx36
-XlatchDri@1 net@0 take[epi] latchDriver60
-XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1
-XtranCap@0 tranCap
-Xwire90@0 net@0 net@5 wire90-372_8-layer_1-width_3
-.ENDS epiDockStage
-
-*** CELL: redFive:nand2LT_sy{sch}
-.SUBCKT nand2LT_sy-X_10 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_5
-XPMOS@1 out inb vdd PMOSx-X_5
-Xnms2_sy@0 out ina inb nms2_sy-X_10
-.ENDS nand2LT_sy-X_10
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_12 d g s
-MNMOSf@0 d g s gnd nch W='36*(1+ABN/sqrt(36*2))' L='2'
-+DELVTO='AVT0N/sqrt(36*2)'
-.ENDS NMOSx-X_12
-
-*** CELL: gates3inM:nor3in6.6sym{sch}
-.SUBCKT nor3in6_6sym inA inB inC out
-XNMOSx@0 out inC gnd NMOSx-X_12
-XNMOSx@7 out inB gnd NMOSx-X_12
-XNMOSx@8 out inA gnd NMOSx-X_12
-Xpms3@0 out inA inB inC pms3-X_3_333
-Xpms3@1 out inC inB inA pms3-X_3_333
-.ENDS nor3in6_6sym
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-956_7-R_34_667m a b
-Ccap@0 gnd net@14 3.508f
-Ccap@1 gnd net@8 3.508f
-Ccap@2 gnd net@11 3.508f
-Rres@0 net@14 a 5.528
-Rres@1 net@11 net@14 11.055
-Rres@2 b net@8 5.528
-Rres@3 net@8 net@11 11.055
-.ENDS wire-C_0_011f-956_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-956_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-956_7-R_34_667m
-.ENDS wire90-956_7-layer_1-width_3
-
-*** CELL: oneHotM:onDeck{sch}
-.SUBCKT onDeck bits[ABORT] bits[HEAD] fire[od] flag[A][clr] flag[A][set]
-+flag[D][clr] flag[D][set] mc od[ABORT] od[HEAD] od[OTHER] pred s[1] s[2]
-Xinv@8 pred net@358 inv-X_5
-Xinv@9 bits[HEAD] net@441 inv-X_5
-Xinv@10 bits[ABORT] net@463 inv-X_5
-XinvI@2 net@317 s[2] inv-X_10
-XinvI@5 net@368 fire[od] inv-X_30
-XinvI@6 net@314 s[1] inv-X_10
-Xnand2LT_@2 net@371 net@374 net@367 nand2LT_sy-X_10
-Xnor2_sy@7 flag[A][set] flag[A][clr] net@305 nor2_sy-X_5
-Xnor2_sy@8 flag[D][set] flag[D][clr] net@297 nor2_sy-X_5
-Xnor3in3_@2 net@317 net@436 net@314 net@322 nor3in6_6sym
-Xnor3in3_@5 od[ABORT] od[OTHER] od[HEAD] net@476 nor3in6_6sym
-XpredDri2@2 fire[od] mc pred predDri20wMC
-Xsuc3ANDd@1 net@438 net@485 fire[od] od[OTHER] suc3ANDdri20
-XsucANDdr@0 bits[HEAD] net@444 od[HEAD] sucANDdri20
-XsucANDdr@4 bits[ABORT] fire[od] od[ABORT] sucANDdri20
-Xwire90@10 fire[od] net@444 wire90-956_7-layer_1-width_3
-Xwire90@11 net@322 net@374 wire90-294_8-layer_1-width_3
-Xwire90@13 net@297 net@317 wire90-294_8-layer_1-width_3
-Xwire90@15 net@305 net@436 wire90-294_8-layer_1-width_3
-Xwire90@16 net@358 net@314 wire90-294_8-layer_1-width_3
-Xwire90@18 net@371 net@476 wire90-294_8-layer_1-width_3
-Xwire90@19 net@368 net@367 wire90-294_8-layer_1-width_3
-Xwire90@20 net@441 net@438 wire90-294_8-layer_1-width_3
-Xwire90@21 net@463 net@485 wire90-294_8-layer_1-width_3
-.ENDS onDeck
-
-*** CELL: stagesM:onDeckDockStage{sch}
-.SUBCKT onDeckDockStage do[od] flag[A][clr] flag[A][set] flag[D][clr]
-+flag[D][set] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
-+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
-+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
-+m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15]
-+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
-+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
-+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] od[ABORT] od[HEAD] od[OTHER]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
-+take[od]
-Xins1in20@0 take[od] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15]
-+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
-+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
-+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] ins1in20Bx36
-XlatchDri@1 fire[1] take[od] latchDriver60
-XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr]
-+flag[D][set] sir[9] od[ABORT] od[HEAD] od[OTHER] do[od] net@62[1] net@62[0]
-+onDeck
-XscanEx2v@2 net@62[1] net@62[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1] scanEx2
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-Xtc[10] tranCap
-Xtc[11] tranCap
-Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
-.ENDS onDeckDockStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-927-R_34_667m a b
-Ccap@0 gnd net@14 3.399f
-Ccap@1 gnd net@8 3.399f
-Ccap@2 gnd net@11 3.399f
-Rres@0 net@14 a 5.356
-Rres@1 net@11 net@14 10.712
-Rres@2 b net@8 5.356
-Rres@3 net@8 net@11 10.712
-.ENDS wire-C_0_011f-927-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-927-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-927-R_34_667m
-.ENDS wire90-927-layer_1-width_3
-
-*** CELL: centersJ:ctrAND1in30{sch}
-.SUBCKT ctrAND1in30 in out
-Xinv@11 net@125 net@120 inv-X_10
-XinvI@1 net@82 out inv-X_30
-XinvI@2 in net@101 inv-X_5
-Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3
-Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3
-.ENDS ctrAND1in30
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-301_8-R_34_667m a b
-Ccap@0 gnd net@14 1.107f
-Ccap@1 gnd net@8 1.107f
-Ccap@2 gnd net@11 1.107f
-Rres@0 net@14 a 1.744
-Rres@1 net@11 net@14 3.487
-Rres@2 b net@8 1.744
-Rres@3 net@8 net@11 3.487
-.ENDS wire-C_0_011f-301_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-301_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-301_8-R_34_667m
-.ENDS wire90-301_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-732_5-R_34_667m a b
-Ccap@0 gnd net@14 2.686f
-Ccap@1 gnd net@8 2.686f
-Ccap@2 gnd net@11 2.686f
-Rres@0 net@14 a 4.232
-Rres@1 net@11 net@14 8.464
-Rres@2 b net@8 4.232
-Rres@3 net@8 net@11 8.464
-.ENDS wire-C_0_011f-732_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-732_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-732_5-R_34_667m
-.ENDS wire90-732_5-layer_1-width_3
-
-*** CELL: oneHotM:reQueueB{sch}
-.SUBCKT reQueueB circulate epi[TAIL] mc od[HEAD] s[1] s[2]
-XctrAND1i@0 net@1 net@7 ctrAND1in30
-Xinv@2 od[HEAD] net@127 inv-X_5
-Xinv@3 epi[TAIL] net@125 inv-X_5
-XinvI@3 net@128 s[1] inv-X_10
-XinvI@4 net@126 s[2] inv-X_10
-Xnand2@0 od[HEAD] epi[TAIL] net@0 nand2-X_5
-XpredDri2@1 net@7 mc epi[TAIL] predDri20wMC
-XpredDri2@2 net@7 mc od[HEAD] predDri20wMC
-XsucDri20@0 net@9 circulate sucDri20
-Xwire90@0 net@0 net@1 wire90-301_8-layer_1-width_3
-Xwire90@1 net@7 net@9 wire90-732_5-layer_1-width_3
-Xwire90@2 net@126 net@125 wire90-142_6-layer_1-width_3
-Xwire90@3 net@128 net@127 wire90-142_6-layer_1-width_3
-.ENDS reQueueB
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_3 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_6
-XNMOS@1 net@0 g gnd NMOSx-X_6
-.ENDS nms2-X_3
-
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_6 d g g2
-Xnms2@0 d g g2 nms2-X_3
-Xnms2@1 d g2 g nms2-X_3
-.ENDS nms2_sy-X_6
-
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_6 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_6
-XPMOS@1 out ina vdd PMOSx-X_6
-Xnms2_sy@0 out ina inb nms2_sy-X_6
-.ENDS nand2_sy-X_6
-
-*** CELL: redFive:nand2n{sch}
-.SUBCKT nand2n-X_5 ina inb out
-Xnand2@0 ina inb out nand2-X_5
-.ENDS nand2n-X_5
-
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_20 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_20
-.ENDS nand2n_sy-X_20
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_9_999 d g s
-MNMOSf@0 d g s gnd nch W='29.997*(1+ABN/sqrt(29.997*2))' L='2'
-+DELVTO='AVT0N/sqrt(29.997*2)'
-.ENDS NMOSx-X_9_999
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_3_333 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_9_999
-XNMOS@1 net@7 g gnd NMOSx-X_9_999
-XNMOS@2 net@6 g2 net@7 NMOSx-X_9_999
-.ENDS nms3-X_3_333
-
-*** CELL: gates3inM:nand3in6.6sym{sch}
-.SUBCKT nand3in6_6sym inA inB inC out
-XPMOSx@1 out inA vdd PMOSx-X_10
-XPMOSx@3 out inC vdd PMOSx-X_10
-XPMOSx@4 out inB vdd PMOSx-X_10
-Xnms3@0 out inA inB inC nms3-X_3_333
-Xnms3@2 out inC inB inA nms3-X_3_333
-.ENDS nand3in6_6sym
-
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_10 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_10
-XNMOS@1 out inb gnd NMOSx-X_10
-Xpms2@0 out ina inb pms2-X_10
-.ENDS nor2-X_10
-
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_10 ina inb out
-Xnor2@0 ina inb out nor2-X_10
-.ENDS nor2n-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-286_3-R_34_667m a b
-Ccap@0 gnd net@14 1.05f
-Ccap@1 gnd net@8 1.05f
-Ccap@2 gnd net@11 1.05f
-Rres@0 net@14 a 1.654
-Rres@1 net@11 net@14 3.308
-Rres@2 b net@8 1.654
-Rres@3 net@8 net@11 3.308
-.ENDS wire-C_0_011f-286_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-286_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-286_3-R_34_667m
-.ENDS wire90-286_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-428_8-R_34_667m a b
-Ccap@0 gnd net@14 1.572f
-Ccap@1 gnd net@8 1.572f
-Ccap@2 gnd net@11 1.572f
-Rres@0 net@14 a 2.478
-Rres@1 net@11 net@14 4.955
-Rres@2 b net@8 2.478
-Rres@3 net@8 net@11 4.955
-.ENDS wire-C_0_011f-428_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-428_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-428_8-R_34_667m
-.ENDS wire90-428_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-356_7-R_34_667m a b
-Ccap@0 gnd net@14 1.308f
-Ccap@1 gnd net@8 1.308f
-Ccap@2 gnd net@11 1.308f
-Rres@0 net@14 a 2.061
-Rres@1 net@11 net@14 4.122
-Rres@2 b net@8 2.061
-Rres@3 net@8 net@11 4.122
-.ENDS wire-C_0_011f-356_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-356_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-356_7-R_34_667m
-.ENDS wire90-356_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-199_1-R_34_667m a b
-Ccap@0 gnd net@14 0.73f
-Ccap@1 gnd net@8 0.73f
-Ccap@2 gnd net@11 0.73f
-Rres@0 net@14 a 1.15
-Rres@1 net@11 net@14 2.301
-Rres@2 b net@8 1.15
-Rres@3 net@8 net@11 2.301
-.ENDS wire-C_0_011f-199_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-199_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-199_1-R_34_667m
-.ENDS wire90-199_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-702_4-R_34_667m a b
-Ccap@0 gnd net@14 2.575f
-Ccap@1 gnd net@8 2.575f
-Ccap@2 gnd net@11 2.575f
-Rres@0 net@14 a 4.058
-Rres@1 net@11 net@14 8.117
-Rres@2 b net@8 4.058
-Rres@3 net@8 net@11 8.117
-.ENDS wire-C_0_011f-702_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-702_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-702_4-R_34_667m
-.ENDS wire90-702_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-251_7-R_34_667m a b
-Ccap@0 gnd net@14 0.923f
-Ccap@1 gnd net@8 0.923f
-Ccap@2 gnd net@11 0.923f
-Rres@0 net@14 a 1.454
-Rres@1 net@11 net@14 2.909
-Rres@2 b net@8 1.454
-Rres@3 net@8 net@11 2.909
-.ENDS wire-C_0_011f-251_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-251_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-251_7-R_34_667m
-.ENDS wire90-251_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-377-R_34_667m a b
-Ccap@0 gnd net@14 1.382f
-Ccap@1 gnd net@8 1.382f
-Ccap@2 gnd net@11 1.382f
-Rres@0 net@14 a 2.178
-Rres@1 net@11 net@14 4.356
-Rres@2 b net@8 2.178
-Rres@3 net@8 net@11 4.356
-.ENDS wire-C_0_011f-377-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-377-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-377-R_34_667m
-.ENDS wire90-377-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-593_4-R_34_667m a b
-Ccap@0 gnd net@14 2.176f
-Ccap@1 gnd net@8 2.176f
-Ccap@2 gnd net@11 2.176f
-Rres@0 net@14 a 3.429
-Rres@1 net@11 net@14 6.857
-Rres@2 b net@8 3.429
-Rres@3 net@8 net@11 6.857
-.ENDS wire-C_0_011f-593_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-593_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-593_4-R_34_667m
-.ENDS wire90-593_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1158_7-R_34_667m a b
-Ccap@0 gnd net@14 4.249f
-Ccap@1 gnd net@8 4.249f
-Ccap@2 gnd net@11 4.249f
-Rres@0 net@14 a 6.695
-Rres@1 net@11 net@14 13.389
-Rres@2 b net@8 6.695
-Rres@3 net@8 net@11 13.389
-.ENDS wire-C_0_011f-1158_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1158_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1158_7-R_34_667m
-.ENDS wire90-1158_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-487_9-R_34_667m a b
-Ccap@0 gnd net@14 1.789f
-Ccap@1 gnd net@8 1.789f
-Ccap@2 gnd net@11 1.789f
-Rres@0 net@14 a 2.819
-Rres@1 net@11 net@14 5.638
-Rres@2 b net@8 2.819
-Rres@3 net@8 net@11 5.638
-.ENDS wire-C_0_011f-487_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-487_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-487_9-R_34_667m
-.ENDS wire90-487_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-214_3-R_34_667m a b
-Ccap@0 gnd net@14 0.786f
-Ccap@1 gnd net@8 0.786f
-Ccap@2 gnd net@11 0.786f
-Rres@0 net@14 a 1.238
-Rres@1 net@11 net@14 2.476
-Rres@2 b net@8 1.238
-Rres@3 net@8 net@11 2.476
-.ENDS wire-C_0_011f-214_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-214_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-214_3-R_34_667m
-.ENDS wire90-214_3-layer_1-width_3
-
-*** CELL: oneHotM:reQueueC{sch}
-.SUBCKT reQueueC circulate epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER]
-+ps[do] ps[skip] s[1] s[2] succ
-XctrAND3i@0 succ net@361 circulate fire[E] ctrAND3in30
-Xinv@12 net@377 abortLO inv-X_10
-Xinv@13 epi[OTHER] net@440 inv-X_5
-Xinv@14 circulate net@320 inv-X_10
-XinvI@10 net@309 net@376 inv-X_5
-XinvI@11 net@394 net@396 inv-X_10
-XinvI@12 net@440 s[2] inv-X_10
-XinvI@13 net@320 s[1] inv-X_10
-Xnand2_sy@1 od[OTHER] ps[skip] net@274 nand2_sy-X_6
-Xnand2_sy@2 od[ABORT] ps[skip] net@277 nand2_sy-X_6
-Xnand2_sy@3 od[OTHER] ps[do] net@280 nand2_sy-X_6
-Xnand2_sy@4 od[ABORT] ps[do] net@283 nand2_sy-X_6
-Xnand2_sy@5 net@313 net@311 net@324 nand2_sy-X_6
-Xnand2n@0 circulate succ net@315 nand2n-X_5
-Xnand2n_s@0 net@324 abortLO fire[C] nand2n_sy-X_20
-Xnand3in6@1 net@303 net@418 net@306 net@420 nand3in6_6sym
-Xnor2n@1 net@326 net@322 fire[R] nor2n-X_10
-XpredDri2@2 net@243 mc od[ABORT] predDri20wMC
-XpredDri2@3 net@243 mc od[OTHER] predDri20wMC
-XpredDri2@4 net@243 mc ps[do] predDri20wMC
-XpredDri2@5 net@243 mc ps[skip] predDri20wMC
-XpredDri2@6 fire[E] mc epi[OTHER] predDri20wMC
-XpredDri2@7 net@399 mc circulate predDri20wMC
-XsucORdri@0 fire[R] fire[E] succ sucORdri20
-Xwire90@12 net@274 net@303 wire90-286_3-layer_1-width_3
-Xwire90@13 net@277 net@418 wire90-428_8-layer_1-width_3
-Xwire90@14 net@280 net@306 wire90-356_7-layer_1-width_3
-Xwire90@15 net@283 net@309 wire90-199_1-layer_1-width_3
-Xwire90@16 net@420 net@311 wire90-702_4-layer_1-width_3
-Xwire90@17 net@313 net@315 wire90-251_7-layer_1-width_3
-Xwire90@18 net@322 net@320 wire90-377-layer_1-width_3
-Xwire90@19 net@324 net@326 wire90-593_4-layer_1-width_3
-Xwire90@20 net@243 fire[C] wire90-1158_7-layer_1-width_3
-Xwire90@23 net@376 net@377 wire90-142_6-layer_1-width_3
-Xwire90@24 abortLO net@394 wire90-487_9-layer_1-width_3
-Xwire90@25 net@396 net@399 wire90-214_3-layer_1-width_3
-Xwire90@27 net@361 net@440 wire90-142_6-layer_1-width_3
-.ENDS reQueueC
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1041_2-R_34_667m a b
-Ccap@0 gnd net@14 3.818f
-Ccap@1 gnd net@8 3.818f
-Ccap@2 gnd net@11 3.818f
-Rres@0 net@14 a 6.016
-Rres@1 net@11 net@14 12.032
-Rres@2 b net@8 6.016
-Rres@3 net@8 net@11 12.032
-.ENDS wire-C_0_011f-1041_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1041_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1041_2-R_34_667m
-.ENDS wire90-1041_2-layer_1-width_3
-
-*** CELL: oneHotM:reQueue{sch}
-.SUBCKT reQueue epi[OTHER] epi[TAIL] fire[E] fire[R] mc od[ABORT] od[HEAD]
-+od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4]
-XreQueueB@1 circulate epi[TAIL] mc od[HEAD] s[1] s[2] reQueueB
-XreQueueC@0 net@3 epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER] ps[do]
-+ps[skip] s[3] s[4] rq[succ] reQueueC
-Xwire90@0 circulate net@3 wire90-1041_2-layer_1-width_3
-.ENDS reQueue
-
-*** CELL: scanM:scanEx3plain{sch}
-.SUBCKT scanEx3plain dIn[1] dIn[2] dIn[3] sin sir[2] sir[3] sir[5] sout
-XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sin net@26 scanCellE
-XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanCellE
-XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sout scanCellE
-Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
-Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3
-.ENDS scanEx3plain
-
-*** CELL: stagesM:rqDockStage{sch}
-.SUBCKT rqDockStage epi[OTHER] epi[TAIL] inE[10] inE[11] inE[12] inE[13]
-+inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21]
-+inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2]
-+inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5]
-+inE[6] inE[7] inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15]
-+inP[16] inP[17] inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23]
-+inP[24] inP[25] inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31]
-+inP[32] inP[33] inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7]
-+inP[8] inP[9] od[ABORT] od[HEAD] od[OTHER] ps[do] ps[skip] rq[10] rq[11]
-+rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] rq[21]
-+rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] rq[31]
-+rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9]
-+rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+sor[1] take[E] take[P]
-Xins2in20@0 take[E] take[P] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15]
-+inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23]
-+inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31]
-+inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7]
-+inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] inP[17]
-+inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] inP[25]
-+inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] inP[33]
-+inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7] inP[8] inP[9]
-+rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1]
-+rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2]
-+rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6]
-+rq[7] rq[8] rq[9] ins2in20Ax36
-XlatchDri@2 net@3 take[E] latchDriver60
-XlatchDri@3 net@7 take[P] latchDriver60
-XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD]
-+od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4] reQueue
-XscanEx1@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sin scanEx1
-XscanEx3p@1 s[2] s[3] s[4] sin sir[2] sir[3] sir[5] sor[1] scanEx3plain
-XtranCap@0 tranCap
-Xwire90@0 net@7 fire[R] wire90-1336_2-layer_1-width_3
-Xwire90@1 net@3 fire[E] wire90-1307-layer_1-width_3
-.ENDS rqDockStage
-
-*** CELL: stageGroupsM:epiRQod{sch}
-.SUBCKT epiRQod do[epi] do[od] epi[TORP] flag[A][clr] flag[A][set]
-+flag[D][clr] flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] m1[10] m1[11] m1[12] m1[13]
-+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
-+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
-+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[do]
-+ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18]
-+rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28]
-+rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4]
-+rq[5] rq[6] rq[7] rq[8] rq[9] rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1]
-XepiDockS@0 do[epi] net@45[26] net@45[25] net@45[24] net@45[23] net@45[22]
-+net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35] net@45[16]
-+net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10] net@45[9]
-+net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4] net@45[3]
-+net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31] net@45[30]
-+net@45[29] net@45[28] net@45[27] epi[OTHER] epi[TAIL] epi[TORP] in[10] in[11]
-+in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21]
-+in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31]
-+in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9]
-+in[T] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@0[8]
-+take[epi] epiDockStage
-XonDeckDo@0 do[od] flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] m1[10]
-+m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20]
-+m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30]
-+m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8]
-+m1[9] net@46[26] net@46[25] net@46[24] net@46[23] net@46[22] net@46[21]
-+net@46[20] net@46[19] net@46[18] net@46[17] net@46[35] net@46[16] net@46[15]
-+net@46[14] net@46[13] net@46[12] net@46[11] net@46[10] net@46[9] net@46[8]
-+net@46[7] net@46[34] net@46[6] net@46[5] net@46[4] net@46[3] net@46[2]
-+net@46[1] net@46[0] net@46[33] net@46[32] net@46[31] net@46[30] net@46[29]
-+net@46[28] net@46[27] od[ABORT] od[HEAD] od[OTHER] net@36[8] sir[2] sir[3]
-+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[od] onDeckDockStage
-XrqDockSt@0 epi[OTHER] epi[TAIL] net@45[26] net@45[25] net@45[24] net@45[23]
-+net@45[22] net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35]
-+net@45[16] net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10]
-+net@45[9] net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4]
-+net@45[3] net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31]
-+net@45[30] net@45[29] net@45[28] net@45[27] net@46[26] net@46[25] net@46[24]
-+net@46[23] net@46[22] net@46[21] net@46[20] net@46[19] net@46[18] net@46[17]
-+net@46[35] net@46[16] net@46[15] net@46[14] net@46[13] net@46[12] net@46[11]
-+net@46[10] net@46[9] net@46[8] net@46[7] net@46[34] net@46[6] net@46[5]
-+net@46[4] net@46[3] net@46[2] net@46[1] net@46[0] net@46[33] net@46[32]
-+net@46[31] net@46[30] net@46[29] net@46[28] net@46[27] od[ABORT] od[HEAD]
-+od[OTHER] ps[do] ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16]
-+rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26]
-+rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36]
-+rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] rq[succ] net@0[8] sir[2] sir[3]
-+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@36[8] take[E] take[P]
-+rqDockStage
-.ENDS epiRQod
-
-*** CELL: wiresL:bitAssignments{sch}
-.SUBCKT bitAssignments
-.ENDS bitAssignments
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_16 d g s
-MPMOSf@0 d g s vdd pch W='96*(1+ABP/sqrt(96*2))' L='2'
-+DELVTO='AVT0P/sqrt(96*2)'
-.ENDS PMOSx-X_16
-
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_16 d g g2
-Xnms2@0 d g g2 nms2-X_8
-Xnms2@1 d g2 g nms2-X_8
-.ENDS nms2_sy-X_16
-
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_16 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_16
-XPMOS@1 out ina vdd PMOSx-X_16
-Xnms2_sy@0 out ina inb nms2_sy-X_16
-.ENDS nand2_sy-X_16
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-416_2-R_34_667m a b
-Ccap@0 gnd net@14 1.526f
-Ccap@1 gnd net@8 1.526f
-Ccap@2 gnd net@11 1.526f
-Rres@0 net@14 a 2.405
-Rres@1 net@11 net@14 4.809
-Rres@2 b net@8 2.405
-Rres@3 net@8 net@11 4.809
-.ENDS wire-C_0_011f-416_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-416_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-416_2-R_34_667m
-.ENDS wire90-416_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-762_9-R_34_667m a b
-Ccap@0 gnd net@14 2.797f
-Ccap@1 gnd net@8 2.797f
-Ccap@2 gnd net@11 2.797f
-Rres@0 net@14 a 4.408
-Rres@1 net@11 net@14 8.816
-Rres@2 b net@8 4.408
-Rres@3 net@8 net@11 8.816
-.ENDS wire-C_0_011f-762_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-762_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-762_9-R_34_667m
-.ENDS wire90-762_9-layer_1-width_3
-
-*** CELL: centersJ:ctrAND3in60{sch}
-.SUBCKT ctrAND3in60 inA inB inC out
-Xinv@5 net@9 out inv-X_60
-Xnand2_sy@0 net@15 inC net@27 nand2_sy-X_16
-Xnor2nn@0 inA inB net@6 nor2-X_5
-Xwire90@0 net@6 net@15 wire90-416_2-layer_1-width_3
-Xwire90@1 net@27 net@9 wire90-762_9-layer_1-width_3
-.ENDS ctrAND3in60
-
-*** CELL: driversM:predDri40{sch}
-.SUBCKT predDri40 in pred
-XNMOSx@0 pred in gnd NMOSx-X_40
-.ENDS predDri40
-
-*** CELL: gaspM:gaspLit{sch}
-.SUBCKT gaspLit do[ins] fire[L] ready sel[Lt]
-XctrAND3i@0 net@248 net@243 ready fire[L] ctrAND3in60
-Xinv@0 fire[L] net@251 inv-X_5
-XinvI@0 net@252 net@253 inv-X_5
-XinvI@1 net@252 invI@1_out inv-X_10
-Xnand2@0 sel[Lt] do[ins] net@233 nand2-X_5
-XpredDri4@0 net@253 do[ins] predDri40
-Xwire90@1 net@233 net@243 wire90-414-layer_1-width_3
-Xwire90@2 net@252 net@251 wire90-414-layer_1-width_3
-Xwire90@3 net@253 net@248 wire90-414-layer_1-width_3
-.ENDS gaspLit
-
-*** CELL: driversM:latchAndDriver60{sch}
-.SUBCKT latchAndDriver60 inA inB out
-Xinv@0 net@8 out inv-X_60
-Xnand2@0 inA inB net@26 nand2-X_20
-Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3
-.ENDS latchAndDriver60
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-276_8-R_34_667m a b
-Ccap@0 gnd net@14 1.015f
-Ccap@1 gnd net@8 1.015f
-Ccap@2 gnd net@11 1.015f
-Rres@0 net@14 a 1.599
-Rres@1 net@11 net@14 3.199
-Rres@2 b net@8 1.599
-Rres@3 net@8 net@11 3.199
-.ENDS wire-C_0_011f-276_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-276_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-276_8-R_34_667m
-.ENDS wire90-276_8-layer_1-width_3
-
-*** CELL: stagesM:litDrivers{sch}
-.SUBCKT litDrivers fire[M] ready sel[Dc] sel[Do] sel[To] succ[D] succ[T]
-+take[A] take[C]
-Xinv@1 sel[Dc] net@56 inv-X_5
-XinvI@0 net@59 take[C] inv-X_5
-XlatchAnd@1 sel[Dc] fire[M] take[A] latchAndDriver60
-Xnand2@0 fire[M] net@62 net@60 nand2-X_5
-Xnor2n_sy@0 succ[T] succ[D] ready nor2n_sy-X_5
-XsucANDdr@0 sel[Do] fire[M] succ[D] sucANDdri60
-XsucANDdr@1 sel[To] fire[M] succ[T] sucANDdri60
-Xwire90@2 net@56 net@62 wire90-276_8-layer_1-width_3
-Xwire90@3 net@60 net@59 wire90-276_8-layer_1-width_3
-.ENDS litDrivers
-
-*** CELL: registersM:data2in60Cx18{sch}
-.SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
-+inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
-+inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
-+inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-XhiL[1] dcl[A] dcl[B] inA[1] inB[1] out[1] latch2in60C
-XhiL[2] dcl[A] dcl[B] inA[2] inB[2] out[2] latch2in60C
-XhiL[3] dcl[A] dcl[B] inA[3] inB[3] out[3] latch2in60C
-XhiL[4] dcl[A] dcl[B] inA[4] inB[4] out[4] latch2in60C
-XhiL[5] dcl[A] dcl[B] inA[5] inB[5] out[5] latch2in60C
-XhiL[6] dcl[A] dcl[B] inA[6] inB[6] out[6] latch2in60C
-XhiL[7] dcl[A] dcl[B] inA[7] inB[7] out[7] latch2in60C
-XhiL[8] dcl[A] dcl[B] inA[8] inB[8] out[8] latch2in60C
-XhiL[9] dcl[A] dcl[B] inA[9] inB[9] out[9] latch2in60C
-XhiL[10] dcl[A] dcl[B] inA[10] inB[10] out[10] latch2in60C
-XhiL[11] dcl[A] dcl[B] inA[11] inB[11] out[11] latch2in60C
-XhiL[12] dcl[A] dcl[B] inA[12] inB[12] out[12] latch2in60C
-XhiL[13] dcl[A] dcl[B] inA[13] inB[13] out[13] latch2in60C
-XhiL[14] dcl[A] dcl[B] inA[14] inB[14] out[14] latch2in60C
-XhiL[15] dcl[A] dcl[B] inA[15] inB[15] out[15] latch2in60C
-XhiL[16] dcl[A] dcl[B] inA[16] inB[16] out[16] latch2in60C
-XhiL[17] dcl[A] dcl[B] inA[17] inB[17] out[17] latch2in60C
-XhiL[18] dcl[A] dcl[B] inA[18] inB[18] out[18] latch2in60C
-.ENDS data2in60Cx18
-
-*** CELL: registersM:data2in60Cx37{sch}
-.SUBCKT data2in60Cx37 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] inA[16]
-+inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] inA[24]
-+inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] inA[32]
-+inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[37] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8]
-+out[9] take[A] take[B]
-Xdata2in6@1 take[A2] take[B2] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] data2in60Cx18
-Xdata2in6@2 take[A1] take[B1] inA[29] inA[30] inA[31] inA[32] inA[33] inA[34]
-+inA[35] inA[36] inA[37] inA[20] inA[21] inA[22] inA[23] inA[24] inA[25]
-+inA[26] inA[27] inA[28] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34]
-+inB[35] inB[36] inB[37] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] out[29] out[30] out[31] out[32] out[33] out[34]
-+out[35] out[36] out[37] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] data2in60Cx18
-Xlatch2in@4 take[A] take[B] inA[19] inB[19] out[19] latch2in60C
-Xwire90@0 take[A] take[A2] wire90-2550-layer_1-width_3
-Xwire90@4 take[B] take[B2] wire90-2550-layer_1-width_3
-Xwire90@5 take[B] take[B1] wire90-2550-layer_1-width_3
-Xwire90@6 take[A] take[A1] wire90-2550-layer_1-width_3
-.ENDS data2in60Cx37
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_9_6 d g s
-MNMOSf@0 d g s gnd nch W='28.8*(1+ABN/sqrt(28.8*2))' L='2'
-+DELVTO='AVT0N/sqrt(28.8*2)'
-.ENDS NMOSx-X_9_6
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_9_6 d g s
-MPMOSf@0 d g s vdd pch W='57.6*(1+ABP/sqrt(57.6*2))' L='2'
-+DELVTO='AVT0P/sqrt(57.6*2)'
-.ENDS PMOSx-X_9_6
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_9_6 in out
-XNMOS@0 out in gnd NMOSx-X_9_6
-XPMOS@0 out in vdd PMOSx-X_9_6
-.ENDS inv-X_9_6
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-277_3-R_34_667m a b
-Ccap@0 gnd net@14 1.017f
-Ccap@1 gnd net@8 1.017f
-Ccap@2 gnd net@11 1.017f
-Rres@0 net@14 a 1.602
-Rres@1 net@11 net@14 3.204
-Rres@2 b net@8 1.602
-Rres@3 net@8 net@11 3.204
-.ENDS wire-C_0_011f-277_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-277_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-277_3-R_34_667m
-.ENDS wire90-277_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-114_7-R_34_667m a b
-Ccap@0 gnd net@14 0.421f
-Ccap@1 gnd net@8 0.421f
-Ccap@2 gnd net@11 0.421f
-Rres@0 net@14 a 0.663
-Rres@1 net@11 net@14 1.325
-Rres@2 b net@8 0.663
-Rres@3 net@8 net@11 1.325
-.ENDS wire-C_0_011f-114_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-114_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-114_7-R_34_667m
-.ENDS wire90-114_7-layer_1-width_3
-
-*** CELL: latchesK:latch1in09.6Bi{sch}
-.SUBCKT latch1in09_6Bi hcl in[1] out[1]
-Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
-Xinv@0 net@23 out[1] inv-X_9_6
-XinvLT@0 net@18 net@25 inv-X_4
-Xwire90@0 net@19 net@18 wire90-277_3-layer_1-width_3
-Xwire90@1 net@25 net@23 wire90-114_7-layer_1-width_3
-.ENDS latch1in09_6Bi
-
-*** CELL: redFive:triInv{sch}
-.SUBCKT triInv-X_5 en enB in out
-Xnms2@0 out in en nms2-X_5
-Xpms2@0 out in enB pms2-X_5
-.ENDS triInv-X_5
-
-*** CELL: gates2inM:mux5{sch}
-.SUBCKT mux5 inA[1] inB[1] out[1] s[F] s[T]
-XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_5
-XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_5
-.ENDS mux5
-
-*** CELL: latchGroupsK:dataMux{sch}
-.SUBCKT dataMux hcl inB[1] in[1] out[1] s[F] s[T]
-Xlatch1in@1 hcl in[1] net@5 latch1in09_6Bi
-Xmux5@0 net@6 inB[1] out[1] s[F] s[T] mux5
-Xwire90@0 net@5 net@6 wire90-277_3-layer_1-width_3
-.ENDS dataMux
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-251_8-R_34_667m a b
-Ccap@0 gnd net@14 0.923f
-Ccap@1 gnd net@8 0.923f
-Ccap@2 gnd net@11 0.923f
-Rres@0 net@14 a 1.455
-Rres@1 net@11 net@14 2.91
-Rres@2 b net@8 1.455
-Rres@3 net@8 net@11 2.91
-.ENDS wire-C_0_011f-251_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-251_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-251_8-R_34_667m
-.ENDS wire90-251_8-layer_1-width_3
-
-*** CELL: registersM:shadowMux4{sch}
-.SUBCKT shadowMux4 in[1] in[2] in[3] in[4] out[1] out[2] out[3] out[4] s[F]
-+s[T] sign
-Xi[1] in[1] x[1] inv-X_10
-Xi[2] in[2] x[2] inv-X_10
-Xi[3] in[3] x[3] inv-X_10
-Xi[4] in[4] x[4] inv-X_10
-Xm[1] x[1] sign out[1] s[F] s[T] mux5
-Xm[2] x[2] sign out[2] s[F] s[T] mux5
-Xm[3] x[3] sign out[3] s[F] s[T] mux5
-Xm[4] x[4] sign out[4] s[F] s[T] mux5
-Xwire90@0 x[1] wire90@0_b wire90-251_8-layer_1-width_3
-Xwire90@1 x[2] wire90@1_b wire90-251_8-layer_1-width_3
-Xwire90@2 x[3] wire90@2_b wire90-251_8-layer_1-width_3
-Xwire90@3 x[4] wire90@3_b wire90-251_8-layer_1-width_3
-.ENDS shadowMux4
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_80 d g s
-MNMOSf@0 d g s gnd nch W='240*(1+ABN/sqrt(240*2))' L='2'
-+DELVTO='AVT0N/sqrt(240*2)'
-.ENDS NMOSx-X_80
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_80 d g s
-MPMOSf@0 d g s vdd pch W='480*(1+ABP/sqrt(480*2))' L='2'
-+DELVTO='AVT0P/sqrt(480*2)'
-.ENDS PMOSx-X_80
-
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_80 in out
-XNMOS@0 out in gnd NMOSx-X_80
-XPMOS@0 out in vdd PMOSx-X_80
-.ENDS inv-X_80
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-817_9-R_34_667m a b
-Ccap@0 gnd net@14 2.999f
-Ccap@1 gnd net@8 2.999f
-Ccap@2 gnd net@11 2.999f
-Rres@0 net@14 a 4.726
-Rres@1 net@11 net@14 9.451
-Rres@2 b net@8 4.726
-Rres@3 net@8 net@11 9.451
-.ENDS wire-C_0_011f-817_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-817_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-817_9-R_34_667m
-.ENDS wire90-817_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1334_3-R_34_667m a b
-Ccap@0 gnd net@14 4.892f
-Ccap@1 gnd net@8 4.892f
-Ccap@2 gnd net@11 4.892f
-Rres@0 net@14 a 7.709
-Rres@1 net@11 net@14 15.419
-Rres@2 b net@8 7.709
-Rres@3 net@8 net@11 15.419
-.ENDS wire-C_0_011f-1334_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1334_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1334_3-R_34_667m
-.ENDS wire90-1334_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-540-R_34_667m a b
-Ccap@0 gnd net@14 1.98f
-Ccap@1 gnd net@8 1.98f
-Ccap@2 gnd net@11 1.98f
-Rres@0 net@14 a 3.12
-Rres@1 net@11 net@14 6.24
-Rres@2 b net@8 3.12
-Rres@3 net@8 net@11 6.24
-.ENDS wire-C_0_011f-540-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-540-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-540-R_34_667m
-.ENDS wire90-540-layer_1-width_3
-
-*** CELL: registersM:signLogic{sch}
-.SUBCKT signLogic inB[15] inB[20] s[F] s[T] sign
-Xinv@0 net@12 sign inv-X_80
-Xinv@2 inB[20] net@19 inv-X_30
-Xinv@3 net@7 s[T] inv-X_100
-Xinv@4 s[T] s[F] inv-X_80
-Xinv@5 net@14 net@13 inv-X_30
-Xnand2_sy@0 net@7 inB[15] net@21 nand2_sy-X_20
-Xwire90@2 net@13 net@12 wire90-817_9-layer_1-width_3
-Xwire90@4 net@19 net@7 wire90-1334_3-layer_1-width_3
-Xwire90@5 net@21 net@14 wire90-540-layer_1-width_3
-.ENDS signLogic
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4861_7-R_34_667m a b
-Ccap@0 gnd net@14 17.826f
-Ccap@1 gnd net@8 17.826f
-Ccap@2 gnd net@11 17.826f
-Rres@0 net@14 a 28.09
-Rres@1 net@11 net@14 56.18
-Rres@2 b net@8 28.09
-Rres@3 net@8 net@11 56.18
-.ENDS wire-C_0_011f-4861_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4861_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4861_7-R_34_667m
-.ENDS wire90-4861_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5555_8-R_34_667m a b
-Ccap@0 gnd net@14 20.371f
-Ccap@1 gnd net@8 20.371f
-Ccap@2 gnd net@11 20.371f
-Rres@0 net@14 a 32.1
-Rres@1 net@11 net@14 64.2
-Rres@2 b net@8 32.1
-Rres@3 net@8 net@11 64.2
-.ENDS wire-C_0_011f-5555_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5555_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5555_8-R_34_667m
-.ENDS wire90-5555_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5262_9-R_34_667m a b
-Ccap@0 gnd net@14 19.297f
-Ccap@1 gnd net@8 19.297f
-Ccap@2 gnd net@11 19.297f
-Rres@0 net@14 a 30.408
-Rres@1 net@11 net@14 60.816
-Rres@2 b net@8 30.408
-Rres@3 net@8 net@11 60.816
-.ENDS wire-C_0_011f-5262_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5262_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5262_9-R_34_667m
-.ENDS wire90-5262_9-layer_1-width_3
-
-*** CELL: registersM:shadow{sch}
-.SUBCKT shadow hcl inB[15] inB[16] inB[17] inB[18] inB[19] inB[20] inn[10]
-+inn[11] inn[12] inn[13] inn[14] inn[15] inn[16] inn[17] inn[18] inn[1] inn[2]
-+inn[3] inn[4] inn[5] inn[6] inn[7] inn[8] inn[9] outt[16] outt[17] outt[18]
-+outt[19] outt[20] outt[21] outt[22] outt[23] outt[24] outt[25] outt[26]
-+outt[27] outt[28] outt[29] outt[30] outt[31] outt[32] outt[33] outt[34]
-+outt[35] outt[36] outt[37]
-Xdl[1] hcl sign inn[1] outt[20] s[F] s[T] dataMux
-Xdl[2] hcl sign inn[2] outt[21] s[F] s[T] dataMux
-Xdl[3] hcl sign inn[3] outt[22] s[F] s[T] dataMux
-Xdl[4] hcl sign inn[4] outt[23] s[F] s[T] dataMux
-Xdl[5] hcl sign inn[5] outt[24] s[F] s[T] dataMux
-Xdl[6] hcl sign inn[6] outt[25] s[F] s[T] dataMux
-Xdl[7] hcl sign inn[7] outt[26] s[F] s[T] dataMux
-Xdl[8] hcl sign inn[8] outt[27] s[F] s[T] dataMux
-Xdl[9] hcl sign inn[9] outt[28] s[F] s[T] dataMux
-Xdr[1] hcl sign inn[18] outt[37] s[F] s[T] dataMux
-Xdr[2] hcl sign inn[17] outt[36] s[F] s[T] dataMux
-Xdr[3] hcl sign inn[16] outt[35] s[F] s[T] dataMux
-Xdr[4] hcl sign inn[15] outt[34] s[F] s[T] dataMux
-Xdr[5] hcl sign inn[14] outt[33] s[F] s[T] dataMux
-Xdr[6] hcl sign inn[13] outt[32] s[F] s[T] dataMux
-Xdr[7] hcl sign inn[12] outt[31] s[F] s[T] dataMux
-Xdr[8] hcl sign inn[11] outt[30] s[F] s[T] dataMux
-Xdr[9] hcl sign inn[10] outt[29] s[F] s[T] dataMux
-XshadowMu@1 inB[16] inB[17] inB[18] inB[19] outt[16] outt[17] outt[18]
-+outt[19] s[F] s[T] sign shadowMux4
-XsignLogi@0 inB[15] inB[20] s[F] s[T] sign signLogic
-Xwire90@1 s[F] wire90@1_b wire90-4861_7-layer_1-width_3
-Xwire90@2 s[T] wire90@2_b wire90-5555_8-layer_1-width_3
-Xwire90@3 sign wire90@3_b wire90-5262_9-layer_1-width_3
-.ENDS shadow
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4175_4-R_34_667m a b
-Ccap@0 gnd net@14 15.31f
-Ccap@1 gnd net@8 15.31f
-Ccap@2 gnd net@11 15.31f
-Rres@0 net@14 a 24.125
-Rres@1 net@11 net@14 48.249
-Rres@2 b net@8 24.125
-Rres@3 net@8 net@11 48.249
-.ENDS wire-C_0_011f-4175_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4175_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4175_4-R_34_667m
-.ENDS wire90-4175_4-layer_1-width_3
-
-*** CELL: registersM:newDregister{sch}
-.SUBCKT newDregister dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
-+dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
-+dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37]
-+dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
-+out[5] out[6] out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7]
-+ps[8] ps[9] take[A] take[B]
-Xdata2in6@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
-+dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
-+dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
-+dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ss[16] ss[17] ss[18] ss[19] ps[1] ss[20] ss[21] ss[22] ss[23] ss[24] ss[25]
-+ss[26] ss[27] ss[28] ss[29] ps[2] ss[30] ss[31] ss[32] ss[33] ss[34] ss[35]
-+ss[36] ss[37] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] take[B]
-+data2in60Cx37
-Xinv@0 take[B] net@66 inv-X_40
-Xshadow@0 net@66 ps[15] ps[16] ps[17] ps[18] ps[19] ps[20] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] ss[16] ss[17] ss[18] ss[19] ss[20]
-+ss[21] ss[22] ss[23] ss[24] ss[25] ss[26] ss[27] ss[28] ss[29] ss[30] ss[31]
-+ss[32] ss[33] ss[34] ss[35] ss[36] ss[37] shadow
-Xwire90@0 net@66 wire90@0_b wire90-4175_4-layer_1-width_3
-.ENDS newDregister
-
-*** CELL: registersM:addr2in60Cx7{sch}
-.SUBCKT addr2in60Cx7 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7]
-+ainB[1] ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] fire[A] fire[B]
-XhiL[1] fire[A] fire[B] ainA[1] ainB[1] aout[1] latch2in60C
-XhiL[2] fire[A] fire[B] ainA[2] ainB[2] aout[2] latch2in60C
-XhiL[3] fire[A] fire[B] ainA[3] ainB[3] aout[3] latch2in60C
-XhiL[4] fire[A] fire[B] ainA[4] ainB[4] aout[4] latch2in60C
-XhiL[5] fire[A] fire[B] ainA[5] ainB[5] aout[5] latch2in60C
-XhiL[6] fire[A] fire[B] ainA[6] ainB[6] aout[6] latch2in60C
-XhiL[7] fire[A] fire[B] ainA[7] ainB[7] aout[7] latch2in60C
-.ENDS addr2in60Cx7
-
-*** CELL: registersM:addr2in60Cx15{sch}
-.SUBCKT addr2in60Cx15 ainA[10] ainA[11] ainA[12] ainA[13] ainA[14] ainA[1]
-+ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainA[8] ainA[9] ainA[TT]
-+ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] ainB[1] ainB[2] ainB[3] ainB[4]
-+ainB[5] ainB[6] ainB[7] ainB[8] ainB[9] ainB[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] fire[A] fire[B]
-Xaddr2in6@1 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainB[1]
-+ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2] aout[3]
-+aout[4] aout[5] aout[6] aout[7] fire[A2] fire[B2] addr2in60Cx7
-Xaddr2in6@2 ainA[8] ainA[9] ainA[10] ainA[11] ainA[12] ainA[13] ainA[14]
-+ainB[8] ainB[9] ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] aout[8] aout[9]
-+aout[10] aout[11] aout[12] aout[13] aout[14] fire[A1] fire[B1] addr2in60Cx7
-Xlatch2in@4 fire[A2] fire[B2] ainA[TT] ainB[TT] aout[TT] latch2in60C
-Xwire90@3 fire[A] fire[A1] wire90-2330-layer_1-width_3
-Xwire90@4 fire[B] fire[B1] wire90-2330-layer_1-width_3
-Xwire90@5 fire[B] fire[B2] wire90-2330-layer_1-width_3
-Xwire90@6 fire[A] fire[A2] wire90-2330-layer_1-width_3
-.ENDS addr2in60Cx15
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-387_3-R_34_667m a b
-Ccap@0 gnd net@14 1.42f
-Ccap@1 gnd net@8 1.42f
-Ccap@2 gnd net@11 1.42f
-Rres@0 net@14 a 2.238
-Rres@1 net@11 net@14 4.475
-Rres@2 b net@8 2.238
-Rres@3 net@8 net@11 4.475
-.ENDS wire-C_0_011f-387_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-387_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-387_3-R_34_667m
-.ENDS wire90-387_3-layer_1-width_3
-
-*** CELL: driversM:latchAndDriver30{sch}
-.SUBCKT latchAndDriver30 inA inB out
-Xinv@0 net@8 out inv-X_30
-Xnand2@0 inA inB net@26 nand2-X_10
-Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3
-.ENDS latchAndDriver30
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3495_7-R_34_667m a b
-Ccap@0 gnd net@14 12.818f
-Ccap@1 gnd net@8 12.818f
-Ccap@2 gnd net@11 12.818f
-Rres@0 net@14 a 20.197
-Rres@1 net@11 net@14 40.395
-Rres@2 b net@8 20.197
-Rres@3 net@8 net@11 40.395
-.ENDS wire-C_0_011f-3495_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3495_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3495_7-R_34_667m
-.ENDS wire90-3495_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3616_3-R_34_667m a b
-Ccap@0 gnd net@14 13.26f
-Ccap@1 gnd net@8 13.26f
-Ccap@2 gnd net@11 13.26f
-Rres@0 net@14 a 20.894
-Rres@1 net@11 net@14 41.788
-Rres@2 b net@8 20.894
-Rres@3 net@8 net@11 41.788
-.ENDS wire-C_0_011f-3616_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3616_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3616_3-R_34_667m
-.ENDS wire90-3616_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-270-R_34_667m a b
-Ccap@0 gnd net@14 0.99f
-Ccap@1 gnd net@8 0.99f
-Ccap@2 gnd net@11 0.99f
-Rres@0 net@14 a 1.56
-Rres@1 net@11 net@14 3.12
-Rres@2 b net@8 1.56
-Rres@3 net@8 net@11 3.12
-.ENDS wire-C_0_011f-270-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-270-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-270-R_34_667m
-.ENDS wire90-270-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-358-R_34_667m a b
-Ccap@0 gnd net@14 1.313f
-Ccap@1 gnd net@8 1.313f
-Ccap@2 gnd net@11 1.313f
-Rres@0 net@14 a 2.068
-Rres@1 net@11 net@14 4.137
-Rres@2 b net@8 2.068
-Rres@3 net@8 net@11 4.137
-.ENDS wire-C_0_011f-358-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-358-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-358-R_34_667m
-.ENDS wire90-358-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-433_4-R_34_667m a b
-Ccap@0 gnd net@14 1.589f
-Ccap@1 gnd net@8 1.589f
-Ccap@2 gnd net@11 1.589f
-Rres@0 net@14 a 2.504
-Rres@1 net@11 net@14 5.008
-Rres@2 b net@8 2.504
-Rres@3 net@8 net@11 5.008
-.ENDS wire-C_0_011f-433_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-433_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-433_4-R_34_667m
-.ENDS wire90-433_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-425_6-R_34_667m a b
-Ccap@0 gnd net@14 1.561f
-Ccap@1 gnd net@8 1.561f
-Ccap@2 gnd net@11 1.561f
-Rres@0 net@14 a 2.459
-Rres@1 net@11 net@14 4.918
-Rres@2 b net@8 2.459
-Rres@3 net@8 net@11 4.918
-.ENDS wire-C_0_011f-425_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-425_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-425_6-R_34_667m
-.ENDS wire90-425_6-layer_1-width_3
-
-*** CELL: registersM:newPathReg{sch}
-.SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
-+dp[10] dp[11] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9]
-+fire[M] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4]
-+ps[5] ps[6] ps[7] ps[8] ps[9]
-Xaddr2in6@0 dp[10] dp[11] dp[12] dp[12] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5]
-+dp[6] dp[7] dp[8] dp[9] ps[15not] ps[10] ps[11] ps[12] ps[13] ps[13] ps[1]
-+ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[15not] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15
-Xinv@1 ps[13] net@46 inv-X_10
-Xinv@2 ps[14] net@47 inv-X_10
-Xinv@3 ps[15] net@52 inv-X_10
-XinvI@0 net@58 net@40 inv-X_30
-XlatchAnd@1 ps[14] fire[M] net@43 latchAndDriver30
-Xnand3@1 net@25 net@28 fire[M] net@59 nand3-X_6_667
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xwire90@0 net@43 take[ps] wire90-3495_7-layer_1-width_3
-Xwire90@1 net@40 take[dp] wire90-3616_3-layer_1-width_3
-Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3
-Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3
-Xwire90@5 net@52 ps[15not] wire90-433_4-layer_1-width_3
-Xwire90@6 net@59 net@58 wire90-425_6-layer_1-width_3
-.ENDS newPathReg
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-402-R_34_667m a b
-Ccap@0 gnd net@14 1.474f
-Ccap@1 gnd net@8 1.474f
-Ccap@2 gnd net@11 1.474f
-Rres@0 net@14 a 2.323
-Rres@1 net@11 net@14 4.645
-Rres@2 b net@8 2.323
-Rres@3 net@8 net@11 4.645
-.ENDS wire-C_0_011f-402-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-402-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-402-R_34_667m
-.ENDS wire90-402-layer_1-width_3
-
-*** CELL: stagesM:litDandP{sch}
-.SUBCKT litDandP do[ins] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16]
-+dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26]
-+dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36]
-+dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11]
-+dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7]
-+dsA[8] dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16]
-+dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
-+dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
-+dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
-+dsD[8] dsD[9] fire[M] flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6]
-+ps[7] ps[8] ps[9] signalBitFromInboundSwitchFabric succ[D] succ[T]
-XbitAssig@0 bitAssignments
-XgaspLit@1 do[ins] take[B] net@108 ps[27] gaspLit
-Xlatch2in@0 take[A] net@140 dp[B] signalBitFromInboundSwitchFabric flag[C]
-+latch2in60C
-XlitDrive@0 fire[M] net@130 ps[17] ps[16] ps[15] succ[D] succ[T] take[A]
-+net@141 litDrivers
-XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
-+dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
-+dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
-+dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14]
-+dsD[15] dsD[16] dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22]
-+dsD[23] dsD[24] dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30]
-+dsD[31] dsD[32] dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5]
-+dsD[6] dsD[7] dsD[8] dsD[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
-+ps[9] take[A] take[B] newDregister
-XnewPathR@0 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3]
-+dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] dp[35] dp[36] dp[37] dp[26]
-+dp[27] dp[28] dp[29] dp[30] dp[31] dp[32] dp[33] dp[34] fire[M] ps[10] ps[11]
-+ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
-+ps[9] newPathReg
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-Xtc[10] tranCap
-Xtc[11] tranCap
-Xwire90@1 net@108 net@130 wire90-402-layer_1-width_3
-Xwire90@4 net@141 net@140 wire90-402-layer_1-width_3
-.ENDS litDandP
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_20 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_40
-XPMOS@1 d g2 net@2 PMOSx-X_40
-.ENDS pms2-X_20
-
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_20 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_20
-XNMOS@1 out inb gnd NMOSx-X_20
-Xpms2@0 out ina inb pms2-X_20
-.ENDS nor2-X_20
-
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_20 ina inb out
-Xnor2@0 ina inb out nor2-X_20
-.ENDS nor2n-X_20
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_2 d g s
-MPMOSf@0 d g s vdd pch W='12*(1+ABP/sqrt(12*2))' L='2'
-+DELVTO='AVT0P/sqrt(12*2)'
-.ENDS PMOSx-X_2
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_2 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_2
-XPMOS@1 out inb vdd PMOSx-X_2
-Xnms2@0 out ina inb nms2-X_2
-.ENDS nand2-X_2
-
-*** CELL: redFive:nms1{sch}
-.SUBCKT nms1-X_4 d g
-XNMOS@1 d g gnd NMOSx-X_4
-.ENDS nms1-X_4
-
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_10 d g
-XPMOS@0 d g vdd PMOSx-X_10
-.ENDS pms1-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-288_3-R_34_667m a b
-Ccap@0 gnd net@14 1.057f
-Ccap@1 gnd net@8 1.057f
-Ccap@2 gnd net@11 1.057f
-Rres@0 net@14 a 1.666
-Rres@1 net@11 net@14 3.331
-Rres@2 b net@8 1.666
-Rres@3 net@8 net@11 3.331
-.ENDS wire-C_0_011f-288_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-288_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-288_3-R_34_667m
-.ENDS wire90-288_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-255_4-R_34_667m a b
-Ccap@0 gnd net@14 0.936f
-Ccap@1 gnd net@8 0.936f
-Ccap@2 gnd net@11 0.936f
-Rres@0 net@14 a 1.476
-Rres@1 net@11 net@14 2.951
-Rres@2 b net@8 1.476
-Rres@3 net@8 net@11 2.951
-.ENDS wire-C_0_011f-255_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-255_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-255_4-R_34_667m
-.ENDS wire90-255_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-120_2-R_34_667m a b
-Ccap@0 gnd net@14 0.441f
-Ccap@1 gnd net@8 0.441f
-Ccap@2 gnd net@11 0.441f
-Rres@0 net@14 a 0.694
-Rres@1 net@11 net@14 1.389
-Rres@2 b net@8 0.694
-Rres@3 net@8 net@11 1.389
-.ENDS wire-C_0_011f-120_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-120_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-120_2-R_34_667m
-.ENDS wire90-120_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-112_1-R_34_667m a b
-Ccap@0 gnd net@14 0.411f
-Ccap@1 gnd net@8 0.411f
-Ccap@2 gnd net@11 0.411f
-Rres@0 net@14 a 0.648
-Rres@1 net@11 net@14 1.295
-Rres@2 b net@8 0.648
-Rres@3 net@8 net@11 1.295
-.ENDS wire-C_0_011f-112_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-112_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-112_1-R_34_667m
-.ENDS wire90-112_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-66_6-R_34_667m a b
-Ccap@0 gnd net@14 0.244f
-Ccap@1 gnd net@8 0.244f
-Ccap@2 gnd net@11 0.244f
-Rres@0 net@14 a 0.385
-Rres@1 net@11 net@14 0.77
-Rres@2 b net@8 0.385
-Rres@3 net@8 net@11 0.77
-.ENDS wire-C_0_011f-66_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-66_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-66_6-R_34_667m
-.ENDS wire90-66_6-layer_1-width_3
-
-*** CELL: oneHotM:sucDri10Pair{sch}
-.SUBCKT sucDri10Pair bit[1] out[1][F] out[1][T] when
-XNMOSx@2 out[1][F] net@105 net@139 NMOSx-X_4
-XNMOSx@3 out[1][F] bit[1] net@144 NMOSx-X_4
-Xinv@2 when net@66 inv-X_4
-Xinv@5 out[1][F] net@92 inv-X_4
-Xinv@6 out[1][T] net@112 inv-X_4
-Xnand2@1 when bit[1] net@64 nand2-X_2
-Xnms1@2 net@139 net@154 nms1-X_4
-Xnms2b@0 out[1][T] net@113 net@4 nms2-X_2
-Xpms1@0 out[1][T] net@4 pms1-X_10
-Xpms2_sy@0 out[1][F] net@105 bit[1] pms2_sy-X_10
-Xwire90@0 net@64 net@4 wire90-288_3-layer_1-width_3
-Xwire90@1 net@66 net@105 wire90-255_4-layer_1-width_3
-Xwire90@3 net@113 net@112 wire90-120_2-layer_1-width_3
-Xwire90@4 net@154 net@92 wire90-112_1-layer_1-width_3
-Xwire90@5 net@144 net@139 wire90-66_6-layer_1-width_3
-.ENDS sucDri10Pair
-
-*** CELL: oneHotM:sucDri10Pairx6{sch}
-.SUBCKT sucDri10Pairx6 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ready when
-Xdd[1] bit[1] m1cate[1][F] m1cate[1][T] when sucDri10Pair
-Xdd[2] bit[2] m1cate[2][F] m1cate[2][T] when sucDri10Pair
-Xdd[3] bit[3] m1cate[3][F] m1cate[3][T] when sucDri10Pair
-Xdd[4] bit[4] m1cate[4][F] m1cate[4][T] when sucDri10Pair
-Xdd[5] bit[5] m1cate[5][F] m1cate[5][T] when sucDri10Pair
-Xdd[6] bit[6] m1cate[6][F] m1cate[6][T] when sucDri10Pair
-Xnor2n_sy@0 m1cate[1][T] m1cate[1][F] ready nor2n_sy-X_5
-.ENDS sucDri10Pairx6
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-425_8-R_34_667m a b
-Ccap@0 gnd net@14 1.561f
-Ccap@1 gnd net@8 1.561f
-Ccap@2 gnd net@11 1.561f
-Rres@0 net@14 a 2.46
-Rres@1 net@11 net@14 4.92
-Rres@2 b net@8 2.46
-Rres@3 net@8 net@11 4.92
-.ENDS wire-C_0_011f-425_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-425_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-425_8-R_34_667m
-.ENDS wire90-425_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-257_3-R_34_667m a b
-Ccap@0 gnd net@14 0.943f
-Ccap@1 gnd net@8 0.943f
-Ccap@2 gnd net@11 0.943f
-Rres@0 net@14 a 1.487
-Rres@1 net@11 net@14 2.973
-Rres@2 b net@8 1.487
-Rres@3 net@8 net@11 2.973
-.ENDS wire-C_0_011f-257_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-257_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-257_3-R_34_667m
-.ENDS wire90-257_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-692_7-R_34_667m a b
-Ccap@0 gnd net@14 2.54f
-Ccap@1 gnd net@8 2.54f
-Ccap@2 gnd net@11 2.54f
-Rres@0 net@14 a 4.002
-Rres@1 net@11 net@14 8.005
-Rres@2 b net@8 4.002
-Rres@3 net@8 net@11 8.005
-.ENDS wire-C_0_011f-692_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-692_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-692_7-R_34_667m
-.ENDS wire90-692_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-399_3-R_34_667m a b
-Ccap@0 gnd net@14 1.464f
-Ccap@1 gnd net@8 1.464f
-Ccap@2 gnd net@11 1.464f
-Rres@0 net@14 a 2.307
-Rres@1 net@11 net@14 4.614
-Rres@2 b net@8 2.307
-Rres@3 net@8 net@11 4.614
-.ENDS wire-C_0_011f-399_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-399_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-399_3-R_34_667m
-.ENDS wire90-399_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-489_2-R_34_667m a b
-Ccap@0 gnd net@14 1.794f
-Ccap@1 gnd net@8 1.794f
-Ccap@2 gnd net@11 1.794f
-Rres@0 net@14 a 2.826
-Rres@1 net@11 net@14 5.653
-Rres@2 b net@8 2.826
-Rres@3 net@8 net@11 5.653
-.ENDS wire-C_0_011f-489_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-489_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-489_2-R_34_667m
-.ENDS wire90-489_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1763-R_34_667m a b
-Ccap@0 gnd net@14 6.464f
-Ccap@1 gnd net@8 6.464f
-Ccap@2 gnd net@11 6.464f
-Rres@0 net@14 a 10.186
-Rres@1 net@11 net@14 20.372
-Rres@2 b net@8 10.186
-Rres@3 net@8 net@11 20.372
-.ENDS wire-C_0_011f-1763-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1763-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1763-R_34_667m
-.ENDS wire90-1763-layer_1-width_3
-
-*** CELL: oneHotM:minusOne{sch}
-.SUBCKT minusOne bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] fire[m1] headBit
-+m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
-+m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T]
-+mc pred s[1] succ[m1]
-Xinv@7 pred net@313 inv-X_5
-XinvI@0 net@235 s[1] inv-X_10
-XinvI@1 net@398 fire[m1] inv-X_10
-Xnand2@1 net@414 net@411 net@398 nand2-X_10
-Xnor2n@0 headBit net@405 net@406 nor2n-X_20
-Xnor2n_sy@1 succ[m1] net@235 net@391 nor2n_sy-X_5
-XpredDri2@0 fire[m1] mc pred predDri20wMC
-XsucDri10@1 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] net@435
-+net@421 sucDri10Pairx6
-XsucDri20@1 net@407 succ[m1] sucDri20
-Xwire90@10 fire[m1] net@407 wire90-425_8-layer_1-width_3
-Xwire90@11 net@313 net@235 wire90-257_3-layer_1-width_3
-Xwire90@12 net@414 net@435 wire90-692_7-layer_1-width_3
-Xwire90@13 net@411 net@391 wire90-399_3-layer_1-width_3
-Xwire90@14 net@398 net@405 wire90-489_2-layer_1-width_3
-Xwire90@15 net@406 net@421 wire90-1763-layer_1-width_3
-.ENDS minusOne
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-793_6-R_34_667m a b
-Ccap@0 gnd net@14 2.91f
-Ccap@1 gnd net@8 2.91f
-Ccap@2 gnd net@11 2.91f
-Rres@0 net@14 a 4.585
-Rres@1 net@11 net@14 9.17
-Rres@2 b net@8 4.585
-Rres@3 net@8 net@11 9.17
-.ENDS wire-C_0_011f-793_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-793_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-793_6-R_34_667m
-.ENDS wire90-793_6-layer_1-width_3
-
-*** CELL: stagesM:mOneDockStage{sch}
-.SUBCKT mOneDockStage m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[R] ring[10] ring[11] ring[12]
-+ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1]
-+ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27]
-+ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34]
-+ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
-+succ[m1] take[m1]
-Xins1in20@0 take[m1] ring[10] ring[11] ring[12] ring[13] ring[14] ring[15]
-+ring[16] ring[17] ring[18] ring[19] ring[1] ring[20] ring[21] ring[22]
-+ring[23] ring[24] ring[25] ring[26] ring[27] ring[28] ring[29] ring[2]
-+ring[30] ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] ring[3]
-+ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] m1[10] m1[11] m1[12] m1[13]
-+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
-+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
-+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ins1in20Bx36
-XlatchDri@1 fire[1] take[m1] latchDriver60
-XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11
-+ring[30] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F]
-+m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F]
-+m1cate[6][T] sir[9] pred[R] net@47 succ[m1] minusOne
-XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-Xtc[10] tranCap
-Xtc[11] tranCap
-Xtc[12] tranCap
-Xtc[13] tranCap
-Xtc[14] tranCap
-Xtc[15] tranCap
-Xtc[16] tranCap
-Xtc[17] tranCap
-Xtc[18] tranCap
-Xtc[19] tranCap
-Xwire90@1 net@11 fire[1] wire90-793_6-layer_1-width_3
-.ENDS mOneDockStage
-
-*** CELL: loopCountM:mux10/2{sch}
-.SUBCKT mux10/2 in[1] out[1] sF sT
-Xnms2b@0 out[1] sT in[1] nms2-X_10
-Xpms2@0 out[1] sF in[1] pms2-X_10
-.ENDS mux10/2
-
-*** CELL: loopCountM:mux10/2x7{sch}
-.SUBCKT mux10/2x7 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] sF sT
-Xmux10/2@0 in[1] out[1] sF sT mux10/2
-Xmux10/2@1 in[2] out[2] sF sT mux10/2
-Xmux10/2@2 in[3] out[3] sF sT mux10/2
-Xmux10/2@3 in[4] out[4] sF sT mux10/2
-Xmux10/2@4 in[5] out[5] sF sT mux10/2
-Xmux10/2@5 in[6] out[6] sF sT mux10/2
-Xmux10/2@6 in[7] out[7] sF sT mux10/2
-.ENDS mux10/2x7
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-704_3-R_34_667m a b
-Ccap@0 gnd net@14 2.582f
-Ccap@1 gnd net@8 2.582f
-Ccap@2 gnd net@11 2.582f
-Rres@0 net@14 a 4.069
-Rres@1 net@11 net@14 8.139
-Rres@2 b net@8 4.069
-Rres@3 net@8 net@11 8.139
-.ENDS wire-C_0_011f-704_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-704_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-704_3-R_34_667m
-.ENDS wire90-704_3-layer_1-width_3
-
-*** CELL: loopCountM:muxForPS{sch}
-.SUBCKT muxForPS in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] sel
-Xinv@0 sel net@0 inv-X_20
-Xinv@1 sT net@1 inv-X_20
-Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] sF sT mux10/2x7
-Xwire90@0 net@0 sT wire90-704_3-layer_1-width_3
-Xwire90@1 net@1 sF wire90-704_3-layer_1-width_3
-.ENDS muxForPS
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4446_4-R_34_667m a b
-Ccap@0 gnd net@14 16.303f
-Ccap@1 gnd net@8 16.303f
-Ccap@2 gnd net@11 16.303f
-Rres@0 net@14 a 25.69
-Rres@1 net@11 net@14 51.381
-Rres@2 b net@8 25.69
-Rres@3 net@8 net@11 51.381
-.ENDS wire-C_0_011f-4446_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4446_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4446_4-R_34_667m
-.ENDS wire90-4446_4-layer_1-width_3
-
-*** CELL: registersM:dockPSreg{sch}
-.SUBCKT dockPSreg do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16]
-+m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26]
-+m1[27] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2]
-+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13]
-+ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23]
-+ps[24] ps[25] ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9]
-Xinv@0 do[ins] net@1 inv-X_40
-Xlx[1] hold[1] m1[1] ps[1] latch1in20B
-Xlx[2] hold[1] m1[2] ps[2] latch1in20B
-Xlx[3] hold[1] m1[3] ps[3] latch1in20B
-Xlx[4] hold[1] m1[4] ps[4] latch1in20B
-Xlx[5] hold[1] m1[5] ps[5] latch1in20B
-Xlx[6] hold[1] m1[6] ps[6] latch1in20B
-Xlx[7] hold[1] m1[7] ps[7] latch1in20B
-Xlx[8] hold[1] m1[8] ps[8] latch1in20B
-Xlx[9] hold[1] m1[9] ps[9] latch1in20B
-Xlx[10] hold[1] m1[10] ps[10] latch1in20B
-Xlx[11] hold[1] m1[11] ps[11] latch1in20B
-Xlx[12] hold[1] m1[12] ps[12] latch1in20B
-Xlx[13] hold[1] m1[13] ps[13] latch1in20B
-Xlx[14] hold[1] m1[14] ps[14] latch1in20B
-Xlx[15] hold[1] m1[15] ps[15] latch1in20B
-Xlx[16] hold[1] m1[16] ps[16] latch1in20B
-Xlx[17] hold[1] m1[17] ps[17] latch1in20B
-Xlx[18] hold[1] m1[18] ps[18] latch1in20B
-Xlx[19] hold[1] m1[19] ps[19] latch1in20B
-Xlx[20] hold[1] m1[20] ps[20] latch1in20B
-Xlx[21] hold[1] m1[21] ps[21] latch1in20B
-Xlx[22] hold[1] m1[22] ps[22] latch1in20B
-Xlx[23] hold[1] m1[23] ps[23] latch1in20B
-Xlx[24] hold[1] m1[24] ps[24] latch1in20B
-Xlx[25] hold[1] m1[25] ps[25] latch1in20B
-Xlx[26] hold[1] m1[26] ps[26] latch1in20B
-Xlx[27] hold[1] m1[27] ps[27] latch1in20B
-XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2]
-+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xwire90@0 net@1 hold[1] wire90-4446_4-layer_1-width_3
-.ENDS dockPSreg
-
-*** CELL: redFive:nand2n{sch}
-.SUBCKT nand2n-X_10 ina inb out
-Xnand2@0 ina inb out nand2-X_10
-.ENDS nand2n-X_10
-
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_10 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_10
-XNMOS@1 out ina gnd NMOSx-X_10
-Xpms2_sy@0 out ina inb pms2_sy-X_10
-.ENDS nor2_sy-X_10
-
-*** CELL: redFive:nor2n_sy{sch}
-.SUBCKT nor2n_sy-X_10 ina inb out
-Xnor2@0 ina inb out nor2_sy-X_10
-.ENDS nor2n_sy-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-405_3-R_34_667m a b
-Ccap@0 gnd net@14 1.486f
-Ccap@1 gnd net@8 1.486f
-Ccap@2 gnd net@11 1.486f
-Rres@0 net@14 a 2.342
-Rres@1 net@11 net@14 4.683
-Rres@2 b net@8 2.342
-Rres@3 net@8 net@11 4.683
-.ENDS wire-C_0_011f-405_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-405_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-405_3-R_34_667m
-.ENDS wire90-405_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-385_8-R_34_667m a b
-Ccap@0 gnd net@14 1.415f
-Ccap@1 gnd net@8 1.415f
-Ccap@2 gnd net@11 1.415f
-Rres@0 net@14 a 2.229
-Rres@1 net@11 net@14 4.458
-Rres@2 b net@8 2.229
-Rres@3 net@8 net@11 4.458
-.ENDS wire-C_0_011f-385_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-385_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-385_8-R_34_667m
-.ENDS wire90-385_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-406_4-R_34_667m a b
-Ccap@0 gnd net@14 1.49f
-Ccap@1 gnd net@8 1.49f
-Ccap@2 gnd net@11 1.49f
-Rres@0 net@14 a 2.348
-Rres@1 net@11 net@14 4.696
-Rres@2 b net@8 2.348
-Rres@3 net@8 net@11 4.696
-.ENDS wire-C_0_011f-406_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-406_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-406_4-R_34_667m
-.ENDS wire90-406_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-329_2-R_34_667m a b
-Ccap@0 gnd net@14 1.207f
-Ccap@1 gnd net@8 1.207f
-Ccap@2 gnd net@11 1.207f
-Rres@0 net@14 a 1.902
-Rres@1 net@11 net@14 3.804
-Rres@2 b net@8 1.902
-Rres@3 net@8 net@11 3.804
-.ENDS wire-C_0_011f-329_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-329_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-329_2-R_34_667m
-.ENDS wire90-329_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-407_9-R_34_667m a b
-Ccap@0 gnd net@14 1.496f
-Ccap@1 gnd net@8 1.496f
-Ccap@2 gnd net@11 1.496f
-Rres@0 net@14 a 2.357
-Rres@1 net@11 net@14 4.714
-Rres@2 b net@8 2.357
-Rres@3 net@8 net@11 4.714
-.ENDS wire-C_0_011f-407_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-407_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-407_9-R_34_667m
-.ENDS wire90-407_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-247-R_34_667m a b
-Ccap@0 gnd net@14 0.906f
-Ccap@1 gnd net@8 0.906f
-Ccap@2 gnd net@11 0.906f
-Rres@0 net@14 a 1.427
-Rres@1 net@11 net@14 2.854
-Rres@2 b net@8 1.427
-Rres@3 net@8 net@11 2.854
-.ENDS wire-C_0_011f-247-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-247-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-247-R_34_667m
-.ENDS wire90-247-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-456_8-R_34_667m a b
-Ccap@0 gnd net@14 1.675f
-Ccap@1 gnd net@8 1.675f
-Ccap@2 gnd net@11 1.675f
-Rres@0 net@14 a 2.639
-Rres@1 net@11 net@14 5.279
-Rres@2 b net@8 2.639
-Rres@3 net@8 net@11 5.279
-.ENDS wire-C_0_011f-456_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-456_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-456_8-R_34_667m
-.ENDS wire90-456_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-477_4-R_34_667m a b
-Ccap@0 gnd net@14 1.75f
-Ccap@1 gnd net@8 1.75f
-Ccap@2 gnd net@11 1.75f
-Rres@0 net@14 a 2.758
-Rres@1 net@11 net@14 5.517
-Rres@2 b net@8 2.758
-Rres@3 net@8 net@11 5.517
-.ENDS wire-C_0_011f-477_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-477_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-477_4-R_34_667m
-.ENDS wire90-477_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-775_9-R_34_667m a b
-Ccap@0 gnd net@14 2.845f
-Ccap@1 gnd net@8 2.845f
-Ccap@2 gnd net@11 2.845f
-Rres@0 net@14 a 4.483
-Rres@1 net@11 net@14 8.966
-Rres@2 b net@8 4.483
-Rres@3 net@8 net@11 8.966
-.ENDS wire-C_0_011f-775_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-775_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-775_9-R_34_667m
-.ENDS wire90-775_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-480_2-R_34_667m a b
-Ccap@0 gnd net@14 1.761f
-Ccap@1 gnd net@8 1.761f
-Ccap@2 gnd net@11 1.761f
-Rres@0 net@14 a 2.774
-Rres@1 net@11 net@14 5.549
-Rres@2 b net@8 2.774
-Rres@3 net@8 net@11 5.549
-.ENDS wire-C_0_011f-480_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-480_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-480_2-R_34_667m
-.ENDS wire90-480_2-layer_1-width_3
-
-*** CELL: redFive:xor2{sch}
-.SUBCKT xor2-X_5 ina inaB inb inbB out
-Xnms2@0 out inb ina nms2-X_5
-Xnms2@1 out inbB inaB nms2-X_5
-Xpms2@0 out inbB ina pms2-X_5
-Xpms2@1 out inb inaB pms2-X_5
-.ENDS xor2-X_5
-
-*** CELL: oneHotM:ohXor{sch}
-.SUBCKT ohXor flag[F] flag[T] in[1][F] in[1][T] out
-Xxor2@0 in[1][T] in[1][F] flag[T] flag[F] out xor2-X_5
-.ENDS ohXor
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-357-R_34_667m a b
-Ccap@0 gnd net@14 1.309f
-Ccap@1 gnd net@8 1.309f
-Ccap@2 gnd net@11 1.309f
-Rres@0 net@14 a 2.063
-Rres@1 net@11 net@14 4.125
-Rres@2 b net@8 2.063
-Rres@3 net@8 net@11 4.125
-.ENDS wire-C_0_011f-357-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-357-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-357-R_34_667m
-.ENDS wire90-357-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-394_5-R_34_667m a b
-Ccap@0 gnd net@14 1.447f
-Ccap@1 gnd net@8 1.447f
-Ccap@2 gnd net@11 1.447f
-Rres@0 net@14 a 2.279
-Rres@1 net@11 net@14 4.559
-Rres@2 b net@8 2.279
-Rres@3 net@8 net@11 4.559
-.ENDS wire-C_0_011f-394_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-394_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-394_5-R_34_667m
-.ENDS wire90-394_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-372_2-R_34_667m a b
-Ccap@0 gnd net@14 1.365f
-Ccap@1 gnd net@8 1.365f
-Ccap@2 gnd net@11 1.365f
-Rres@0 net@14 a 2.15
-Rres@1 net@11 net@14 4.301
-Rres@2 b net@8 2.15
-Rres@3 net@8 net@11 4.301
-.ENDS wire-C_0_011f-372_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-372_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-372_2-R_34_667m
-.ENDS wire90-372_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-319_8-R_34_667m a b
-Ccap@0 gnd net@14 1.173f
-Ccap@1 gnd net@8 1.173f
-Ccap@2 gnd net@11 1.173f
-Rres@0 net@14 a 1.848
-Rres@1 net@11 net@14 3.695
-Rres@2 b net@8 1.848
-Rres@3 net@8 net@11 3.695
-.ENDS wire-C_0_011f-319_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-319_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-319_8-R_34_667m
-.ENDS wire90-319_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-386_5-R_34_667m a b
-Ccap@0 gnd net@14 1.417f
-Ccap@1 gnd net@8 1.417f
-Ccap@2 gnd net@11 1.417f
-Rres@0 net@14 a 2.233
-Rres@1 net@11 net@14 4.466
-Rres@2 b net@8 2.233
-Rres@3 net@8 net@11 4.466
-.ENDS wire-C_0_011f-386_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-386_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-386_5-R_34_667m
-.ENDS wire90-386_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-297_8-R_34_667m a b
-Ccap@0 gnd net@14 1.092f
-Ccap@1 gnd net@8 1.092f
-Ccap@2 gnd net@11 1.092f
-Rres@0 net@14 a 1.721
-Rres@1 net@11 net@14 3.441
-Rres@2 b net@8 1.721
-Rres@3 net@8 net@11 3.441
-.ENDS wire-C_0_011f-297_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-297_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-297_8-R_34_667m
-.ENDS wire90-297_8-layer_1-width_3
-
-*** CELL: oneHotM:xor6x12{sch}
-.SUBCKT xor6x12 all any flag[1][F] flag[1][T] flag[2][F] flag[2][T]
-+flag[3][F] flag[3][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T]
-+in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T]
-Xnand3in6@2 match[12T] match[34T] match[56T] any nand3in6_6sym
-Xnor3in3_@1 match[56F] match[34F] match[12F] all nor3in6_6sym
-XohMux@6 flag[1][F] flag[1][T] in[2][F] in[1][F] net@84 ohXor
-XohMux@7 flag[1][F] flag[1][T] in[2][T] in[1][T] net@91 ohXor
-XohMux@8 flag[2][F] flag[2][T] in[4][F] in[3][F] net@94 ohXor
-XohMux@9 flag[2][F] flag[2][T] in[4][T] in[3][T] net@93 ohXor
-XohMux@10 flag[3][F] flag[3][T] in[6][F] in[5][F] net@102 ohXor
-XohMux@11 flag[3][F] flag[3][T] in[6][T] in[5][T] net@101 ohXor
-Xwire90@0 net@94 match[34F] wire90-357-layer_1-width_3
-Xwire90@1 match[34T] net@93 wire90-394_5-layer_1-width_3
-Xwire90@2 net@102 match[56F] wire90-372_2-layer_1-width_3
-Xwire90@3 match[56T] net@101 wire90-319_8-layer_1-width_3
-Xwire90@4 net@84 match[12F] wire90-386_5-layer_1-width_3
-Xwire90@5 match[12T] net@91 wire90-297_8-layer_1-width_3
-.ENDS xor6x12
-
-*** CELL: oneHotM:aFlag{sch}
-.SUBCKT aFlag flag[1][F] flag[1][T] flag[1][clr] flag[1][set] flag[A][F]
-+flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] in[1][T] in[2][T]
-+in[3][T] in[4][T] in[5][T] in[6][T] mc
-Xinv@0 net@257 flag[1][T] inv-X_20
-Xinv@2 net@258 flag[1][F] inv-X_20
-Xinv@3 net@2 net@267 inv-X_10
-Xinv@4 mc net@305 inv-X_10
-XinvI@10 net@9 net@308 inv-X_5
-XinvI@11 net@176 net@306 inv-X_5
-Xinv[1] in[1][T] in[1][F] inv-X_10
-Xinv[2] in[2][T] in[2][F] inv-X_10
-Xinv[3] in[3][T] in[3][F] inv-X_10
-Xinv[4] in[4][T] in[4][F] inv-X_10
-Xinv[5] in[5][T] in[5][F] inv-X_10
-Xinv[6] in[6][T] in[6][F] inv-X_10
-Xnand2@0 net@5 net@2 net@9 nand2-X_5
-Xnand2@1 net@69 net@71 net@176 nand2-X_5
-Xnand2@2 net@51 net@267 net@239 nand2-X_5
-Xnand2@3 net@22 net@265 net@240 nand2-X_5
-Xnand2n@0 net@64 net@49 net@51 nand2n-X_10
-Xnand2n@1 net@172 net@50 net@22 nand2n-X_10
-Xnand2n@2 net@236 net@235 net@258 nand2n-X_10
-Xnand2n@3 net@259 net@234 net@257 nand2n-X_10
-Xnor2n_sy@0 flag[1][clr] flag[1][set] net@2 nor2n_sy-X_10
-XsucANDdr@0 net@305 net@308 flag[1][set] sucANDdri20
-XsucANDdr@3 net@319 net@306 flag[1][clr] sucANDdri20
-Xwire90@1 net@8 net@5 wire90-405_3-layer_1-width_3
-Xwire90@4 net@22 net@49 wire90-385_8-layer_1-width_3
-Xwire90@5 net@50 net@51 wire90-406_4-layer_1-width_3
-Xwire90@6 net@64 net@9 wire90-329_2-layer_1-width_3
-Xwire90@8 net@69 net@68 wire90-407_9-layer_1-width_3
-Xwire90@19 net@176 net@172 wire90-329_2-layer_1-width_3
-Xwire90@22 net@240 net@259 wire90-247-layer_1-width_3
-Xwire90@23 net@236 net@239 wire90-247-layer_1-width_3
-Xwire90@24 net@257 net@235 wire90-456_8-layer_1-width_3
-Xwire90@25 net@234 net@258 wire90-477_4-layer_1-width_3
-Xwire90@26 net@71 net@2 wire90-775_9-layer_1-width_3
-Xwire90@27 net@265 net@267 wire90-480_2-layer_1-width_3
-Xwire90@28 net@319 net@305 wire90-385_8-layer_1-width_3
-Xxor6x12@0 net@68 net@8 flag[A][F] flag[A][T] flag[B][F] flag[B][T]
-+flag[C][F] flag[C][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T]
-+in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T] xor6x12
-.ENDS aFlag
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-218_6-R_34_667m a b
-Ccap@0 gnd net@14 0.802f
-Ccap@1 gnd net@8 0.802f
-Ccap@2 gnd net@11 0.802f
-Rres@0 net@14 a 1.263
-Rres@1 net@11 net@14 2.526
-Rres@2 b net@8 1.263
-Rres@3 net@8 net@11 2.526
-.ENDS wire-C_0_011f-218_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-218_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-218_6-R_34_667m
-.ENDS wire90-218_6-layer_1-width_3
-
-*** CELL: scanM:scanEx3h{sch}
-.SUBCKT scanEx3h dIn[1] dIn[2] dIn[3] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanCellE
-XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanCellE
-XscanCell@12 dIn[3] p1p p2p rd net@32 sout scanCellE
-Xwire90@0 net@18 net@31 wire90-218_6-layer_1-width_3
-Xwire90@1 net@20 net@32 wire90-218_6-layer_1-width_3
-.ENDS scanEx3h
-
-*** CELL: oneHotM:flags{sch}
-.SUBCKT flags flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
-+m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc
-+p1p p2p rd sin sout
-XaFlag@0 flag[A][F] flag[A][T] flag[A][clr] flag[A][set] flag[A][F]
-+flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[1] m1[2] m1[3]
-+m1[4] m1[5] m1[6] mc aFlag
-XaFlag@1 flag[B][F] flag[B][T] flag[B][clr] flag[B][set] flag[A][F]
-+flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[7] m1[8] m1[9]
-+m1[10] m1[11] m1[12] mc aFlag
-Xinv@0 flag[C][T] flag[C][F] inv-X_10
-XinvI@0 flag[A][F] s[1] inv-X_10
-XinvI@1 flag[B][F] s[2] inv-X_10
-XinvI@2 flag[C][F] s[3] inv-X_10
-XscanEx3h@0 s[1] s[2] s[3] mc p1p p2p rd sin sout scanEx3h
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-.ENDS flags
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-979-R_34_667m a b
-Ccap@0 gnd net@14 3.59f
-Ccap@1 gnd net@8 3.59f
-Ccap@2 gnd net@11 3.59f
-Rres@0 net@14 a 5.656
-Rres@1 net@11 net@14 11.313
-Rres@2 b net@8 5.656
-Rres@3 net@8 net@11 11.313
-.ENDS wire-C_0_011f-979-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-979-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-979-R_34_667m
-.ENDS wire90-979-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-704_9-R_34_667m a b
-Ccap@0 gnd net@14 2.585f
-Ccap@1 gnd net@8 2.585f
-Ccap@2 gnd net@11 2.585f
-Rres@0 net@14 a 4.073
-Rres@1 net@11 net@14 8.146
-Rres@2 b net@8 4.073
-Rres@3 net@8 net@11 8.146
-.ENDS wire-C_0_011f-704_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-704_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-704_9-R_34_667m
-.ENDS wire90-704_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-784_7-R_34_667m a b
-Ccap@0 gnd net@14 2.877f
-Ccap@1 gnd net@8 2.877f
-Ccap@2 gnd net@11 2.877f
-Rres@0 net@14 a 4.534
-Rres@1 net@11 net@14 9.068
-Rres@2 b net@8 4.534
-Rres@3 net@8 net@11 9.068
-.ENDS wire-C_0_011f-784_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-784_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-784_7-R_34_667m
-.ENDS wire90-784_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-631_7-R_34_667m a b
-Ccap@0 gnd net@14 2.316f
-Ccap@1 gnd net@8 2.316f
-Ccap@2 gnd net@11 2.316f
-Rres@0 net@14 a 3.65
-Rres@1 net@11 net@14 7.3
-Rres@2 b net@8 3.65
-Rres@3 net@8 net@11 7.3
-.ENDS wire-C_0_011f-631_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-631_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-631_7-R_34_667m
-.ENDS wire90-631_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-328_2-R_34_667m a b
-Ccap@0 gnd net@14 1.203f
-Ccap@1 gnd net@8 1.203f
-Ccap@2 gnd net@11 1.203f
-Rres@0 net@14 a 1.896
-Rres@1 net@11 net@14 3.793
-Rres@2 b net@8 1.896
-Rres@3 net@8 net@11 3.793
-.ENDS wire-C_0_011f-328_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-328_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-328_2-R_34_667m
-.ENDS wire90-328_2-layer_1-width_3
-
-*** CELL: loopCountM:calculate{sch}
-.SUBCKT calculate bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] do[2] do[3] do[4]
-+do[5] do[6] zero zoo
-Xinv@0 net@257 do[2] inv-X_10
-Xinv@1 bit[2] net@128 inv-X_10
-Xinv@2 bit[1] net@257 inv-X_10
-Xnand2@0 bit[3] bit[1] net@145 nand2-X_10
-Xnand2@1 bit[4] bit[2] net@195 nand2-X_10
-Xnand2@2 bit[3] bit[5] net@315 nand2-X_10
-Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667
-Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667
-Xnor2n@1 net@128 net@257 do[3] nor2n-X_10
-Xnor2n@2 net@145 net@146 do[4] nor2n-X_10
-Xnor2n@3 net@195 net@58 do[5] nor2n-X_10
-Xnor2n@4 net@221 net@56 do[6] nor2n-X_10
-Xnor2n@5 net@289 net@267 zoo nor2n-X_10
-Xnor2n@6 net@198 net@264 zero nor2n-X_10
-Xwire90@0 net@264 net@221 wire90-979-layer_1-width_3
-Xwire90@1 net@58 net@145 wire90-704_9-layer_1-width_3
-Xwire90@3 net@56 net@195 wire90-704_3-layer_1-width_3
-Xwire90@5 net@198 net@289 wire90-784_7-layer_1-width_3
-Xwire90@6 net@146 net@128 wire90-631_7-layer_1-width_3
-Xwire90@8 net@267 net@315 wire90-328_2-layer_1-width_3
-.ENDS calculate
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_1_5 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_3
-XPMOS@1 d g2 net@2 PMOSx-X_3
-.ENDS pms2-X_1_5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-176_2-R_34_667m a b
-Ccap@0 gnd net@14 0.646f
-Ccap@1 gnd net@8 0.646f
-Ccap@2 gnd net@11 0.646f
-Rres@0 net@14 a 1.018
-Rres@1 net@11 net@14 2.036
-Rres@2 b net@8 1.018
-Rres@3 net@8 net@11 2.036
-.ENDS wire-C_0_011f-176_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-176_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-176_2-R_34_667m
-.ENDS wire90-176_2-layer_1-width_3
-
-*** CELL: latchesK:mlat1in5s{sch}
-.SUBCKT mlat1in5s c[F] c[T] in inC out[1]
-Xnand2@0 net@166 inC out[1] nand2-X_5
-Xnms2@2 net@173 in c[T] nms2-X_3
-Xnms2@3 net@173 out[1] c[F] nms2-X_3
-Xpms2@0 net@173 out[1] c[T] pms2-X_1_5
-Xpms2@1 net@173 in c[F] pms2-X_2_5
-Xwire90@19 net@173 net@166 wire90-176_2-layer_1-width_3
-.ENDS mlat1in5s
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_15 d g s
-MNMOSf@0 d g s gnd nch W='45*(1+ABN/sqrt(45*2))' L='2'
-+DELVTO='AVT0N/sqrt(45*2)'
-.ENDS NMOSx-X_15
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_15 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_30
-XPMOS@1 d g2 net@2 PMOSx-X_30
-.ENDS pms2-X_15
-
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_15 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_15
-XNMOS@1 out inb gnd NMOSx-X_15
-Xpms2@0 out ina inb pms2-X_15
-.ENDS nor2-X_15
-
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_15 ina inb out
-Xnor2@0 ina inb out nor2-X_15
-.ENDS nor2n-X_15
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_2 in out
-XNMOS@0 out in gnd NMOSx-X_4
-XPMOS@0 out in vdd PMOSx-X_2
-.ENDS invLT-X_2
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_1 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_2
-XPMOS@1 d g2 net@2 PMOSx-X_2
-.ENDS pms2-X_1
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-133_8-R_34_667m a b
-Ccap@0 gnd net@14 0.491f
-Ccap@1 gnd net@8 0.491f
-Ccap@2 gnd net@11 0.491f
-Rres@0 net@14 a 0.773
-Rres@1 net@11 net@14 1.546
-Rres@2 b net@8 0.773
-Rres@3 net@8 net@11 1.546
-.ENDS wire-C_0_011f-133_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-133_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-133_8-R_34_667m
-.ENDS wire90-133_8-layer_1-width_3
-
-*** CELL: latchesK:mlat1in5i{sch}
-.SUBCKT mlat1in5i c[F] c[T] in out
-XinvLT@0 out net@119 invLT-X_2
-Xnms2@2 out in c[T] nms2-X_5
-Xnms2@3 out net@114 c[F] nms2-X_2
-Xpms2@0 out net@114 c[T] pms2-X_1
-Xpms2@1 out in c[F] pms2-X_5
-Xwire90@19 net@114 net@119 wire90-133_8-layer_1-width_3
-.ENDS mlat1in5i
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_2 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_6
-XNMOS@1 net@7 g gnd NMOSx-X_6
-XNMOS@2 net@6 g2 net@7 NMOSx-X_6
-.ENDS nms3-X_2
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-200_9-R_34_667m a b
-Ccap@0 gnd net@14 0.737f
-Ccap@1 gnd net@8 0.737f
-Ccap@2 gnd net@11 0.737f
-Rres@0 net@14 a 1.161
-Rres@1 net@11 net@14 2.322
-Rres@2 b net@8 1.161
-Rres@3 net@8 net@11 2.322
-.ENDS wire-C_0_011f-200_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-200_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-200_9-R_34_667m
-.ENDS wire90-200_9-layer_1-width_3
-
-*** CELL: latchesK:mlat2in10i{sch}
-.SUBCKT mlat2in10i clA[F] clA[T] clB[F] clB[T] inA inB out[1]
-Xinv@0 out[1] net@33 inv-X_4
-Xnms2@0 out[1] inB clB[T] nms2-X_10
-Xnms2@1 out[1] inA clA[T] nms2-X_10
-Xnms3@0 out[1] clB[F] clA[F] net@33 nms3-X_2
-Xpms2@0 out[1] inB clB[F] pms2-X_10
-Xpms2@1 out[1] inA clA[F] pms2-X_10
-Xpms3@0 out[1] clA[T] clB[T] net@81 pms3-X_1
-Xwire90@1 net@81 net@33 wire90-200_9-layer_1-width_3
-.ENDS mlat2in10i
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-173_2-R_34_667m a b
-Ccap@0 gnd net@14 0.635f
-Ccap@1 gnd net@8 0.635f
-Ccap@2 gnd net@11 0.635f
-Rres@0 net@14 a 1.001
-Rres@1 net@11 net@14 2.001
-Rres@2 b net@8 1.001
-Rres@3 net@8 net@11 2.001
-.ENDS wire-C_0_011f-173_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-173_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-173_2-R_34_667m
-.ENDS wire90-173_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-381_1-R_34_667m a b
-Ccap@0 gnd net@14 1.397f
-Ccap@1 gnd net@8 1.397f
-Ccap@2 gnd net@11 1.397f
-Rres@0 net@14 a 2.202
-Rres@1 net@11 net@14 4.404
-Rres@2 b net@8 2.202
-Rres@3 net@8 net@11 4.404
-.ENDS wire-C_0_011f-381_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-381_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-381_1-R_34_667m
-.ENDS wire90-381_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-982_2-R_34_667m a b
-Ccap@0 gnd net@14 3.601f
-Ccap@1 gnd net@8 3.601f
-Ccap@2 gnd net@11 3.601f
-Rres@0 net@14 a 5.675
-Rres@1 net@11 net@14 11.35
-Rres@2 b net@8 5.675
-Rres@3 net@8 net@11 11.35
-.ENDS wire-C_0_011f-982_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-982_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-982_2-R_34_667m
-.ENDS wire90-982_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-523_4-R_34_667m a b
-Ccap@0 gnd net@14 1.919f
-Ccap@1 gnd net@8 1.919f
-Ccap@2 gnd net@11 1.919f
-Rres@0 net@14 a 3.024
-Rres@1 net@11 net@14 6.048
-Rres@2 b net@8 3.024
-Rres@3 net@8 net@11 6.048
-.ENDS wire-C_0_011f-523_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-523_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-523_4-R_34_667m
-.ENDS wire90-523_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-535_9-R_34_667m a b
-Ccap@0 gnd net@14 1.965f
-Ccap@1 gnd net@8 1.965f
-Ccap@2 gnd net@11 1.965f
-Rres@0 net@14 a 3.096
-Rres@1 net@11 net@14 6.193
-Rres@2 b net@8 3.096
-Rres@3 net@8 net@11 6.193
-.ENDS wire-C_0_011f-535_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-535_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-535_9-R_34_667m
-.ENDS wire90-535_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-555_1-R_34_667m a b
-Ccap@0 gnd net@14 2.035f
-Ccap@1 gnd net@8 2.035f
-Ccap@2 gnd net@11 2.035f
-Rres@0 net@14 a 3.207
-Rres@1 net@11 net@14 6.414
-Rres@2 b net@8 3.207
-Rres@3 net@8 net@11 6.414
-.ENDS wire-C_0_011f-555_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-555_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-555_1-R_34_667m
-.ENDS wire90-555_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-678_3-R_34_667m a b
-Ccap@0 gnd net@14 2.487f
-Ccap@1 gnd net@8 2.487f
-Ccap@2 gnd net@11 2.487f
-Rres@0 net@14 a 3.919
-Rres@1 net@11 net@14 7.838
-Rres@2 b net@8 3.919
-Rres@3 net@8 net@11 7.838
-.ENDS wire-C_0_011f-678_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-678_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-678_3-R_34_667m
-.ENDS wire90-678_3-layer_1-width_3
-
-*** CELL: loopCountM:ringB{sch}
-.SUBCKT ringB bit[1] count[F] count[T] do[1] inLO[1] load[F] load[T]
-Xinv@0 net@60 bit[1] inv-X_20
-Xinv@1 bit[1] net@67 inv-X_5
-Xinv@2 net@68 net@65 inv-X_10
-Xinv@3 xx[T] net@64 inv-X_10
-Xmlat1in5@0 xx[T] xx[F] net@66 net@9 mlat1in5i
-Xmlat1in5@1 count[T] count[F] do[1] net@77 mlat1in5i
-Xmlat2in1@0 load[F] load[T] xx[F] xx[T] inLO[1] net@63 net@61 mlat2in10i
-Xnor2n@0 net@78 count[F] net@84 nor2n-X_10
-Xwire90@1 net@67 net@68 wire90-173_2-layer_1-width_3
-Xwire90@2 net@65 net@66 wire90-381_1-layer_1-width_3
-Xwire90@3 net@60 net@61 wire90-982_2-layer_1-width_3
-Xwire90@5 net@63 net@9 wire90-523_4-layer_1-width_3
-Xwire90@6 net@64 xx[F] wire90-535_9-layer_1-width_3
-Xwire90@7 net@77 net@78 wire90-555_1-layer_1-width_3
-Xwire90@8 net@84 xx[T] wire90-678_3-layer_1-width_3
-.ENDS ringB
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1588-R_34_667m a b
-Ccap@0 gnd net@14 5.823f
-Ccap@1 gnd net@8 5.823f
-Ccap@2 gnd net@11 5.823f
-Rres@0 net@14 a 9.175
-Rres@1 net@11 net@14 18.35
-Rres@2 b net@8 9.175
-Rres@3 net@8 net@11 18.35
-.ENDS wire-C_0_011f-1588-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1588-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1588-R_34_667m
-.ENDS wire90-1588-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1311_2-R_34_667m a b
-Ccap@0 gnd net@14 4.808f
-Ccap@1 gnd net@8 4.808f
-Ccap@2 gnd net@11 4.808f
-Rres@0 net@14 a 7.576
-Rres@1 net@11 net@14 15.152
-Rres@2 b net@8 7.576
-Rres@3 net@8 net@11 15.152
-.ENDS wire-C_0_011f-1311_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1311_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1311_2-R_34_667m
-.ENDS wire90-1311_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1283_3-R_34_667m a b
-Ccap@0 gnd net@14 4.705f
-Ccap@1 gnd net@8 4.705f
-Ccap@2 gnd net@11 4.705f
-Rres@0 net@14 a 7.415
-Rres@1 net@11 net@14 14.829
-Rres@2 b net@8 7.415
-Rres@3 net@8 net@11 14.829
-.ENDS wire-C_0_011f-1283_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1283_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1283_3-R_34_667m
-.ENDS wire90-1283_3-layer_1-width_3
-
-*** CELL: loopCountM:ilcEven{sch}
-.SUBCKT ilcEven bit[2] bit[4] bit[6] bit[8] do[2] do[4] do[6] ilc[decLO]
-+ilc[torpLO] inLO[2] inLO[4] inLO[6] inLO[8] load[T] zero
-Xinv@7 count[T] net@273 inv-X_30
-Xinv@8 load[T] net@275 inv-X_30
-Xmlat1in5@1 load[F] load[T] inLO[8] ilc[torpLO] bit[8] mlat1in5s
-Xnor2n@0 zero ilc[decLO] net@365 nor2n-X_15
-XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
-XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
-XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
-Xwire90@8 net@273 count[F] wire90-1588-layer_1-width_3
-Xwire90@9 net@275 load[F] wire90-1311_2-layer_1-width_3
-Xwire90@10 net@365 count[T] wire90-1283_3-layer_1-width_3
-.ENDS ilcEven
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-268_2-R_34_667m a b
-Ccap@0 gnd net@14 0.983f
-Ccap@1 gnd net@8 0.983f
-Ccap@2 gnd net@11 0.983f
-Rres@0 net@14 a 1.55
-Rres@1 net@11 net@14 3.099
-Rres@2 b net@8 1.55
-Rres@3 net@8 net@11 3.099
-.ENDS wire-C_0_011f-268_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-268_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-268_2-R_34_667m
-.ENDS wire90-268_2-layer_1-width_3
-
-*** CELL: latchesK:mlat2in5s{sch}
-.SUBCKT mlat2in5s clA[F] clA[T] clB[F] clB[T] inA inB inC out[1]
-Xnand2@0 net@147 inC out[1] nand2-X_5
-Xnms2@0 net@4 inB clB[T] nms2-X_3
-Xnms2@1 net@4 inA clA[T] nms2-X_3
-Xnms3@0 net@4 clA[F] out[1] clB[F] nms3-X_2
-Xpms2@0 net@4 inB clB[F] pms2-X_2_5
-Xpms2@1 net@4 inA clA[F] pms2-X_2_5
-Xpms3@0 net@4 clA[T] out[1] clB[T] pms3-X_1
-Xwire90@0 net@4 net@147 wire90-268_2-layer_1-width_3
-.ENDS mlat2in5s
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1320_5-R_34_667m a b
-Ccap@0 gnd net@14 4.842f
-Ccap@1 gnd net@8 4.842f
-Ccap@2 gnd net@11 4.842f
-Rres@0 net@14 a 7.63
-Rres@1 net@11 net@14 15.259
-Rres@2 b net@8 7.63
-Rres@3 net@8 net@11 15.259
-.ENDS wire-C_0_011f-1320_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1320_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1320_5-R_34_667m
-.ENDS wire90-1320_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-316_3-R_34_667m a b
-Ccap@0 gnd net@14 1.16f
-Ccap@1 gnd net@8 1.16f
-Ccap@2 gnd net@11 1.16f
-Rres@0 net@14 a 1.828
-Rres@1 net@11 net@14 3.655
-Rres@2 b net@8 1.828
-Rres@3 net@8 net@11 3.655
-.ENDS wire-C_0_011f-316_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-316_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-316_3-R_34_667m
-.ENDS wire90-316_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-389_4-R_34_667m a b
-Ccap@0 gnd net@14 1.428f
-Ccap@1 gnd net@8 1.428f
-Ccap@2 gnd net@11 1.428f
-Rres@0 net@14 a 2.25
-Rres@1 net@11 net@14 4.5
-Rres@2 b net@8 2.25
-Rres@3 net@8 net@11 4.5
-.ENDS wire-C_0_011f-389_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-389_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-389_4-R_34_667m
-.ENDS wire90-389_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-302-R_34_667m a b
-Ccap@0 gnd net@14 1.107f
-Ccap@1 gnd net@8 1.107f
-Ccap@2 gnd net@11 1.107f
-Rres@0 net@14 a 1.745
-Rres@1 net@11 net@14 3.49
-Rres@2 b net@8 1.745
-Rres@3 net@8 net@11 3.49
-.ENDS wire-C_0_011f-302-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-302-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-302-R_34_667m
-.ENDS wire90-302-layer_1-width_3
-
-*** CELL: loopCountM:ilcOdd{sch}
-.SUBCKT ilcOdd bit[1] bit[3] bit[5] bit[7] do[3] do[5] do[7] ilc[decLO]
-+ilc[torpLO] inLO[1] inLO[3] inLO[5] load[T] zero
-Xinv@5 count[T] net@273 inv-X_30
-Xinv@6 load[T] net@275 inv-X_30
-Xinv@7 check[T] net@441 inv-X_5
-Xinv@8 ilc[decLO] net@461 inv-X_5
-Xinv@12 net@515 bit[7] inv-X_10
-Xmlat2in5@4 load[F] load[T] check[F] check[T] gnd do[7] ilc[torpLO] net@511
-+mlat2in5s
-Xnor2n@0 zero ilc[decLO] net@454 nor2n-X_15
-XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
-XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
-XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
-Xwire90@4 net@273 count[F] wire90-1588-layer_1-width_3
-Xwire90@5 net@275 load[F] wire90-1320_5-layer_1-width_3
-Xwire90@6 net@441 check[F] wire90-316_3-layer_1-width_3
-Xwire90@7 net@454 count[T] wire90-1283_3-layer_1-width_3
-Xwire90@8 net@461 check[T] wire90-389_4-layer_1-width_3
-Xwire90@9 net@515 net@511 wire90-302-layer_1-width_3
-.ENDS ilcOdd
-
-*** CELL: redFive:nms1{sch}
-.SUBCKT nms1-X_20 d g
-XNMOS@1 d g gnd NMOSx-X_20
-.ENDS nms1-X_20
-
-*** CELL: gates3inM:orNand10{sch}
-.SUBCKT orNand10 inA inB inC out
-XNMOSx@0 out inC net@14 NMOSx-X_10
-XNMOSx@1 out inB net@14 NMOSx-X_10
-Xnms1@0 net@14 inA nms1-X_20
-Xpms1@0 net@14 inA pms1-X_10
-Xpms2@0 out inC inB pms2-X_5
-.ENDS orNand10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-349_7-R_34_667m a b
-Ccap@0 gnd net@14 1.282f
-Ccap@1 gnd net@8 1.282f
-Ccap@2 gnd net@11 1.282f
-Rres@0 net@14 a 2.02
-Rres@1 net@11 net@14 4.041
-Rres@2 b net@8 2.02
-Rres@3 net@8 net@11 4.041
-.ENDS wire-C_0_011f-349_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-349_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-349_7-R_34_667m
-.ENDS wire90-349_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-488_8-R_34_667m a b
-Ccap@0 gnd net@14 1.792f
-Ccap@1 gnd net@8 1.792f
-Ccap@2 gnd net@11 1.792f
-Rres@0 net@14 a 2.824
-Rres@1 net@11 net@14 5.648
-Rres@2 b net@8 2.824
-Rres@3 net@8 net@11 5.648
-.ENDS wire-C_0_011f-488_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-488_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-488_8-R_34_667m
-.ENDS wire90-488_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-422_3-R_34_667m a b
-Ccap@0 gnd net@14 1.548f
-Ccap@1 gnd net@8 1.548f
-Ccap@2 gnd net@11 1.548f
-Rres@0 net@14 a 2.44
-Rres@1 net@11 net@14 4.88
-Rres@2 b net@8 2.44
-Rres@3 net@8 net@11 4.88
-.ENDS wire-C_0_011f-422_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-422_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-422_3-R_34_667m
-.ENDS wire90-422_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-498_3-R_34_667m a b
-Ccap@0 gnd net@14 1.827f
-Ccap@1 gnd net@8 1.827f
-Ccap@2 gnd net@11 1.827f
-Rres@0 net@14 a 2.879
-Rres@1 net@11 net@14 5.758
-Rres@2 b net@8 2.879
-Rres@3 net@8 net@11 5.758
-.ENDS wire-C_0_011f-498_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-498_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-498_3-R_34_667m
-.ENDS wire90-498_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-407_3-R_34_667m a b
-Ccap@0 gnd net@14 1.493f
-Ccap@1 gnd net@8 1.493f
-Ccap@2 gnd net@11 1.493f
-Rres@0 net@14 a 2.353
-Rres@1 net@11 net@14 4.707
-Rres@2 b net@8 2.353
-Rres@3 net@8 net@11 4.707
-.ENDS wire-C_0_011f-407_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-407_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-407_3-R_34_667m
-.ENDS wire90-407_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1077_6-R_34_667m a b
-Ccap@0 gnd net@14 3.951f
-Ccap@1 gnd net@8 3.951f
-Ccap@2 gnd net@11 3.951f
-Rres@0 net@14 a 6.226
-Rres@1 net@11 net@14 12.452
-Rres@2 b net@8 6.226
-Rres@3 net@8 net@11 12.452
-.ENDS wire-C_0_011f-1077_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1077_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1077_6-R_34_667m
-.ENDS wire90-1077_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-687_6-R_34_667m a b
-Ccap@0 gnd net@14 2.521f
-Ccap@1 gnd net@8 2.521f
-Ccap@2 gnd net@11 2.521f
-Rres@0 net@14 a 3.973
-Rres@1 net@11 net@14 7.946
-Rres@2 b net@8 3.973
-Rres@3 net@8 net@11 7.946
-.ENDS wire-C_0_011f-687_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-687_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-687_6-R_34_667m
-.ENDS wire90-687_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1261_9-R_34_667m a b
-Ccap@0 gnd net@14 4.627f
-Ccap@1 gnd net@8 4.627f
-Ccap@2 gnd net@11 4.627f
-Rres@0 net@14 a 7.291
-Rres@1 net@11 net@14 14.582
-Rres@2 b net@8 7.291
-Rres@3 net@8 net@11 14.582
-.ENDS wire-C_0_011f-1261_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1261_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1261_9-R_34_667m
-.ENDS wire90-1261_9-layer_1-width_3
-
-*** CELL: loopCountM:ilc{sch}
-.SUBCKT ilc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
-+ilc[decLO] ilc[do] ilc[load] ilc[mo] ilc[torpLO] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8]
-Xcalculat@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
-+do[5] do[6] net@474 do[7] calculate
-XilcEven@0 bitt[2] bitt[4] bitt[6] bitt[8] do[2] do[4] do[6] ilc[decLO]
-+ilc[torpLO] inLO[2] inLO[4] inLO[6] inLO[8] ilc[load] zero ilcEven
-XilcOdd@0 bitt[1] bitt[3] bitt[5] bitt[7] do[3] do[5] do[7] ilc[decLO]
-+ilc[torpLO] inLO[1] inLO[3] inLO[5] ilc[load] zero ilcOdd
-XinvI@1 net@450 ovf inv-X_5
-Xnand3@0 net@360 net@450 zero ilc[do] nand3-X_6_667
-XorNand10@0 net@360 ovf do[7] ilc[mo] orNand10
-Xwire90@1 wire90@1_a do[2] wire90-349_7-layer_1-width_3
-Xwire90@2 wire90@2_a do[3] wire90-488_8-layer_1-width_3
-Xwire90@3 wire90@3_a do[4] wire90-422_3-layer_1-width_3
-Xwire90@4 wire90@4_a do[5] wire90-498_3-layer_1-width_3
-Xwire90@5 wire90@5_a do[6] wire90-407_3-layer_1-width_3
-Xwire90@48 net@450 bitt[7] wire90-1077_6-layer_1-width_3
-Xwire90@49 net@360 bitt[8] wire90-687_6-layer_1-width_3
-Xwire90@51 zero net@474 wire90-1261_9-layer_1-width_3
-.ENDS ilc
-
-*** CELL: redFive:nand2n{sch}
-.SUBCKT nand2n-X_20 ina inb out
-Xnand2@0 ina inb out nand2-X_20
-.ENDS nand2n-X_20
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_22 d g s
-MPMOSf@0 d g s vdd pch W='132*(1+ABP/sqrt(132*2))' L='2'
-+DELVTO='AVT0P/sqrt(132*2)'
-.ENDS PMOSx-X_22
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_66 d g s
-MNMOSf@0 d g s gnd nch W='198*(1+ABN/sqrt(198*2))' L='2'
-+DELVTO='AVT0N/sqrt(198*2)'
-.ENDS NMOSx-X_66
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_22 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_66
-XNMOS@1 net@7 g gnd NMOSx-X_66
-XNMOS@2 net@6 g2 net@7 NMOSx-X_66
-.ENDS nms3-X_22
-
-*** CELL: redFive:nand3{sch}
-.SUBCKT nand3-X_22 ina inb inc out
-XPMOS@0 out inc vdd PMOSx-X_22
-XPMOS@1 out inb vdd PMOSx-X_22
-XPMOS@2 out ina vdd PMOSx-X_22
-Xnms3@0 out ina inb inc nms3-X_22
-.ENDS nand3-X_22
-
-*** CELL: gates3inM:nand3in44s{sch}
-.SUBCKT nand3in44s inA inB inC out
-Xnand3@0 inA inB inC out nand3-X_22
-Xnand3@1 inB inA inC out nand3-X_22
-.ENDS nand3in44s
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-321_9-R_34_667m a b
-Ccap@0 gnd net@14 1.18f
-Ccap@1 gnd net@8 1.18f
-Ccap@2 gnd net@11 1.18f
-Rres@0 net@14 a 1.86
-Rres@1 net@11 net@14 3.72
-Rres@2 b net@8 1.86
-Rres@3 net@8 net@11 3.72
-.ENDS wire-C_0_011f-321_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-321_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-321_9-R_34_667m
-.ENDS wire90-321_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-294-R_34_667m a b
-Ccap@0 gnd net@14 1.078f
-Ccap@1 gnd net@8 1.078f
-Ccap@2 gnd net@11 1.078f
-Rres@0 net@14 a 1.699
-Rres@1 net@11 net@14 3.397
-Rres@2 b net@8 1.699
-Rres@3 net@8 net@11 3.397
-.ENDS wire-C_0_011f-294-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-294-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-294-R_34_667m
-.ENDS wire90-294-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-572_3-R_34_667m a b
-Ccap@0 gnd net@14 2.098f
-Ccap@1 gnd net@8 2.098f
-Ccap@2 gnd net@11 2.098f
-Rres@0 net@14 a 3.307
-Rres@1 net@11 net@14 6.613
-Rres@2 b net@8 3.307
-Rres@3 net@8 net@11 6.613
-.ENDS wire-C_0_011f-572_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-572_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-572_3-R_34_667m
-.ENDS wire90-572_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-741_5-R_34_667m a b
-Ccap@0 gnd net@14 2.719f
-Ccap@1 gnd net@8 2.719f
-Ccap@2 gnd net@11 2.719f
-Rres@0 net@14 a 4.284
-Rres@1 net@11 net@14 8.568
-Rres@2 b net@8 4.284
-Rres@3 net@8 net@11 8.568
-.ENDS wire-C_0_011f-741_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-741_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-741_5-R_34_667m
-.ENDS wire90-741_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-783-R_34_667m a b
-Ccap@0 gnd net@14 2.871f
-Ccap@1 gnd net@8 2.871f
-Ccap@2 gnd net@11 2.871f
-Rres@0 net@14 a 4.524
-Rres@1 net@11 net@14 9.048
-Rres@2 b net@8 4.524
-Rres@3 net@8 net@11 9.048
-.ENDS wire-C_0_011f-783-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-783-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-783-R_34_667m
-.ENDS wire90-783-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1254_1-R_34_667m a b
-Ccap@0 gnd net@14 4.598f
-Ccap@1 gnd net@8 4.598f
-Ccap@2 gnd net@11 4.598f
-Rres@0 net@14 a 7.246
-Rres@1 net@11 net@14 14.492
-Rres@2 b net@8 7.246
-Rres@3 net@8 net@11 14.492
-.ENDS wire-C_0_011f-1254_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1254_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1254_1-R_34_667m
-.ENDS wire90-1254_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1300_1-R_34_667m a b
-Ccap@0 gnd net@14 4.767f
-Ccap@1 gnd net@8 4.767f
-Ccap@2 gnd net@11 4.767f
-Rres@0 net@14 a 7.512
-Rres@1 net@11 net@14 15.023
-Rres@2 b net@8 7.512
-Rres@3 net@8 net@11 15.023
-.ENDS wire-C_0_011f-1300_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1300_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1300_1-R_34_667m
-.ENDS wire90-1300_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-392_9-R_34_667m a b
-Ccap@0 gnd net@14 1.441f
-Ccap@1 gnd net@8 1.441f
-Ccap@2 gnd net@11 1.441f
-Rres@0 net@14 a 2.27
-Rres@1 net@11 net@14 4.54
-Rres@2 b net@8 2.27
-Rres@3 net@8 net@11 4.54
-.ENDS wire-C_0_011f-392_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-392_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-392_9-R_34_667m
-.ENDS wire90-392_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1154_9-R_34_667m a b
-Ccap@0 gnd net@14 4.235f
-Ccap@1 gnd net@8 4.235f
-Ccap@2 gnd net@11 4.235f
-Rres@0 net@14 a 6.673
-Rres@1 net@11 net@14 13.346
-Rres@2 b net@8 6.673
-Rres@3 net@8 net@11 13.346
-.ENDS wire-C_0_011f-1154_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1154_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1154_9-R_34_667m
-.ENDS wire90-1154_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-590_5-R_34_667m a b
-Ccap@0 gnd net@14 2.165f
-Ccap@1 gnd net@8 2.165f
-Ccap@2 gnd net@11 2.165f
-Rres@0 net@14 a 3.412
-Rres@1 net@11 net@14 6.824
-Rres@2 b net@8 3.412
-Rres@3 net@8 net@11 6.824
-.ENDS wire-C_0_011f-590_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-590_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-590_5-R_34_667m
-.ENDS wire90-590_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-174_7-R_34_667m a b
-Ccap@0 gnd net@14 0.641f
-Ccap@1 gnd net@8 0.641f
-Ccap@2 gnd net@11 0.641f
-Rres@0 net@14 a 1.009
-Rres@1 net@11 net@14 2.019
-Rres@2 b net@8 1.009
-Rres@3 net@8 net@11 2.019
-.ENDS wire-C_0_011f-174_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-174_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-174_7-R_34_667m
-.ENDS wire90-174_7-layer_1-width_3
-
-*** CELL: moveM:moveRepeat{sch}
-.SUBCKT moveRepeat do[ins] fire[T] in[D] in[T] sel[Di] sel[Mv] sel[Ti]
-+sel[Tp] succ[sf] torp winLO[M]
-Xarbiter2@0 net@131 net@128 torp in[D] arbiter2
-Xarbiter2@1 net@130 net@129 torp in[T] arbiter2
-XinvI@0 net@150 fire[T] inv-X_20
-XinvI@6 net@271 net@217 inv-X_5
-XinvI@7 net@224 invI@7_out inv-X_10
-Xnand2@2 net@224 do[ins] net@86 nand2-X_5
-Xnand2@5 winLO[M] sel[Mv] net@221 nand2-X_5
-Xnand2@6 sel[Tp] do[ins] net@254 nand2-X_10
-Xnand2n@0 sel[Di] net@11 net@57 nand2n-X_20
-Xnand2n@1 sel[Ti] net@53 net@60 nand2n-X_20
-Xnand3in4@0 net@159 net@127 net@98 winLO[M] nand3in44s
-Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_10
-Xnor2n@0 net@38 net@12 net@44 nor2n-X_10
-Xnor2n@1 net@38 net@32 net@43 nor2n-X_10
-Xnor2n@2 succ[sf] net@153 net@152 nor2n-X_20
-Xwire90@0 net@131 net@12 wire90-321_9-layer_1-width_3
-Xwire90@1 net@130 net@32 wire90-321_9-layer_1-width_3
-Xwire90@2 net@129 net@53 wire90-294-layer_1-width_3
-Xwire90@3 net@128 net@11 wire90-294-layer_1-width_3
-Xwire90@4 net@254 net@38 wire90-572_3-layer_1-width_3
-Xwire90@6 net@44 net@45 wire90-741_5-layer_1-width_3
-Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3
-Xwire90@8 net@60 net@127 wire90-1254_1-layer_1-width_3
-Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3
-Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3
-Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3
-Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3
-Xwire90@19 net@224 net@217 wire90-174_7-layer_1-width_3
-Xwire90@20 net@271 net@221 wire90-174_7-layer_1-width_3
-.ENDS moveRepeat
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-362_9-R_34_667m a b
-Ccap@0 gnd net@14 1.331f
-Ccap@1 gnd net@8 1.331f
-Ccap@2 gnd net@11 1.331f
-Rres@0 net@14 a 2.097
-Rres@1 net@11 net@14 4.194
-Rres@2 b net@8 2.097
-Rres@3 net@8 net@11 4.194
-.ENDS wire-C_0_011f-362_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-362_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-362_9-R_34_667m
-.ENDS wire90-362_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-658-R_34_667m a b
-Ccap@0 gnd net@14 2.413f
-Ccap@1 gnd net@8 2.413f
-Ccap@2 gnd net@11 2.413f
-Rres@0 net@14 a 3.802
-Rres@1 net@11 net@14 7.604
-Rres@2 b net@8 3.802
-Rres@3 net@8 net@11 7.604
-.ENDS wire-C_0_011f-658-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-658-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-658-R_34_667m
-.ENDS wire90-658-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-269_9-R_34_667m a b
-Ccap@0 gnd net@14 0.99f
-Ccap@1 gnd net@8 0.99f
-Ccap@2 gnd net@11 0.99f
-Rres@0 net@14 a 1.559
-Rres@1 net@11 net@14 3.119
-Rres@2 b net@8 1.559
-Rres@3 net@8 net@11 3.119
-.ENDS wire-C_0_011f-269_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-269_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-269_9-R_34_667m
-.ENDS wire90-269_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-483_1-R_34_667m a b
-Ccap@0 gnd net@14 1.771f
-Ccap@1 gnd net@8 1.771f
-Ccap@2 gnd net@11 1.771f
-Rres@0 net@14 a 2.791
-Rres@1 net@11 net@14 5.582
-Rres@2 b net@8 2.791
-Rres@3 net@8 net@11 5.582
-.ENDS wire-C_0_011f-483_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-483_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-483_1-R_34_667m
-.ENDS wire90-483_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1036_9-R_34_667m a b
-Ccap@0 gnd net@14 3.802f
-Ccap@1 gnd net@8 3.802f
-Ccap@2 gnd net@11 3.802f
-Rres@0 net@14 a 5.991
-Rres@1 net@11 net@14 11.982
-Rres@2 b net@8 5.991
-Rres@3 net@8 net@11 11.982
-.ENDS wire-C_0_011f-1036_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1036_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1036_9-R_34_667m
-.ENDS wire90-1036_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-182_6-R_34_667m a b
-Ccap@0 gnd net@14 0.67f
-Ccap@1 gnd net@8 0.67f
-Ccap@2 gnd net@11 0.67f
-Rres@0 net@14 a 1.055
-Rres@1 net@11 net@14 2.11
-Rres@2 b net@8 1.055
-Rres@3 net@8 net@11 2.11
-.ENDS wire-C_0_011f-182_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-182_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-182_6-R_34_667m
-.ENDS wire90-182_6-layer_1-width_3
-
-*** CELL: moveM:moveOut{sch}
-.SUBCKT moveOut do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[decLO]
-+ilc[do] ilc[mo] ilc[torpLO] mc pred[D] pred[T] s[1] s[2] s[3] sel[Di] sel[Mv]
-+sel[Ti] sel[Tp] succ[sf]
-Xinv@9 fire[T] net@326 inv-X_5
-Xinv@10 ilc[do] net@221 inv-X_10
-Xinv@13 pred[T] net@194 inv-X_5
-Xinv@14 pred[D] net@227 inv-X_5
-Xinv@15 epi[torp] net@29 inv-X_5
-Xinv@16 fire[T] ilc[torpLO] inv-X_20
-XinvI@9 net@194 s[1] inv-X_10
-XinvI@10 net@227 s[2] inv-X_10
-XinvI@11 net@29 s[3] inv-X_10
-XmoveRepe@0 do[ins] fire[T] pred[D] pred[T] sel[Di] sel[Mv] sel[Ti] sel[Tp]
-+succ[sf] epi[torp] ilc[decLO] moveRepeat
-Xnand2@2 ilc[do] sel[Di] net@208 nand2-X_5
-Xnand2@3 ilc[do] sel[Ti] net@207 nand2-X_5
-Xnand2@4 sel[Tp] net@250 doneLO[M] nand2-X_20
-Xnor2n@1 ilc[mo] ilc[decLO] net@250 nor2n-X_10
-Xnor2n@5 net@206 ilc[decLO] net@203 nor2n-X_10
-Xnor2n@6 net@205 ilc[decLO] net@204 nor2n-X_10
-Xnor2n@7 net@220 ilc[decLO] fire[M] nor2n-X_20
-Xpms1@0 flag[D][set] net@327 pms1-X_20
-XpredDri2@0 fire[T] mc epi[torp] predDri20wMC
-XpredDri2@3 net@201 mc pred[D] predDri20wMC
-XpredDri2@4 net@200 mc pred[T] predDri20wMC
-XpredDri4@0 net@345 do[ins] predDri40
-XpredDri4@1 net@340 do[ins] predDri40
-Xwire90@9 net@206 net@208 wire90-362_9-layer_1-width_3
-Xwire90@10 net@220 net@221 wire90-658-layer_1-width_3
-Xwire90@11 net@200 net@204 wire90-269_9-layer_1-width_3
-Xwire90@12 net@201 net@203 wire90-269_9-layer_1-width_3
-Xwire90@13 net@205 net@207 wire90-362_9-layer_1-width_3
-Xwire90@15 net@345 net@250 wire90-483_1-layer_1-width_3
-Xwire90@16 net@340 fire[T] wire90-1036_9-layer_1-width_3
-Xwire90@17 net@326 net@327 wire90-182_6-layer_1-width_3
-.ENDS moveOut
-
-*** CELL: scanM:scanEx1h{sch}
-.SUBCKT scanEx1h dIn[1] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin sout scanCellE
-.ENDS scanEx1h
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-297_9-R_34_667m a b
-Ccap@0 gnd net@14 1.092f
-Ccap@1 gnd net@8 1.092f
-Ccap@2 gnd net@11 1.092f
-Rres@0 net@14 a 1.721
-Rres@1 net@11 net@14 3.442
-Rres@2 b net@8 1.721
-Rres@3 net@8 net@11 3.442
-.ENDS wire-C_0_011f-297_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-297_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-297_9-R_34_667m
-.ENDS wire90-297_9-layer_1-width_3
-
-*** CELL: scanM:scanEx2h{sch}
-.SUBCKT scanEx2h dIn[1] dIn[2] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanCellE
-XscanCell@11 dIn[2] p1p p2p rd net@31 sout scanCellE
-Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
-.ENDS scanEx2h
-
-*** CELL: scanM:scanEx4h{sch}
-.SUBCKT scanEx4h dIn[1] dIn[2] dIn[3] dIn[4] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanCellE
-XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanCellE
-XscanCell@12 dIn[3] p1p p2p rd net@32 net@24 scanCellE
-XscanCell@13 dIn[4] p1p p2p rd net@33 sout scanCellE
-Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
-Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
-Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3
-.ENDS scanEx4h
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-494_9-R_34_667m a b
-Ccap@0 gnd net@14 1.815f
-Ccap@1 gnd net@8 1.815f
-Ccap@2 gnd net@11 1.815f
-Rres@0 net@14 a 2.859
-Rres@1 net@11 net@14 5.719
-Rres@2 b net@8 2.859
-Rres@3 net@8 net@11 5.719
-.ENDS wire-C_0_011f-494_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-494_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-494_9-R_34_667m
-.ENDS wire90-494_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-569_3-R_34_667m a b
-Ccap@0 gnd net@14 2.087f
-Ccap@1 gnd net@8 2.087f
-Ccap@2 gnd net@11 2.087f
-Rres@0 net@14 a 3.289
-Rres@1 net@11 net@14 6.579
-Rres@2 b net@8 3.289
-Rres@3 net@8 net@11 6.579
-.ENDS wire-C_0_011f-569_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-569_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-569_3-R_34_667m
-.ENDS wire90-569_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1618_1-R_34_667m a b
-Ccap@0 gnd net@14 5.933f
-Ccap@1 gnd net@8 5.933f
-Ccap@2 gnd net@11 5.933f
-Rres@0 net@14 a 9.349
-Rres@1 net@11 net@14 18.698
-Rres@2 b net@8 9.349
-Rres@3 net@8 net@11 18.698
-.ENDS wire-C_0_011f-1618_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1618_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1618_1-R_34_667m
-.ENDS wire90-1618_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1538_5-R_34_667m a b
-Ccap@0 gnd net@14 5.641f
-Ccap@1 gnd net@8 5.641f
-Ccap@2 gnd net@11 5.641f
-Rres@0 net@14 a 8.889
-Rres@1 net@11 net@14 17.778
-Rres@2 b net@8 8.889
-Rres@3 net@8 net@11 17.778
-.ENDS wire-C_0_011f-1538_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1538_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1538_5-R_34_667m
-.ENDS wire90-1538_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1876_2-R_34_667m a b
-Ccap@0 gnd net@14 6.879f
-Ccap@1 gnd net@8 6.879f
-Ccap@2 gnd net@11 6.879f
-Rres@0 net@14 a 10.84
-Rres@1 net@11 net@14 21.681
-Rres@2 b net@8 10.84
-Rres@3 net@8 net@11 21.681
-.ENDS wire-C_0_011f-1876_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1876_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1876_2-R_34_667m
-.ENDS wire90-1876_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1489_6-R_34_667m a b
-Ccap@0 gnd net@14 5.462f
-Ccap@1 gnd net@8 5.462f
-Ccap@2 gnd net@11 5.462f
-Rres@0 net@14 a 8.607
-Rres@1 net@11 net@14 17.213
-Rres@2 b net@8 8.607
-Rres@3 net@8 net@11 17.213
-.ENDS wire-C_0_011f-1489_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1489_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1489_6-R_34_667m
-.ENDS wire90-1489_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1607_5-R_34_667m a b
-Ccap@0 gnd net@14 5.894f
-Ccap@1 gnd net@8 5.894f
-Ccap@2 gnd net@11 5.894f
-Rres@0 net@14 a 9.288
-Rres@1 net@11 net@14 18.576
-Rres@2 b net@8 9.288
-Rres@3 net@8 net@11 18.576
-.ENDS wire-C_0_011f-1607_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1607_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1607_5-R_34_667m
-.ENDS wire90-1607_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1251_5-R_34_667m a b
-Ccap@0 gnd net@14 4.589f
-Ccap@1 gnd net@8 4.589f
-Ccap@2 gnd net@11 4.589f
-Rres@0 net@14 a 7.231
-Rres@1 net@11 net@14 14.462
-Rres@2 b net@8 7.231
-Rres@3 net@8 net@11 14.462
-.ENDS wire-C_0_011f-1251_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1251_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1251_5-R_34_667m
-.ENDS wire90-1251_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1436-R_34_667m a b
-Ccap@0 gnd net@14 5.265f
-Ccap@1 gnd net@8 5.265f
-Ccap@2 gnd net@11 5.265f
-Rres@0 net@14 a 8.297
-Rres@1 net@11 net@14 16.594
-Rres@2 b net@8 8.297
-Rres@3 net@8 net@11 16.594
-.ENDS wire-C_0_011f-1436-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1436-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1436-R_34_667m
-.ENDS wire90-1436-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1429-R_34_667m a b
-Ccap@0 gnd net@14 5.24f
-Ccap@1 gnd net@8 5.24f
-Ccap@2 gnd net@11 5.24f
-Rres@0 net@14 a 8.256
-Rres@1 net@11 net@14 16.513
-Rres@2 b net@8 8.256
-Rres@3 net@8 net@11 16.513
-.ENDS wire-C_0_011f-1429-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1429-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1429-R_34_667m
-.ENDS wire90-1429-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3919-R_34_667m a b
-Ccap@0 gnd net@14 14.37f
-Ccap@1 gnd net@8 14.37f
-Ccap@2 gnd net@11 14.37f
-Rres@0 net@14 a 22.643
-Rres@1 net@11 net@14 45.286
-Rres@2 b net@8 22.643
-Rres@3 net@8 net@11 45.286
-.ENDS wire-C_0_011f-3919-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3919-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3919-R_34_667m
-.ENDS wire90-3919-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1219-R_34_667m a b
-Ccap@0 gnd net@14 4.47f
-Ccap@1 gnd net@8 4.47f
-Ccap@2 gnd net@11 4.47f
-Rres@0 net@14 a 7.043
-Rres@1 net@11 net@14 14.086
-Rres@2 b net@8 7.043
-Rres@3 net@8 net@11 14.086
-.ENDS wire-C_0_011f-1219-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1219-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1219-R_34_667m
-.ENDS wire90-1219-layer_1-width_3
-
-*** CELL: moveM:ilcMoveOut{sch}
-.SUBCKT ilcMoveOut do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[load]
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] mc p1p p2p pred[D]
-+pred[T] rd sel[Di] sel[Mv] sel[Ti] sel[Tp] sin sout succ[sf]
-Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
-+ilc[decLO] ilc[do] ilc[load] ilc[mo] ilc[torpLO] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] ilc
-XoutDockM@0 do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[decLO]
-+ilc[do] ilc[mo] ilc[torpLO] mc pred[D] pred[T] s[1] s[2] s[3] sel[Di] sel[Mv]
-+sel[Ti] sel[Tp] succ[sf] moveOut
-XscanEx1h@0 s[3] mc p1p p2p rd net@84 sout scanEx1h
-XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@85 net@84 scanEx2h
-XscanEx4h@0 bitt[1] bitt[3] bitt[5] bitt[7] mc p1p p2p rd sin net@50 scanEx4h
-XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@85
-+scanEx4h
-Xwire90@1 wire90@1_a ilc[mo] wire90-494_9-layer_1-width_3
-Xwire90@2 wire90@2_a ilc[do] wire90-569_3-layer_1-width_3
-Xwire90@3 wire90@3_a bitt[8] wire90-1618_1-layer_1-width_3
-Xwire90@4 wire90@4_a bitt[1] wire90-1538_5-layer_1-width_3
-Xwire90@5 wire90@5_a bitt[2] wire90-1876_2-layer_1-width_3
-Xwire90@6 wire90@6_a bitt[3] wire90-1489_6-layer_1-width_3
-Xwire90@7 wire90@7_a bitt[4] wire90-1607_5-layer_1-width_3
-Xwire90@8 wire90@8_a bitt[5] wire90-1251_5-layer_1-width_3
-Xwire90@9 wire90@9_a bitt[6] wire90-1436-layer_1-width_3
-Xwire90@10 wire90@10_a bitt[7] wire90-1429-layer_1-width_3
-Xwire90@11 wire90@11_a ilc[decLO] wire90-3919-layer_1-width_3
-Xwire90@12 wire90@12_a ilc[torpLO] wire90-1219-layer_1-width_3
-.ENDS ilcMoveOut
-
-*** CELL: loopCountM:muxForD{sch}
-.SUBCKT muxForD in[1] in[2] in[3] in[4] in[5] in[6] outLO[1] outLO[2]
-+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] sel
-Xinv@0 sel net@0 inv-X_20
-Xinv@1 sF net@1 inv-X_20
-Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] gnd outLO[1] outLO[2]
-+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] sF sT mux10/2x7
-Xwire90@0 net@0 sF wire90-704_3-layer_1-width_3
-Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3
-.ENDS muxForD
-
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_30 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_30
-XPMOS@1 out ina vdd PMOSx-X_30
-Xnms2_sy@0 out ina inb nms2_sy-X_30
-.ENDS nand2_sy-X_30
-
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_30 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_30
-.ENDS nand2n_sy-X_30
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_20 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_60
-XNMOS@1 net@7 g gnd NMOSx-X_60
-XNMOS@2 net@6 g2 net@7 NMOSx-X_60
-.ENDS nms3-X_20
-
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_3 d g
-XPMOS@0 d g vdd PMOSx-X_3
-.ENDS pms1-X_3
-
-*** CELL: predicateM:nand3in20sr{sch}
-.SUBCKT nand3in20sr inA inB inC out resetLO
-Xnms3a@0 out inA inB inC nms3-X_20
-Xpms1@0 out inC pms1-X_3
-Xpms1@1 out inB pms1-X_3
-Xpms1@2 out inA pms1-X_3
-Xpms1@3 out resetLO pms1-X_20
-.ENDS nand3in20sr
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
-Ccap@0 gnd net@14 1.581f
-Ccap@1 gnd net@8 1.581f
-Ccap@2 gnd net@11 1.581f
-Rres@0 net@14 a 2.492
-Rres@1 net@11 net@14 4.984
-Rres@2 b net@8 2.492
-Rres@3 net@8 net@11 4.984
-.ENDS wire-C_0_011f-431_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-431_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
-.ENDS wire90-431_3-layer_1-width_3
-
-*** CELL: predicateM:flagNOP{sch}
-.SUBCKT flagNOP do[ins] ps[Fl]
-Xinv@0 net@16 net@23 inv-X_5
-XinvI@0 net@22 net@21 inv-X_10
-XinvI@1 net@29 net@15 inv-X_5
-XinvI@2 net@15 invI@2_out inv-X_10
-XinvI@3 net@23 invI@3_out inv-X_10
-Xnand2@0 ps[Fl] do[ins] net@0 nand2-X_5
-XpredDri4@0 net@4 do[ins] predDri40
-Xwire90@0 net@0 net@29 wire90-431_3-layer_1-width_3
-Xwire90@1 net@15 net@16 wire90-414-layer_1-width_3
-Xwire90@2 net@4 net@21 wire90-431_3-layer_1-width_3
-Xwire90@3 net@22 net@23 wire90-414-layer_1-width_3
-.ENDS flagNOP
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-219_8-R_34_667m a b
-Ccap@0 gnd net@14 0.806f
-Ccap@1 gnd net@8 0.806f
-Ccap@2 gnd net@11 0.806f
-Rres@0 net@14 a 1.27
-Rres@1 net@11 net@14 2.54
-Rres@2 b net@8 1.27
-Rres@3 net@8 net@11 2.54
-.ENDS wire-C_0_011f-219_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-219_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-219_8-R_34_667m
-.ENDS wire90-219_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-60_2-R_34_667m a b
-Ccap@0 gnd net@14 0.221f
-Ccap@1 gnd net@8 0.221f
-Ccap@2 gnd net@11 0.221f
-Rres@0 net@14 a 0.348
-Rres@1 net@11 net@14 0.696
-Rres@2 b net@8 0.348
-Rres@3 net@8 net@11 0.696
-.ENDS wire-C_0_011f-60_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-60_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-60_2-R_34_667m
-.ENDS wire90-60_2-layer_1-width_3
-
-*** CELL: driversM:predCond20wMC{sch}
-.SUBCKT predCond20wMC cond in mc pred
-XNMOSx@1 pred mc gnd NMOSx-X_10
-XPMOSx@0 pred in net@217 PMOSx-X_3
-XPMOSx@1 pred cond net@210 PMOSx-X_3
-Xinv@0 pred net@145 inv-X_10
-Xnms2@0 pred cond in nms2-X_20
-Xpms2a@0 net@217 mc net@200 pms2-X_1_5
-Xwire90@0 net@200 net@145 wire90-219_8-layer_1-width_3
-Xwire90@1 net@217 net@210 wire90-60_2-layer_1-width_3
-.ENDS predCond20wMC
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-219_5-R_34_667m a b
-Ccap@0 gnd net@14 0.805f
-Ccap@1 gnd net@8 0.805f
-Ccap@2 gnd net@11 0.805f
-Rres@0 net@14 a 1.268
-Rres@1 net@11 net@14 2.536
-Rres@2 b net@8 1.268
-Rres@3 net@8 net@11 2.536
-.ENDS wire-C_0_011f-219_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-219_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-219_5-R_34_667m
-.ENDS wire90-219_5-layer_1-width_3
-
-*** CELL: driversM:predCond20wMS{sch}
-.SUBCKT predCond20wMS cond in mc pred
-XPMOSx@0 pred cond net@210 PMOSx-X_3
-XPMOSx@1 pred in net@217 PMOSx-X_3
-Xinv@0 pred net@145 inv-X_10
-XinvLT@0 mc net@240 invLT-X_5
-Xnms2@0 pred cond in nms2-X_20
-Xpms1@0 pred net@240 pms1-X_3
-Xpms2a@0 net@217 mc net@200 pms2-X_1_5
-Xwire90@0 net@200 net@145 wire90-219_5-layer_1-width_3
-Xwire90@1 net@217 net@210 wire90-60_2-layer_1-width_3
-.ENDS predCond20wMS
-
-*** CELL: predicateM:predFlagDri{sch}
-.SUBCKT predFlagDri fire[do] flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] mc sel[Fl] sel[rD]
-XbitAssig@0 bitAssignments
-Xpc[1] sel[Fl] fire[do] mc flag[A][set] predCond20wMC
-Xpc[2] sel[Fl] fire[do] mc flag[A][clr] predCond20wMC
-Xpc[3] sel[Fl] fire[do] mc flag[B][set] predCond20wMC
-Xpc[4] sel[Fl] fire[do] mc flag[B][clr] predCond20wMC
-XpredCond@0 sel[rD] fire[do] mc flag[D][clr] predCond20wMC
-XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS
-.ENDS predFlagDri
-
-*** CELL: orangeTSMC090nm:NMOSxwk{sch}
-.SUBCKT NMOSxwk-X_4 d g s
-MNMOSfwk@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2'
-+DELVTO='AVT0N/sqrt(12*2)'
-.ENDS NMOSxwk-X_4
-
-*** CELL: redFive:invK{sch}
-.SUBCKT invK-X_4 in out
-XNMOSwk@0 out in gnd NMOSxwk-X_4
-XPMOSwk@0 out in vdd PMOSxwk-X_4
-.ENDS invK-X_4
-
-*** CELL: redFive:nms1{sch}
-.SUBCKT nms1-X_10 d g
-XNMOS@1 d g gnd NMOSx-X_10
-.ENDS nms1-X_10
-
-*** CELL: driversM:sucDri40keep{sch}
-.SUBCKT sucDri40keep in mc succ
-XPMOSx@0 succ net@124 vdd PMOSx-X_40
-Xinv@2 in net@110 inv-X_10
-Xinv@3 succ net@115 inv-X_4
-XinvK@0 net@113 succ invK-X_4
-Xnms1@0 succ mc nms1-X_10
-Xwire90@0 net@113 net@115 wire90-124_7-layer_1-width_3
-Xwire90@1 net@110 net@124 wire90-503_4-layer_1-width_3
-.ENDS sucDri40keep
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-215_4-R_34_667m a b
-Ccap@0 gnd net@14 0.79f
-Ccap@1 gnd net@8 0.79f
-Ccap@2 gnd net@11 0.79f
-Rres@0 net@14 a 1.245
-Rres@1 net@11 net@14 2.489
-Rres@2 b net@8 1.245
-Rres@3 net@8 net@11 2.489
-.ENDS wire-C_0_011f-215_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-215_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-215_4-R_34_667m
-.ENDS wire90-215_4-layer_1-width_3
-
-*** CELL: predicateM:ohPredDo{sch}
-.SUBCKT ohPredDo do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set]
-+flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[Fl]
-+ps[do] ps[skip] s[3]
-XbitAssig@0 bitAssignments
-XflagNOP@0 do[ins] ps[Fl] flagNOP
-Xinv@0 do[ins] net@159 inv-X_5
-XinvI@0 net@156 s[3] inv-X_10
-XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] mc m1[Fl] m1[rD] predFlagDri
-XsucDri20@0 net@55 ps[skip] sucDri20
-XsucDri20@1 fire[do] ps[do] sucDri20
-XsucDri40@0 fire[do] mc do[ins] sucDri40keep
-Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3
-Xwire90@3 net@159 net@156 wire90-215_4-layer_1-width_3
-.ENDS ohPredDo
-
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_5 d g
-XPMOS@0 d g vdd PMOSx-X_5
-.ENDS pms1-X_5
-
-*** CELL: predicateM:ohSRxor{sch}
-.SUBCKT ohSRxor flag[F] flag[T] out resetLO sel[1] sel[2]
-Xnms2b@4 out flag[T] sel[1] nms2-X_5
-Xnms2b@5 out flag[F] sel[2] nms2-X_5
-Xpms1@0 out resetLO pms1-X_5
-Xpms2@0 out flag[T] sel[2] pms2-X_1
-Xpms2@1 out flag[F] sel[1] pms2-X_1
-.ENDS ohSRxor
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-395_6-R_34_667m a b
-Ccap@0 gnd net@14 1.451f
-Ccap@1 gnd net@8 1.451f
-Ccap@2 gnd net@11 1.451f
-Rres@0 net@14 a 2.286
-Rres@1 net@11 net@14 4.571
-Rres@2 b net@8 2.286
-Rres@3 net@8 net@11 4.571
-.ENDS wire-C_0_011f-395_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-395_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-395_6-R_34_667m
-.ENDS wire90-395_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-313_6-R_34_667m a b
-Ccap@0 gnd net@14 1.15f
-Ccap@1 gnd net@8 1.15f
-Ccap@2 gnd net@11 1.15f
-Rres@0 net@14 a 1.812
-Rres@1 net@11 net@14 3.624
-Rres@2 b net@8 1.812
-Rres@3 net@8 net@11 3.624
-.ENDS wire-C_0_011f-313_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-313_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-313_6-R_34_667m
-.ENDS wire90-313_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-339-R_34_667m a b
-Ccap@0 gnd net@14 1.243f
-Ccap@1 gnd net@8 1.243f
-Ccap@2 gnd net@11 1.243f
-Rres@0 net@14 a 1.959
-Rres@1 net@11 net@14 3.917
-Rres@2 b net@8 1.959
-Rres@3 net@8 net@11 3.917
-.ENDS wire-C_0_011f-339-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-339-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-339-R_34_667m
-.ENDS wire90-339-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-286_1-R_34_667m a b
-Ccap@0 gnd net@14 1.049f
-Ccap@1 gnd net@8 1.049f
-Ccap@2 gnd net@11 1.049f
-Rres@0 net@14 a 1.653
-Rres@1 net@11 net@14 3.306
-Rres@2 b net@8 1.653
-Rres@3 net@8 net@11 3.306
-.ENDS wire-C_0_011f-286_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-286_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-286_1-R_34_667m
-.ENDS wire90-286_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-358_1-R_34_667m a b
-Ccap@0 gnd net@14 1.313f
-Ccap@1 gnd net@8 1.313f
-Ccap@2 gnd net@11 1.313f
-Rres@0 net@14 a 2.069
-Rres@1 net@11 net@14 4.138
-Rres@2 b net@8 2.069
-Rres@3 net@8 net@11 4.138
-.ENDS wire-C_0_011f-358_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-358_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-358_1-R_34_667m
-.ENDS wire90-358_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-415_1-R_34_667m a b
-Ccap@0 gnd net@14 1.522f
-Ccap@1 gnd net@8 1.522f
-Ccap@2 gnd net@11 1.522f
-Rres@0 net@14 a 2.398
-Rres@1 net@11 net@14 4.797
-Rres@2 b net@8 2.398
-Rres@3 net@8 net@11 4.797
-.ENDS wire-C_0_011f-415_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-415_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-415_1-R_34_667m
-.ENDS wire90-415_1-layer_1-width_3
-
-*** CELL: predicateM:ohSRxor6x12{sch}
-.SUBCKT ohSRxor6x12 all any flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] in[1][F] in[1][T] in[2][F] in[2][T]
-+in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T]
-+resetLO
-Xnand3in6@3 match[12T] match[34T] match[56T] any nand3in6_6sym
-Xnor3in3_@2 match[12F] match[34F] match[56F] all nor3in6_6sym
-XohSRxor@6 flag[A][clr] flag[A][set] net@106 resetLO in[1][T] in[2][T]
-+ohSRxor
-XohSRxor@7 flag[A][clr] flag[A][set] net@107 resetLO in[1][F] in[2][F]
-+ohSRxor
-XohSRxor@8 flag[B][clr] flag[B][set] net@125 resetLO in[3][F] in[4][F]
-+ohSRxor
-XohSRxor@9 flag[B][clr] flag[B][set] net@122 resetLO in[3][T] in[4][T]
-+ohSRxor
-XohSRxor@10 flag[D][clr] flag[D][set] net@177 resetLO in[5][F] in[6][F]
-+ohSRxor
-XohSRxor@11 flag[D][clr] flag[D][set] net@178 resetLO in[5][T] in[6][T]
-+ohSRxor
-Xwire90@1 match[34T] net@122 wire90-395_6-layer_1-width_3
-Xwire90@3 match[56T] net@178 wire90-313_6-layer_1-width_3
-Xwire90@4 net@107 match[12F] wire90-339-layer_1-width_3
-Xwire90@5 match[12T] net@106 wire90-286_1-layer_1-width_3
-Xwire90@6 match[34F] net@125 wire90-358_1-layer_1-width_3
-Xwire90@7 net@177 match[56F] wire90-415_1-layer_1-width_3
-.ENDS ohSRxor6x12
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-625_1-R_34_667m a b
-Ccap@0 gnd net@14 2.292f
-Ccap@1 gnd net@8 2.292f
-Ccap@2 gnd net@11 2.292f
-Rres@0 net@14 a 3.612
-Rres@1 net@11 net@14 7.223
-Rres@2 b net@8 3.612
-Rres@3 net@8 net@11 7.223
-.ENDS wire-C_0_011f-625_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-625_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-625_1-R_34_667m
-.ENDS wire90-625_1-layer_1-width_3
-
-*** CELL: predicateM:ohPredPred{sch}
-.SUBCKT ohPredPred any do fire[both] flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] mc resetLO s[1] s[2]
-Xinv@0 net@51 resetLO inv-X_10
-Xinv@2 fire[both] net@54 inv-X_10
-XinvI@0 net@18 net@49 inv-X_5
-XinvI@4 net@66 s[1] inv-X_10
-XinvI@5 net@71 s[2] inv-X_10
-Xnor2_sy@5 flag[A][clr] flag[A][set] net@67 nor2_sy-X_5
-Xnor2_sy@6 m1cate[1][F] m1cate[1][T] net@62 nor2_sy-X_5
-XohSRxor6@1 do any flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
-+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
-+m1cate[6][F] m1cate[6][T] net@18 ohSRxor6x12
-Xpp[1] fire[both] mc m1cate[1][T] predDri20wMC
-Xpp[2] fire[both] mc m1cate[1][F] predDri20wMC
-Xpp[3] fire[both] mc m1cate[2][T] predDri20wMC
-Xpp[4] fire[both] mc m1cate[2][F] predDri20wMC
-Xpp[5] fire[both] mc m1cate[3][T] predDri20wMC
-Xpp[6] fire[both] mc m1cate[3][F] predDri20wMC
-Xpp[7] fire[both] mc m1cate[4][T] predDri20wMC
-Xpp[8] fire[both] mc m1cate[4][F] predDri20wMC
-Xpp[9] fire[both] mc m1cate[5][T] predDri20wMC
-Xpp[10] fire[both] mc m1cate[5][F] predDri20wMC
-Xpp[11] fire[both] mc m1cate[6][T] predDri20wMC
-Xpp[12] fire[both] mc m1cate[6][F] predDri20wMC
-Xwire90@1 net@54 net@18 wire90-625_1-layer_1-width_3
-Xwire90@3 net@49 net@51 wire90-142_6-layer_1-width_3
-Xwire90@4 net@62 net@66 wire90-215_4-layer_1-width_3
-Xwire90@5 net@67 net@71 wire90-215_4-layer_1-width_3
-.ENDS ohPredPred
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1000_9-R_34_667m a b
-Ccap@0 gnd net@14 3.67f
-Ccap@1 gnd net@8 3.67f
-Ccap@2 gnd net@11 3.67f
-Rres@0 net@14 a 5.783
-Rres@1 net@11 net@14 11.566
-Rres@2 b net@8 5.783
-Rres@3 net@8 net@11 11.566
-.ENDS wire-C_0_011f-1000_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1000_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1000_9-R_34_667m
-.ENDS wire90-1000_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-544-R_34_667m a b
-Ccap@0 gnd net@14 1.995f
-Ccap@1 gnd net@8 1.995f
-Ccap@2 gnd net@11 1.995f
-Rres@0 net@14 a 3.143
-Rres@1 net@11 net@14 6.286
-Rres@2 b net@8 3.143
-Rres@3 net@8 net@11 6.286
-.ENDS wire-C_0_011f-544-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-544-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-544-R_34_667m
-.ENDS wire90-544-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-863_3-R_34_667m a b
-Ccap@0 gnd net@14 3.165f
-Ccap@1 gnd net@8 3.165f
-Ccap@2 gnd net@11 3.165f
-Rres@0 net@14 a 4.988
-Rres@1 net@11 net@14 9.976
-Rres@2 b net@8 4.988
-Rres@3 net@8 net@11 9.976
-.ENDS wire-C_0_011f-863_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-863_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-863_3-R_34_667m
-.ENDS wire90-863_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-355_3-R_34_667m a b
-Ccap@0 gnd net@14 1.303f
-Ccap@1 gnd net@8 1.303f
-Ccap@2 gnd net@11 1.303f
-Rres@0 net@14 a 2.053
-Rres@1 net@11 net@14 4.106
-Rres@2 b net@8 2.053
-Rres@3 net@8 net@11 4.106
-.ENDS wire-C_0_011f-355_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-355_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-355_3-R_34_667m
-.ENDS wire90-355_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1035_5-R_34_667m a b
-Ccap@0 gnd net@14 3.797f
-Ccap@1 gnd net@8 3.797f
-Ccap@2 gnd net@11 3.797f
-Rres@0 net@14 a 5.983
-Rres@1 net@11 net@14 11.966
-Rres@2 b net@8 5.983
-Rres@3 net@8 net@11 11.966
-.ENDS wire-C_0_011f-1035_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1035_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1035_5-R_34_667m
-.ENDS wire90-1035_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-602_8-R_34_667m a b
-Ccap@0 gnd net@14 2.21f
-Ccap@1 gnd net@8 2.21f
-Ccap@2 gnd net@11 2.21f
-Rres@0 net@14 a 3.483
-Rres@1 net@11 net@14 6.966
-Rres@2 b net@8 3.483
-Rres@3 net@8 net@11 6.966
-.ENDS wire-C_0_011f-602_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-602_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-602_8-R_34_667m
-.ENDS wire90-602_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-613_9-R_34_667m a b
-Ccap@0 gnd net@14 2.251f
-Ccap@1 gnd net@8 2.251f
-Ccap@2 gnd net@11 2.251f
-Rres@0 net@14 a 3.547
-Rres@1 net@11 net@14 7.094
-Rres@2 b net@8 3.547
-Rres@3 net@8 net@11 7.094
-.ENDS wire-C_0_011f-613_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-613_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-613_9-R_34_667m
-.ENDS wire90-613_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-782-R_34_667m a b
-Ccap@0 gnd net@14 2.867f
-Ccap@1 gnd net@8 2.867f
-Ccap@2 gnd net@11 2.867f
-Rres@0 net@14 a 4.518
-Rres@1 net@11 net@14 9.036
-Rres@2 b net@8 4.518
-Rres@3 net@8 net@11 9.036
-.ENDS wire-C_0_011f-782-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-782-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-782-R_34_667m
-.ENDS wire90-782-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2516_8-R_34_667m a b
-Ccap@0 gnd net@14 9.228f
-Ccap@1 gnd net@8 9.228f
-Ccap@2 gnd net@11 9.228f
-Rres@0 net@14 a 14.542
-Rres@1 net@11 net@14 29.083
-Rres@2 b net@8 14.542
-Rres@3 net@8 net@11 29.083
-.ENDS wire-C_0_011f-2516_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2516_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2516_8-R_34_667m
-.ENDS wire90-2516_8-layer_1-width_3
-
-*** CELL: predicateM:ohPredAll{sch}
-.SUBCKT ohPredAll do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] m1[Fl] m1[rD] m1cate[1][F] m1cate[1][T]
-+m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T]
-+m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p ps[Fl] ps[do]
-+ps[skip] rd sin sout
-XbitAssig@0 bitAssignments
-XinvI@0 net@82 net@166 inv-X_40
-XinvI@1 net@63 net@144 inv-X_10
-XinvI@2 do[ins] net@193 inv-X_10
-Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10
-Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30
-Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr
-Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_10
-XohPredDo@1 do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set]
-+flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[Fl]
-+ps[do] ps[skip] s[3] ohPredDo
-XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred
-XscanEx3h@0 s[1] s[2] s[3] mc p1p p2p rd sin sout scanEx3h
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xwire90@0 net@39 net@11 wire90-1000_9-layer_1-width_3
-Xwire90@1 net@193 net@41 wire90-544-layer_1-width_3
-Xwire90@2 net@46 net@139 wire90-863_3-layer_1-width_3
-Xwire90@3 net@21 net@19 wire90-355_3-layer_1-width_3
-Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3
-Xwire90@5 net@147 net@63 wire90-602_8-layer_1-width_3
-Xwire90@6 net@92 net@94 wire90-613_9-layer_1-width_3
-Xwire90@7 fire[skip] net@144 wire90-782-layer_1-width_3
-Xwire90@9 fire[both] net@160 wire90-2516_8-layer_1-width_3
-Xwire90@11 net@166 fire[do] wire90-782-layer_1-width_3
-.ENDS ohPredAll
-
-*** CELL: centersJ:ctrAND2in100{sch}
-.SUBCKT ctrAND2in100 inA inB out
-Xinv@9 net@163 net@161 inv-X_30
-XinvI@1 net@162 out inv-X_100
-Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10
-Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
-Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
-.ENDS ctrAND2in100
-
-*** CELL: loopCountM:ilcLoad{sch}
-.SUBCKT ilcLoad do[ins] ilc[load] sel[Ld] sel[rD]
-XctrAND2i@0 sel[rD] net@12 ilc[load] ctrAND2in100
-Xnand2@0 sel[Ld] do[ins] net@23 nand2-X_5
-XpredDri4@0 ilc[load] do[ins] predDri40
-Xwire90@0 net@23 net@12 wire90-431_3-layer_1-width_3
-.ENDS ilcLoad
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_3_999 d g s
-MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2'
-+DELVTO='AVT0N/sqrt(11.997*2)'
-.ENDS NMOSx-X_3_999
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_1_333 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_3_999
-XNMOS@1 net@7 g gnd NMOSx-X_3_999
-XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999
-.ENDS nms3-X_1_333
-
-*** CELL: driversM:sucDri20or{sch}
-.SUBCKT sucDri20or inA inB succ
-Xinv@1 succ net@94 inv-X_4
-Xnms3b@0 succ net@142 inB inA nms3-X_1_333
-Xpms1@0 succ inA pms1-X_20
-Xpms1@1 succ inB pms1-X_20
-Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3
-.ENDS sucDri20or
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-406_2-R_34_667m a b
-Ccap@0 gnd net@14 1.489f
-Ccap@1 gnd net@8 1.489f
-Ccap@2 gnd net@11 1.489f
-Rres@0 net@14 a 2.347
-Rres@1 net@11 net@14 4.694
-Rres@2 b net@8 2.347
-Rres@3 net@8 net@11 4.694
-.ENDS wire-C_0_011f-406_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-406_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-406_2-R_34_667m
-.ENDS wire90-406_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-488_9-R_34_667m a b
-Ccap@0 gnd net@14 1.793f
-Ccap@1 gnd net@8 1.793f
-Ccap@2 gnd net@11 1.793f
-Rres@0 net@14 a 2.825
-Rres@1 net@11 net@14 5.65
-Rres@2 b net@8 2.825
-Rres@3 net@8 net@11 5.65
-.ENDS wire-C_0_011f-488_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-488_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-488_9-R_34_667m
-.ENDS wire90-488_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-348_7-R_34_667m a b
-Ccap@0 gnd net@14 1.279f
-Ccap@1 gnd net@8 1.279f
-Ccap@2 gnd net@11 1.279f
-Rres@0 net@14 a 2.015
-Rres@1 net@11 net@14 4.029
-Rres@2 b net@8 2.015
-Rres@3 net@8 net@11 4.029
-.ENDS wire-C_0_011f-348_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-348_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-348_7-R_34_667m
-.ENDS wire90-348_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-411_6-R_34_667m a b
-Ccap@0 gnd net@14 1.509f
-Ccap@1 gnd net@8 1.509f
-Ccap@2 gnd net@11 1.509f
-Rres@0 net@14 a 2.378
-Rres@1 net@11 net@14 4.756
-Rres@2 b net@8 2.378
-Rres@3 net@8 net@11 4.756
-.ENDS wire-C_0_011f-411_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-411_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-411_6-R_34_667m
-.ENDS wire90-411_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-147_3-R_34_667m a b
-Ccap@0 gnd net@14 0.54f
-Ccap@1 gnd net@8 0.54f
-Ccap@2 gnd net@11 0.54f
-Rres@0 net@14 a 0.851
-Rres@1 net@11 net@14 1.702
-Rres@2 b net@8 0.851
-Rres@3 net@8 net@11 1.702
-.ENDS wire-C_0_011f-147_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-147_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-147_3-R_34_667m
-.ENDS wire90-147_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-143_2-R_34_667m a b
-Ccap@0 gnd net@14 0.525f
-Ccap@1 gnd net@8 0.525f
-Ccap@2 gnd net@11 0.525f
-Rres@0 net@14 a 0.827
-Rres@1 net@11 net@14 1.655
-Rres@2 b net@8 0.827
-Rres@3 net@8 net@11 1.655
-.ENDS wire-C_0_011f-143_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-143_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-143_2-R_34_667m
-.ENDS wire90-143_2-layer_1-width_3
-
-*** CELL: loopCountM:olcControlD{sch}
-.SUBCKT olcControlD fire[Co] fire[zz] flag[D][clr] flag[D][set] olc[zero]
-+olc[zoo] s[1] s[2]
-Xinv@6 olc[zoo] net@180 inv-X_5
-Xinv@7 olc[zero] net@184 inv-X_5
-Xinv@18 flag[D][set] net@550 inv-X_5
-Xinv@19 flag[D][clr] net@545 inv-X_5
-XinvI@0 net@544 s[2] inv-X_10
-XinvI@1 net@549 s[1] inv-X_10
-Xnand2@0 net@288 fire[Co] net@286 nand2-X_5
-Xnand2@1 net@289 fire[zz] net@284 nand2-X_5
-Xnand2@2 olc[zoo] fire[Co] net@279 nand2-X_5
-Xnand2@3 olc[zero] fire[zz] net@281 nand2-X_5
-XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or
-XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or
-Xwire90@9 net@281 net@422 wire90-406_2-layer_1-width_3
-Xwire90@10 net@279 net@426 wire90-488_9-layer_1-width_3
-Xwire90@11 net@286 net@428 wire90-348_7-layer_1-width_3
-Xwire90@12 net@284 net@424 wire90-411_6-layer_1-width_3
-Xwire90@13 net@180 net@288 wire90-147_3-layer_1-width_3
-Xwire90@14 net@184 net@289 wire90-143_2-layer_1-width_3
-Xwire90@21 net@550 net@549 wire90-142_6-layer_1-width_3
-Xwire90@22 net@545 net@544 wire90-142_6-layer_1-width_3
-.ENDS olcControlD
-
-*** CELL: loopCountM:olcCount{sch}
-.SUBCKT olcCount do[ins] fire[Co] olc[dec] olc[zero] sel[Co]
-XctrAND1i@0 net@12 fire[Co] ctrAND1in30
-XctrAND2i@0 olc[zero] net@12 olc[dec] ctrAND2in100
-Xnand2@0 sel[Co] do[ins] net@23 nand2-X_10
-XpredDri4@0 fire[Co] do[ins] predDri40
-Xwire90@0 net@23 net@12 wire90-431_3-layer_1-width_3
-.ENDS olcCount
-
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_6 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_6
-.ENDS nand2n_sy-X_6
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_3 in out
-XNMOS@0 out in gnd NMOSx-X_6
-XPMOS@0 out in vdd PMOSx-X_3
-.ENDS invLT-X_3
-
-*** CELL: driversM:predDri10wMC{sch}
-.SUBCKT predDri10wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_10
-XNMOSx@1 pred mc gnd NMOSx-X_4
-XinvLT@0 pred net@145 invLT-X_3
-Xpms3@0 pred in net@180 mc pms3-X_1
-Xwire90@0 net@180 net@145 wire90-106_7-layer_1-width_3
-.ENDS predDri10wMC
-
-*** CELL: driversM:sucDri10{sch}
-.SUBCKT sucDri10 in succ
-Xinv@1 succ net@94 inv-X_4
-Xinv@2 in net@110 inv-X_4
-Xnms2@0 succ net@117 net@109 nms2-X_2
-Xpms1@0 succ net@109 pms1-X_10
-Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
-Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3
-.ENDS sucDri10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-306_9-R_34_667m a b
-Ccap@0 gnd net@14 1.125f
-Ccap@1 gnd net@8 1.125f
-Ccap@2 gnd net@11 1.125f
-Rres@0 net@14 a 1.773
-Rres@1 net@11 net@14 3.546
-Rres@2 b net@8 1.773
-Rres@3 net@8 net@11 3.546
-.ENDS wire-C_0_011f-306_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-306_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-306_9-R_34_667m
-.ENDS wire90-306_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-393_3-R_34_667m a b
-Ccap@0 gnd net@14 1.442f
-Ccap@1 gnd net@8 1.442f
-Ccap@2 gnd net@11 1.442f
-Rres@0 net@14 a 2.272
-Rres@1 net@11 net@14 4.545
-Rres@2 b net@8 2.272
-Rres@3 net@8 net@11 4.545
-.ENDS wire-C_0_011f-393_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-393_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-393_3-R_34_667m
-.ENDS wire90-393_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-299_4-R_34_667m a b
-Ccap@0 gnd net@14 1.098f
-Ccap@1 gnd net@8 1.098f
-Ccap@2 gnd net@11 1.098f
-Rres@0 net@14 a 1.73
-Rres@1 net@11 net@14 3.46
-Rres@2 b net@8 1.73
-Rres@3 net@8 net@11 3.46
-.ENDS wire-C_0_011f-299_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-299_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-299_4-R_34_667m
-.ENDS wire90-299_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-209_3-R_34_667m a b
-Ccap@0 gnd net@14 0.767f
-Ccap@1 gnd net@8 0.767f
-Ccap@2 gnd net@11 0.767f
-Rres@0 net@14 a 1.209
-Rres@1 net@11 net@14 2.419
-Rres@2 b net@8 1.209
-Rres@3 net@8 net@11 2.419
-.ENDS wire-C_0_011f-209_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-209_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-209_3-R_34_667m
-.ENDS wire90-209_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-264_2-R_34_667m a b
-Ccap@0 gnd net@14 0.969f
-Ccap@1 gnd net@8 0.969f
-Ccap@2 gnd net@11 0.969f
-Rres@0 net@14 a 1.526
-Rres@1 net@11 net@14 3.053
-Rres@2 b net@8 1.526
-Rres@3 net@8 net@11 3.053
-.ENDS wire-C_0_011f-264_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-264_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-264_2-R_34_667m
-.ENDS wire90-264_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1062_7-R_34_667m a b
-Ccap@0 gnd net@14 3.897f
-Ccap@1 gnd net@8 3.897f
-Ccap@2 gnd net@11 3.897f
-Rres@0 net@14 a 6.14
-Rres@1 net@11 net@14 12.28
-Rres@2 b net@8 6.14
-Rres@3 net@8 net@11 12.28
-.ENDS wire-C_0_011f-1062_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1062_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1062_7-R_34_667m
-.ENDS wire90-1062_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-136_4-R_34_667m a b
-Ccap@0 gnd net@14 0.5f
-Ccap@1 gnd net@8 0.5f
-Ccap@2 gnd net@11 0.5f
-Rres@0 net@14 a 0.788
-Rres@1 net@11 net@14 1.576
-Rres@2 b net@8 0.788
-Rres@3 net@8 net@11 1.576
-.ENDS wire-C_0_011f-136_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-136_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-136_4-R_34_667m
-.ENDS wire90-136_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-330_3-R_34_667m a b
-Ccap@0 gnd net@14 1.211f
-Ccap@1 gnd net@8 1.211f
-Ccap@2 gnd net@11 1.211f
-Rres@0 net@14 a 1.908
-Rres@1 net@11 net@14 3.817
-Rres@2 b net@8 1.908
-Rres@3 net@8 net@11 3.817
-.ENDS wire-C_0_011f-330_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-330_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-330_3-R_34_667m
-.ENDS wire90-330_3-layer_1-width_3
-
-*** CELL: loopCountM:olcLoad{sch}
-.SUBCKT olcLoad do[ins] doneLO[M] fire[zz] mc olc[load] sel[Ld] sel[rD]
-XctrAND3i@2 net@983 net@981 net@979 olc[load] ctrAND3in100A
-Xinv@28 net@905 net@908 inv-X_5
-Xinv@30 sel[rD] net@976 inv-X_5
-Xinv@32 net@1032 net@1057 inv-X_5
-Xinv@34 net@913 inv@34_out inv-X_10
-XinvI@7 net@929 net@913 inv-X_5
-XinvI@8 net@1046 net@937 inv-X_10
-Xnand2@5 sel[Ld] do[ins] net@956 nand2-X_5
-Xnand2@7 net@1035 do[2] net@1033 nand2-X_5
-Xnand2n_s@1 doneLO[M] net@908 fire[zz] nand2n_sy-X_6
-XpredDri1@0 net@979 mc do[2] predDri10wMC
-XpredDri4@0 net@1032 do[ins] predDri40
-XsucDri10@1 olc[load] do[2] sucDri10
-Xwire90@17 net@1033 net@929 wire90-306_9-layer_1-width_3
-Xwire90@25 net@956 net@979 wire90-393_3-layer_1-width_3
-Xwire90@39 net@1032 net@937 wire90-299_4-layer_1-width_3
-Xwire90@42 net@913 net@905 wire90-209_3-layer_1-width_3
-Xwire90@48 net@976 net@981 wire90-264_2-layer_1-width_3
-Xwire90@50 net@983 do[2] wire90-1062_7-layer_1-width_3
-Xwire90@51 net@1035 net@1057 wire90-136_4-layer_1-width_3
-Xwire90@52 net@908 net@1046 wire90-330_3-layer_1-width_3
-.ENDS olcLoad
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-716_7-R_34_667m a b
-Ccap@0 gnd net@14 2.628f
-Ccap@1 gnd net@8 2.628f
-Ccap@2 gnd net@11 2.628f
-Rres@0 net@14 a 4.141
-Rres@1 net@11 net@14 8.282
-Rres@2 b net@8 4.141
-Rres@3 net@8 net@11 8.282
-.ENDS wire-C_0_011f-716_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-716_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-716_7-R_34_667m
-.ENDS wire90-716_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-643_1-R_34_667m a b
-Ccap@0 gnd net@14 2.358f
-Ccap@1 gnd net@8 2.358f
-Ccap@2 gnd net@11 2.358f
-Rres@0 net@14 a 3.716
-Rres@1 net@11 net@14 7.431
-Rres@2 b net@8 3.716
-Rres@3 net@8 net@11 7.431
-.ENDS wire-C_0_011f-643_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-643_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-643_1-R_34_667m
-.ENDS wire90-643_1-layer_1-width_3
-
-*** CELL: loopCountM:loadORcount{sch}
-.SUBCKT loadORcount do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] mc
-+olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] sel[Co] sel[Ld] sel[rD]
-XilcLoad@0 do[ins] ilc[load] sel[Ld] sel[rD] ilcLoad
-XolcContr@1 net@885 net@880 flag[D][clr] flag[D][set] olc[zero] olc[zoo] s[1]
-+s[2] olcControlD
-XolcCount@0 do[ins] net@883 olc[dec] olc[zero] sel[Co] olcCount
-XolcLoad@0 do[ins] doneLO[M] net@882 mc olc[load] sel[Ld] sel[rD] olcLoad
-Xwire90@0 net@882 net@880 wire90-716_7-layer_1-width_3
-Xwire90@1 net@885 net@883 wire90-643_1-layer_1-width_3
-.ENDS loadORcount
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b
-Ccap@0 gnd net@14 6.469f
-Ccap@1 gnd net@8 6.469f
-Ccap@2 gnd net@11 6.469f
-Rres@0 net@14 a 10.194
-Rres@1 net@11 net@14 20.389
-Rres@2 b net@8 10.194
-Rres@3 net@8 net@11 20.389
-.ENDS wire-C_0_011f-1764_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1764_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m
-.ENDS wire90-1764_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b
-Ccap@0 gnd net@14 5.036f
-Ccap@1 gnd net@8 5.036f
-Ccap@2 gnd net@11 5.036f
-Rres@0 net@14 a 7.935
-Rres@1 net@11 net@14 15.87
-Rres@2 b net@8 7.935
-Rres@3 net@8 net@11 15.87
-.ENDS wire-C_0_011f-1373_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1373_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m
-.ENDS wire90-1373_4-layer_1-width_3
-
-*** CELL: loopCountM:olcEven{sch}
-.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2]
-+inLO[4] inLO[6] load[T]
-Xinv@2 count[T] net@210 inv-X_30
-Xinv@3 load[T] net@211 inv-X_30
-XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
-XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
-XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
-Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3
-Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3
-.ENDS olcEven
-
-*** CELL: loopCountM:olcOdd{sch}
-.SUBCKT olcOdd bit[1] bit[3] bit[5] count[T] do[3] do[5] inLO[1] inLO[3]
-+inLO[5] load[T]
-Xinv@2 load[T] net@307 inv-X_30
-Xinv@3 count[T] net@310 inv-X_30
-XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
-XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
-XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
-Xwire90@2 net@307 load[F] wire90-1373_4-layer_1-width_3
-Xwire90@3 net@310 count[F] wire90-1764_4-layer_1-width_3
-.ENDS olcOdd
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-380_7-R_34_667m a b
-Ccap@0 gnd net@14 1.396f
-Ccap@1 gnd net@8 1.396f
-Ccap@2 gnd net@11 1.396f
-Rres@0 net@14 a 2.2
-Rres@1 net@11 net@14 4.399
-Rres@2 b net@8 2.2
-Rres@3 net@8 net@11 4.399
-.ENDS wire-C_0_011f-380_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-380_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-380_7-R_34_667m
-.ENDS wire90-380_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-544_8-R_34_667m a b
-Ccap@0 gnd net@14 1.998f
-Ccap@1 gnd net@8 1.998f
-Ccap@2 gnd net@11 1.998f
-Rres@0 net@14 a 3.148
-Rres@1 net@11 net@14 6.295
-Rres@2 b net@8 3.148
-Rres@3 net@8 net@11 6.295
-.ENDS wire-C_0_011f-544_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-544_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-544_8-R_34_667m
-.ENDS wire90-544_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-478_3-R_34_667m a b
-Ccap@0 gnd net@14 1.754f
-Ccap@1 gnd net@8 1.754f
-Ccap@2 gnd net@11 1.754f
-Rres@0 net@14 a 2.764
-Rres@1 net@11 net@14 5.527
-Rres@2 b net@8 2.764
-Rres@3 net@8 net@11 5.527
-.ENDS wire-C_0_011f-478_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-478_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-478_3-R_34_667m
-.ENDS wire90-478_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-554_3-R_34_667m a b
-Ccap@0 gnd net@14 2.032f
-Ccap@1 gnd net@8 2.032f
-Ccap@2 gnd net@11 2.032f
-Rres@0 net@14 a 3.203
-Rres@1 net@11 net@14 6.405
-Rres@2 b net@8 3.203
-Rres@3 net@8 net@11 6.405
-.ENDS wire-C_0_011f-554_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-554_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-554_3-R_34_667m
-.ENDS wire90-554_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-463_3-R_34_667m a b
-Ccap@0 gnd net@14 1.699f
-Ccap@1 gnd net@8 1.699f
-Ccap@2 gnd net@11 1.699f
-Rres@0 net@14 a 2.677
-Rres@1 net@11 net@14 5.354
-Rres@2 b net@8 2.677
-Rres@3 net@8 net@11 5.354
-.ENDS wire-C_0_011f-463_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-463_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-463_3-R_34_667m
-.ENDS wire90-463_3-layer_1-width_3
-
-*** CELL: loopCountM:olc{sch}
-.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
-+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo]
-XcountLog@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
-+do[5] do[6] olc[zero] olc[zoo] calculate
-XolcEven@1 bitt[2] bitt[4] bitt[6] olc[dec] do[2] do[4] do[6] inLO[2] inLO[4]
-+inLO[6] olc[load] olcEven
-XolcOdd@2 bitt[1] bitt[3] bitt[5] olc[dec] do[3] do[5] inLO[1] inLO[3]
-+inLO[5] olc[load] olcOdd
-Xwire90@1 wire90@1_a do[2] wire90-380_7-layer_1-width_3
-Xwire90@2 wire90@2_a do[3] wire90-544_8-layer_1-width_3
-Xwire90@3 wire90@3_a do[4] wire90-478_3-layer_1-width_3
-Xwire90@4 wire90@4_a do[5] wire90-554_3-layer_1-width_3
-Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3
-.ENDS olc
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-849_4-R_34_667m a b
-Ccap@0 gnd net@14 3.114f
-Ccap@1 gnd net@8 3.114f
-Ccap@2 gnd net@11 3.114f
-Rres@0 net@14 a 4.908
-Rres@1 net@11 net@14 9.815
-Rres@2 b net@8 4.908
-Rres@3 net@8 net@11 9.815
-.ENDS wire-C_0_011f-849_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-849_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-849_4-R_34_667m
-.ENDS wire90-849_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-868_7-R_34_667m a b
-Ccap@0 gnd net@14 3.185f
-Ccap@1 gnd net@8 3.185f
-Ccap@2 gnd net@11 3.185f
-Rres@0 net@14 a 5.019
-Rres@1 net@11 net@14 10.038
-Rres@2 b net@8 5.019
-Rres@3 net@8 net@11 10.038
-.ENDS wire-C_0_011f-868_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-868_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-868_7-R_34_667m
-.ENDS wire90-868_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3939_8-R_34_667m a b
-Ccap@0 gnd net@14 14.446f
-Ccap@1 gnd net@8 14.446f
-Ccap@2 gnd net@11 14.446f
-Rres@0 net@14 a 22.763
-Rres@1 net@11 net@14 45.527
-Rres@2 b net@8 22.763
-Rres@3 net@8 net@11 45.527
-.ENDS wire-C_0_011f-3939_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3939_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3939_8-R_34_667m
-.ENDS wire90-3939_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3317_6-R_34_667m a b
-Ccap@0 gnd net@14 12.165f
-Ccap@1 gnd net@8 12.165f
-Ccap@2 gnd net@11 12.165f
-Rres@0 net@14 a 19.168
-Rres@1 net@11 net@14 38.337
-Rres@2 b net@8 19.168
-Rres@3 net@8 net@11 38.337
-.ENDS wire-C_0_011f-3317_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3317_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3317_6-R_34_667m
-.ENDS wire90-3317_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1688_5-R_34_667m a b
-Ccap@0 gnd net@14 6.191f
-Ccap@1 gnd net@8 6.191f
-Ccap@2 gnd net@11 6.191f
-Rres@0 net@14 a 9.756
-Rres@1 net@11 net@14 19.512
-Rres@2 b net@8 9.756
-Rres@3 net@8 net@11 19.512
-.ENDS wire-C_0_011f-1688_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1688_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1688_5-R_34_667m
-.ENDS wire90-1688_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1392_5-R_34_667m a b
-Ccap@0 gnd net@14 5.106f
-Ccap@1 gnd net@8 5.106f
-Ccap@2 gnd net@11 5.106f
-Rres@0 net@14 a 8.046
-Rres@1 net@11 net@14 16.091
-Rres@2 b net@8 8.046
-Rres@3 net@8 net@11 16.091
-.ENDS wire-C_0_011f-1392_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1392_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1392_5-R_34_667m
-.ENDS wire90-1392_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1411-R_34_667m a b
-Ccap@0 gnd net@14 5.174f
-Ccap@1 gnd net@8 5.174f
-Ccap@2 gnd net@11 5.174f
-Rres@0 net@14 a 8.152
-Rres@1 net@11 net@14 16.305
-Rres@2 b net@8 8.152
-Rres@3 net@8 net@11 16.305
-.ENDS wire-C_0_011f-1411-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1411-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1411-R_34_667m
-.ENDS wire90-1411-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1679_5-R_34_667m a b
-Ccap@0 gnd net@14 6.158f
-Ccap@1 gnd net@8 6.158f
-Ccap@2 gnd net@11 6.158f
-Rres@0 net@14 a 9.704
-Rres@1 net@11 net@14 19.408
-Rres@2 b net@8 9.704
-Rres@3 net@8 net@11 19.408
-.ENDS wire-C_0_011f-1679_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1679_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1679_5-R_34_667m
-.ENDS wire90-1679_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1929_7-R_34_667m a b
-Ccap@0 gnd net@14 7.076f
-Ccap@1 gnd net@8 7.076f
-Ccap@2 gnd net@11 7.076f
-Rres@0 net@14 a 11.149
-Rres@1 net@11 net@14 22.299
-Rres@2 b net@8 11.149
-Rres@3 net@8 net@11 22.299
-.ENDS wire-C_0_011f-1929_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1929_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1929_7-R_34_667m
-.ENDS wire90-1929_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1631_6-R_34_667m a b
-Ccap@0 gnd net@14 5.983f
-Ccap@1 gnd net@8 5.983f
-Ccap@2 gnd net@11 5.983f
-Rres@0 net@14 a 9.427
-Rres@1 net@11 net@14 18.854
-Rres@2 b net@8 9.427
-Rres@3 net@8 net@11 18.854
-.ENDS wire-C_0_011f-1631_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1631_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1631_6-R_34_667m
-.ENDS wire90-1631_6-layer_1-width_3
-
-*** CELL: loopCountM:olcWcont{sch}
-.SUBCKT olcWcont do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load]
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sel[Co] sel[Ld]
-+sel[rD] sin sout
-XloadORco@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] mc olc[dec]
-+olc[load] olc[zero] olc[zoo] s[1] s[2] sel[Co] sel[Ld] sel[rD] loadORcount
-Xolc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
-+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc
-XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@81 sout scanEx2h
-XscanEx3h@1 bitt[1] bitt[3] bitt[5] mc p1p p2p rd sin net@46 scanEx3h
-XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@81 scanEx3h
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xwire90@1 olc[zero] wire90@1_b wire90-849_4-layer_1-width_3
-Xwire90@2 olc[zoo] wire90@2_b wire90-868_7-layer_1-width_3
-Xwire90@3 olc[load] wire90@3_b wire90-3939_8-layer_1-width_3
-Xwire90@4 olc[dec] wire90@4_b wire90-3317_6-layer_1-width_3
-Xwire90@5 wire90@5_a bitt[4] wire90-1688_5-layer_1-width_3
-Xwire90@6 wire90@6_a bitt[5] wire90-1392_5-layer_1-width_3
-Xwire90@7 wire90@7_a bitt[6] wire90-1411-layer_1-width_3
-Xwire90@8 wire90@8_a bitt[1] wire90-1679_5-layer_1-width_3
-Xwire90@9 wire90@9_a bitt[2] wire90-1929_7-layer_1-width_3
-Xwire90@10 wire90@10_a bitt[3] wire90-1631_6-layer_1-width_3
-.ENDS olcWcont
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3585-R_34_667m a b
-Ccap@0 gnd net@14 13.145f
-Ccap@1 gnd net@8 13.145f
-Ccap@2 gnd net@11 13.145f
-Rres@0 net@14 a 20.713
-Rres@1 net@11 net@14 41.427
-Rres@2 b net@8 20.713
-Rres@3 net@8 net@11 41.427
-.ENDS wire-C_0_011f-3585-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3585-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3585-R_34_667m
-.ENDS wire90-3585-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3431-R_34_667m a b
-Ccap@0 gnd net@14 12.58f
-Ccap@1 gnd net@8 12.58f
-Ccap@2 gnd net@11 12.58f
-Rres@0 net@14 a 19.824
-Rres@1 net@11 net@14 39.647
-Rres@2 b net@8 19.824
-Rres@3 net@8 net@11 39.647
-.ENDS wire-C_0_011f-3431-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3431-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3431-R_34_667m
-.ENDS wire90-3431-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3643_1-R_34_667m a b
-Ccap@0 gnd net@14 13.358f
-Ccap@1 gnd net@8 13.358f
-Ccap@2 gnd net@11 13.358f
-Rres@0 net@14 a 21.049
-Rres@1 net@11 net@14 42.098
-Rres@2 b net@8 21.049
-Rres@3 net@8 net@11 42.098
-.ENDS wire-C_0_011f-3643_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3643_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3643_1-R_34_667m
-.ENDS wire90-3643_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3498_9-R_34_667m a b
-Ccap@0 gnd net@14 12.829f
-Ccap@1 gnd net@8 12.829f
-Ccap@2 gnd net@11 12.829f
-Rres@0 net@14 a 20.216
-Rres@1 net@11 net@14 40.432
-Rres@2 b net@8 20.216
-Rres@3 net@8 net@11 40.432
-.ENDS wire-C_0_011f-3498_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3498_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3498_9-R_34_667m
-.ENDS wire90-3498_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2425-R_34_667m a b
-Ccap@0 gnd net@14 8.892f
-Ccap@1 gnd net@8 8.892f
-Ccap@2 gnd net@11 8.892f
-Rres@0 net@14 a 14.011
-Rres@1 net@11 net@14 28.022
-Rres@2 b net@8 14.011
-Rres@3 net@8 net@11 28.022
-.ENDS wire-C_0_011f-2425-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2425-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2425-R_34_667m
-.ENDS wire90-2425-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1981_8-R_34_667m a b
-Ccap@0 gnd net@14 7.267f
-Ccap@1 gnd net@8 7.267f
-Ccap@2 gnd net@11 7.267f
-Rres@0 net@14 a 11.45
-Rres@1 net@11 net@14 22.901
-Rres@2 b net@8 11.45
-Rres@3 net@8 net@11 22.901
-.ENDS wire-C_0_011f-1981_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1981_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1981_8-R_34_667m
-.ENDS wire90-1981_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5586_2-R_34_667m a b
-Ccap@0 gnd net@14 20.483f
-Ccap@1 gnd net@8 20.483f
-Ccap@2 gnd net@11 20.483f
-Rres@0 net@14 a 32.276
-Rres@1 net@11 net@14 64.552
-Rres@2 b net@8 32.276
-Rres@3 net@8 net@11 64.552
-.ENDS wire-C_0_011f-5586_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5586_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5586_2-R_34_667m
-.ENDS wire90-5586_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2119_6-R_34_667m a b
-Ccap@0 gnd net@14 7.772f
-Ccap@1 gnd net@8 7.772f
-Ccap@2 gnd net@11 7.772f
-Rres@0 net@14 a 12.247
-Rres@1 net@11 net@14 24.493
-Rres@2 b net@8 12.247
-Rres@3 net@8 net@11 24.493
-.ENDS wire-C_0_011f-2119_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2119_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2119_6-R_34_667m
-.ENDS wire90-2119_6-layer_1-width_3
-
-*** CELL: stagesM:outDockCenter{sch}
-.SUBCKT outDockCenter do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set]
-+flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12]
-+m1[1] m1[21] m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9]
-+m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
-+m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T]
-+pred[D] pred[T] ps[18] ps[19] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25]
-+ps[26] ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1] succ[sf]
-XbitAssig@0 bitAssignments
-Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
-+m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9]
-+sir[9] sir[3] sir[2] sir[5] sir[1] net@279 flags
-XilcMoveO@0 do[ins] net@293 epi[torp] fire[M] flag[D][set] ilc[load] inLO[1]
-+inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] sir[9] sir[3] sir[2] pred[D]
-+pred[T] sir[5] ps[18] ps[25] ps[19] ps[26] net@249 sor[1] succ[sf] ilcMoveOut
-XmuxForD@0 in[1] in[2] in[3] in[4] in[5] in[6] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] ps[20] muxForD
-XohPredAl@0 do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] m1[22] m1[21] m1cate[1][F] m1cate[1][T]
-+m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T]
-+m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2]
-+ps[22] ps[do] ps[skip] sir[5] net@244 net@249 ohPredAll
-XolcWcont@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] net@165 inLO[1]
-+inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] ps[24]
-+ps[23] ps[21] net@279 net@244 olcWcont
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-Xtc[10] tranCap
-Xtc[11] tranCap
-Xtc[12] tranCap
-Xtc[13] tranCap
-Xtc[14] tranCap
-Xtc[15] tranCap
-Xtc[16] tranCap
-Xwire90@5 wire90@5_a flag[A][set] wire90-3585-layer_1-width_3
-Xwire90@6 wire90@6_a flag[A][clr] wire90-3431-layer_1-width_3
-Xwire90@7 wire90@7_a flag[B][set] wire90-3643_1-layer_1-width_3
-Xwire90@8 wire90@8_a flag[B][clr] wire90-3498_9-layer_1-width_3
-Xwire90@9 wire90@9_a flag[D][set] wire90-2425-layer_1-width_3
-Xwire90@10 wire90@10_a flag[D][clr] wire90-1981_8-layer_1-width_3
-Xwire90@24 net@165 ilc[load] wire90-5586_2-layer_1-width_3
-Xwire90@25 net@293 doneLO[M] wire90-2119_6-layer_1-width_3
-.ENDS outDockCenter
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5140_2-R_34_667m a b
-Ccap@0 gnd net@14 18.847f
-Ccap@1 gnd net@8 18.847f
-Ccap@2 gnd net@11 18.847f
-Rres@0 net@14 a 29.699
-Rres@1 net@11 net@14 59.398
-Rres@2 b net@8 29.699
-Rres@3 net@8 net@11 59.398
-.ENDS wire-C_0_011f-5140_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5140_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5140_2-R_34_667m
-.ENDS wire90-5140_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5074_2-R_34_667m a b
-Ccap@0 gnd net@14 18.605f
-Ccap@1 gnd net@8 18.605f
-Ccap@2 gnd net@11 18.605f
-Rres@0 net@14 a 29.318
-Rres@1 net@11 net@14 58.635
-Rres@2 b net@8 29.318
-Rres@3 net@8 net@11 58.635
-.ENDS wire-C_0_011f-5074_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5074_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5074_2-R_34_667m
-.ENDS wire90-5074_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4771_5-R_34_667m a b
-Ccap@0 gnd net@14 17.496f
-Ccap@1 gnd net@8 17.496f
-Ccap@2 gnd net@11 17.496f
-Rres@0 net@14 a 27.569
-Rres@1 net@11 net@14 55.137
-Rres@2 b net@8 27.569
-Rres@3 net@8 net@11 55.137
-.ENDS wire-C_0_011f-4771_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4771_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4771_5-R_34_667m
-.ENDS wire90-4771_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4754_4-R_34_667m a b
-Ccap@0 gnd net@14 17.433f
-Ccap@1 gnd net@8 17.433f
-Ccap@2 gnd net@11 17.433f
-Rres@0 net@14 a 27.47
-Rres@1 net@11 net@14 54.94
-Rres@2 b net@8 27.47
-Rres@3 net@8 net@11 54.94
-.ENDS wire-C_0_011f-4754_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4754_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4754_4-R_34_667m
-.ENDS wire90-4754_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4487_8-R_34_667m a b
-Ccap@0 gnd net@14 16.455f
-Ccap@1 gnd net@8 16.455f
-Ccap@2 gnd net@11 16.455f
-Rres@0 net@14 a 25.93
-Rres@1 net@11 net@14 51.859
-Rres@2 b net@8 25.93
-Rres@3 net@8 net@11 51.859
-.ENDS wire-C_0_011f-4487_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4487_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4487_8-R_34_667m
-.ENDS wire90-4487_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4482_1-R_34_667m a b
-Ccap@0 gnd net@14 16.434f
-Ccap@1 gnd net@8 16.434f
-Ccap@2 gnd net@11 16.434f
-Rres@0 net@14 a 25.897
-Rres@1 net@11 net@14 51.793
-Rres@2 b net@8 25.897
-Rres@3 net@8 net@11 51.793
-.ENDS wire-C_0_011f-4482_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4482_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4482_1-R_34_667m
-.ENDS wire90-4482_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3199-R_34_667m a b
-Ccap@0 gnd net@14 11.73f
-Ccap@1 gnd net@8 11.73f
-Ccap@2 gnd net@11 11.73f
-Rres@0 net@14 a 18.483
-Rres@1 net@11 net@14 36.966
-Rres@2 b net@8 18.483
-Rres@3 net@8 net@11 36.966
-.ENDS wire-C_0_011f-3199-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3199-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3199-R_34_667m
-.ENDS wire90-3199-layer_1-width_3
-
-*** CELL: stagesM:outDockPredStage{sch}
-.SUBCKT outDockPredStage do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set]
-+flag[C][T] flag[D][clr] flag[D][set] in[1] in[2] in[3] in[4] in[5] in[6]
-+m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1]
-+m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[2] m1[3] m1[4]
-+m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12]
-+ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2]
-+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[sf]
-XdockPSre@0 do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25]
-+ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSreg
-XoutDockC@0 do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set] flag[C][T]
-+flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
-+inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[21]
-+m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D]
-+pred[T] ps[18] ps[19] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[do]
-+ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+sor[1] succ[sf] outDockCenter
-Xwire90@1 wire90@1_a inLO[1] wire90-5140_2-layer_1-width_3
-Xwire90@2 wire90@2_a inLO[2] wire90-5074_2-layer_1-width_3
-Xwire90@3 wire90@3_a inLO[3] wire90-4771_5-layer_1-width_3
-Xwire90@4 wire90@4_a inLO[4] wire90-4754_4-layer_1-width_3
-Xwire90@5 wire90@5_a inLO[5] wire90-4487_8-layer_1-width_3
-Xwire90@6 wire90@6_a inLO[6] wire90-4482_1-layer_1-width_3
-Xwire90@7 wire90@7_a inLO[8] wire90-3199-layer_1-width_3
-.ENDS outDockPredStage
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3095_7-R_34_667m a b
-Ccap@0 gnd net@14 11.351f
-Ccap@1 gnd net@8 11.351f
-Ccap@2 gnd net@11 11.351f
-Rres@0 net@14 a 17.886
-Rres@1 net@11 net@14 35.773
-Rres@2 b net@8 17.886
-Rres@3 net@8 net@11 35.773
-.ENDS wire-C_0_011f-3095_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3095_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3095_7-R_34_667m
-.ENDS wire90-3095_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3453_4-R_34_667m a b
-Ccap@0 gnd net@14 12.662f
-Ccap@1 gnd net@8 12.662f
-Ccap@2 gnd net@11 12.662f
-Rres@0 net@14 a 19.953
-Rres@1 net@11 net@14 39.906
-Rres@2 b net@8 19.953
-Rres@3 net@8 net@11 39.906
-.ENDS wire-C_0_011f-3453_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3453_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3453_4-R_34_667m
-.ENDS wire90-3453_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-6559_5-R_34_667m a b
-Ccap@0 gnd net@14 24.052f
-Ccap@1 gnd net@8 24.052f
-Ccap@2 gnd net@11 24.052f
-Rres@0 net@14 a 37.899
-Rres@1 net@11 net@14 75.799
-Rres@2 b net@8 37.899
-Rres@3 net@8 net@11 75.799
-.ENDS wire-C_0_011f-6559_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-6559_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-6559_5-R_34_667m
-.ENDS wire90-6559_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1466_1-R_34_667m a b
-Ccap@0 gnd net@14 5.376f
-Ccap@1 gnd net@8 5.376f
-Ccap@2 gnd net@11 5.376f
-Rres@0 net@14 a 8.471
-Rres@1 net@11 net@14 16.942
-Rres@2 b net@8 8.471
-Rres@3 net@8 net@11 16.942
-.ENDS wire-C_0_011f-1466_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1466_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1466_1-R_34_667m
-.ENDS wire90-1466_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1632_5-R_34_667m a b
-Ccap@0 gnd net@14 5.986f
-Ccap@1 gnd net@8 5.986f
-Ccap@2 gnd net@11 5.986f
-Rres@0 net@14 a 9.432
-Rres@1 net@11 net@14 18.864
-Rres@2 b net@8 9.432
-Rres@3 net@8 net@11 18.864
-.ENDS wire-C_0_011f-1632_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1632_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1632_5-R_34_667m
-.ENDS wire90-1632_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1066_4-R_34_667m a b
-Ccap@0 gnd net@14 3.91f
-Ccap@1 gnd net@8 3.91f
-Ccap@2 gnd net@11 3.91f
-Rres@0 net@14 a 6.161
-Rres@1 net@11 net@14 12.323
-Rres@2 b net@8 6.161
-Rres@3 net@8 net@11 12.323
-.ENDS wire-C_0_011f-1066_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1066_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1066_4-R_34_667m
-.ENDS wire90-1066_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1232_5-R_34_667m a b
-Ccap@0 gnd net@14 4.519f
-Ccap@1 gnd net@8 4.519f
-Ccap@2 gnd net@11 4.519f
-Rres@0 net@14 a 7.121
-Rres@1 net@11 net@14 14.242
-Rres@2 b net@8 7.121
-Rres@3 net@8 net@11 14.242
-.ENDS wire-C_0_011f-1232_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1232_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1232_5-R_34_667m
-.ENDS wire90-1232_5-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1106_7-R_34_667m a b
-Ccap@0 gnd net@14 4.058f
-Ccap@1 gnd net@8 4.058f
-Ccap@2 gnd net@11 4.058f
-Rres@0 net@14 a 6.394
-Rres@1 net@11 net@14 12.789
-Rres@2 b net@8 6.394
-Rres@3 net@8 net@11 12.789
-.ENDS wire-C_0_011f-1106_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1106_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1106_7-R_34_667m
-.ENDS wire90-1106_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1242_8-R_34_667m a b
-Ccap@0 gnd net@14 4.557f
-Ccap@1 gnd net@8 4.557f
-Ccap@2 gnd net@11 4.557f
-Rres@0 net@14 a 7.181
-Rres@1 net@11 net@14 14.361
-Rres@2 b net@8 7.181
-Rres@3 net@8 net@11 14.361
-.ENDS wire-C_0_011f-1242_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1242_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1242_8-R_34_667m
-.ENDS wire90-1242_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1260_9-R_34_667m a b
-Ccap@0 gnd net@14 4.623f
-Ccap@1 gnd net@8 4.623f
-Ccap@2 gnd net@11 4.623f
-Rres@0 net@14 a 7.285
-Rres@1 net@11 net@14 14.57
-Rres@2 b net@8 7.285
-Rres@3 net@8 net@11 14.57
-.ENDS wire-C_0_011f-1260_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1260_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1260_9-R_34_667m
-.ENDS wire90-1260_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1327_2-R_34_667m a b
-Ccap@0 gnd net@14 4.866f
-Ccap@1 gnd net@8 4.866f
-Ccap@2 gnd net@11 4.866f
-Rres@0 net@14 a 7.668
-Rres@1 net@11 net@14 15.337
-Rres@2 b net@8 7.668
-Rres@3 net@8 net@11 15.337
-.ENDS wire-C_0_011f-1327_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1327_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1327_2-R_34_667m
-.ENDS wire90-1327_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1283_7-R_34_667m a b
-Ccap@0 gnd net@14 4.707f
-Ccap@1 gnd net@8 4.707f
-Ccap@2 gnd net@11 4.707f
-Rres@0 net@14 a 7.417
-Rres@1 net@11 net@14 14.834
-Rres@2 b net@8 7.417
-Rres@3 net@8 net@11 14.834
-.ENDS wire-C_0_011f-1283_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1283_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1283_7-R_34_667m
-.ENDS wire90-1283_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1456_1-R_34_667m a b
-Ccap@0 gnd net@14 5.339f
-Ccap@1 gnd net@8 5.339f
-Ccap@2 gnd net@11 5.339f
-Rres@0 net@14 a 8.413
-Rres@1 net@11 net@14 16.826
-Rres@2 b net@8 8.413
-Rres@3 net@8 net@11 16.826
-.ENDS wire-C_0_011f-1456_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1456_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1456_1-R_34_667m
-.ENDS wire90-1456_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1427_2-R_34_667m a b
-Ccap@0 gnd net@14 5.233f
-Ccap@1 gnd net@8 5.233f
-Ccap@2 gnd net@11 5.233f
-Rres@0 net@14 a 8.246
-Rres@1 net@11 net@14 16.492
-Rres@2 b net@8 8.246
-Rres@3 net@8 net@11 16.492
-.ENDS wire-C_0_011f-1427_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1427_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1427_2-R_34_667m
-.ENDS wire90-1427_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1544_9-R_34_667m a b
-Ccap@0 gnd net@14 5.665f
-Ccap@1 gnd net@8 5.665f
-Ccap@2 gnd net@11 5.665f
-Rres@0 net@14 a 8.926
-Rres@1 net@11 net@14 17.852
-Rres@2 b net@8 8.926
-Rres@3 net@8 net@11 17.852
-.ENDS wire-C_0_011f-1544_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1544_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1544_9-R_34_667m
-.ENDS wire90-1544_9-layer_1-width_3
-
-*** CELL: stageGroupsM:outM1PredLit{sch}
-.SUBCKT outM1PredLit dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
-+dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
-+dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37]
-+dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] dsA[12]
-+dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8]
-+dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16]
-+dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
-+dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
-+dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
-+dsD[8] dsD[9] epi[torp] flag[A][clr] flag[A][set] flag[D][clr] flag[D][set]
-+m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1]
-+m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2]
-+m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6]
-+m1[7] m1[8] m1[9] pred[D] pred[R] pred[T] ps[do] ps[skip] ring[10] ring[11]
-+ring[12] ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19]
-+ring[1] ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26]
-+ring[27] ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33]
-+ring[34] ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8]
-+ring[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] succ[m1]
-XlitDandP@0 net@89 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
-+dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
-+dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37]
-+dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] dsA[12]
-+dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8]
-+dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16]
-+dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
-+dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
-+dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
-+dsD[8] dsD[9] net@90 flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7]
-+ps[8] ps[9] signalBitFromInboundSwitchFabric succ[D] succ[T] litDandP
-XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
-+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
-+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
-+m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[R] ring[10] ring[11] ring[12]
-+ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1]
-+ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27]
-+ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34]
-+ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@47[8]
-+succ[m1] take[m1] mOneDockStage
-XoutDockP@0 do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set] net@82
-+flag[D][clr] flag[D][set] dsD[1] dsD[2] dsD[3] dsD[4] dsD[5] dsD[6] m1[10]
-+m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20]
-+m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[2] m1[3] m1[4] m1[5]
-+m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
-+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
-+m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14]
-+ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4]
-+ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4]
-+sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] outDockPredStage
-Xwire90@0 flag[C] net@82 wire90-3095_7-layer_1-width_3
-Xwire90@1 net@90 fire[M] wire90-3453_4-layer_1-width_3
-Xwire90@2 net@89 do[ins] wire90-6559_5-layer_1-width_3
-Xwire90@3 wire90@3_a m1cate[1][T] wire90-1466_1-layer_1-width_3
-Xwire90@4 wire90@4_a m1cate[1][F] wire90-1632_5-layer_1-width_3
-Xwire90@5 wire90@5_a m1cate[2][T] wire90-1066_4-layer_1-width_3
-Xwire90@6 wire90@6_a m1cate[2][F] wire90-1232_5-layer_1-width_3
-Xwire90@7 wire90@7_a m1cate[3][T] wire90-1106_7-layer_1-width_3
-Xwire90@8 wire90@8_a m1cate[3][F] wire90-1242_8-layer_1-width_3
-Xwire90@9 wire90@9_a m1cate[4][T] wire90-1260_9-layer_1-width_3
-Xwire90@10 wire90@10_a m1cate[4][F] wire90-1327_2-layer_1-width_3
-Xwire90@11 wire90@11_a m1cate[5][T] wire90-1283_7-layer_1-width_3
-Xwire90@12 wire90@12_a m1cate[5][F] wire90-1456_1-layer_1-width_3
-Xwire90@13 wire90@13_a m1cate[6][T] wire90-1427_2-layer_1-width_3
-Xwire90@14 wire90@14_a m1cate[6][F] wire90-1544_9-layer_1-width_3
-.ENDS outM1PredLit
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1923_7-R_34_667m a b
-Ccap@0 gnd net@14 7.054f
-Ccap@1 gnd net@8 7.054f
-Ccap@2 gnd net@11 7.054f
-Rres@0 net@14 a 11.115
-Rres@1 net@11 net@14 22.229
-Rres@2 b net@8 11.115
-Rres@3 net@8 net@11 22.229
-.ENDS wire-C_0_011f-1923_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1923_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1923_7-R_34_667m
-.ENDS wire90-1923_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3844_8-R_34_667m a b
-Ccap@0 gnd net@14 14.098f
-Ccap@1 gnd net@8 14.098f
-Ccap@2 gnd net@11 14.098f
-Rres@0 net@14 a 22.214
-Rres@1 net@11 net@14 44.429
-Rres@2 b net@8 22.214
-Rres@3 net@8 net@11 44.429
-.ENDS wire-C_0_011f-3844_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3844_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3844_8-R_34_667m
-.ENDS wire90-3844_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-909_6-R_34_667m a b
-Ccap@0 gnd net@14 3.335f
-Ccap@1 gnd net@8 3.335f
-Ccap@2 gnd net@11 3.335f
-Rres@0 net@14 a 5.255
-Rres@1 net@11 net@14 10.511
-Rres@2 b net@8 5.255
-Rres@3 net@8 net@11 10.511
-.ENDS wire-C_0_011f-909_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-909_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-909_6-R_34_667m
-.ENDS wire90-909_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2011_2-R_34_667m a b
-Ccap@0 gnd net@14 7.374f
-Ccap@1 gnd net@8 7.374f
-Ccap@2 gnd net@11 7.374f
-Rres@0 net@14 a 11.62
-Rres@1 net@11 net@14 23.241
-Rres@2 b net@8 11.62
-Rres@3 net@8 net@11 23.241
-.ENDS wire-C_0_011f-2011_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2011_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2011_2-R_34_667m
-.ENDS wire90-2011_2-layer_1-width_3
-
-*** CELL: dockM:outputDock{sch}
-.SUBCKT outputDock do[epi] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16]
-+dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26]
-+dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36]
-+dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11]
-+dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7]
-+dsA[8] dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16]
-+dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
-+dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
-+dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
-+dsD[8] dsD[9] fout in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] in[T] pred[D] pred[T]
-+signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ[D] succ[T]
-XdockWagN@0 net@26[26] net@26[25] net@26[24] net@26[23] net@26[22] net@26[21]
-+net@26[20] net@26[19] net@26[18] net@26[17] net@26[35] net@26[16] net@26[15]
-+net@26[14] net@26[13] net@26[12] net@26[11] net@26[10] net@26[9] net@26[8]
-+net@26[7] net@26[34] net@26[6] net@26[5] net@26[4] net@26[3] net@26[2]
-+net@26[1] net@26[0] net@26[33] net@26[32] net@26[31] net@26[30] net@26[29]
-+net@26[28] net@26[27] net@57[26] net@57[25] net@57[24] net@57[23] net@57[22]
-+net@57[21] net@57[20] net@57[19] net@57[18] net@57[17] net@57[35] net@57[16]
-+net@57[15] net@57[14] net@57[13] net@57[12] net@57[11] net@57[10] net@57[9]
-+net@57[8] net@57[7] net@57[34] net@57[6] net@57[5] net@57[4] net@57[3]
-+net@57[2] net@57[1] net@57[0] net@57[33] net@57[32] net@57[31] net@57[30]
-+net@57[29] net@57[28] net@57[27] net@15 net@75[8] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] net@76[8] net@85 fout dockWagNine
-XepiRQod@1 do[epi] net@89 net@82 flag[A][clr] flag[A][set] flag[D][clr]
-+flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
-+in[5] in[6] in[7] in[8] in[9] in[T] net@68[26] net@68[25] net@68[24]
-+net@68[23] net@68[22] net@68[21] net@68[20] net@68[19] net@68[18] net@68[17]
-+net@68[35] net@68[16] net@68[15] net@68[14] net@68[13] net@68[12] net@68[11]
-+net@68[10] net@68[9] net@68[8] net@68[7] net@68[34] net@68[6] net@68[5]
-+net@68[4] net@68[3] net@68[2] net@68[1] net@68[0] net@68[33] net@68[32]
-+net@68[31] net@68[30] net@68[29] net@68[28] net@68[27] ps[do] ps[skip]
-+net@26[26] net@26[25] net@26[24] net@26[23] net@26[22] net@26[21] net@26[20]
-+net@26[19] net@26[18] net@26[17] net@26[35] net@26[16] net@26[15] net@26[14]
-+net@26[13] net@26[12] net@26[11] net@26[10] net@26[9] net@26[8] net@26[7]
-+net@26[34] net@26[6] net@26[5] net@26[4] net@26[3] net@26[2] net@26[1]
-+net@26[0] net@26[33] net@26[32] net@26[31] net@26[30] net@26[29] net@26[28]
-+net@26[27] net@90 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@75[8] epiRQod
-XoutM1Pre@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
-+dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
-+dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
-+dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] dsA[12] dsA[13]
-+dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9]
-+dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] dsD[17]
-+dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25]
-+dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33]
-+dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8]
-+dsD[9] torp flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] net@68[26]
-+net@68[25] net@68[24] net@68[23] net@68[22] net@68[21] net@68[20] net@68[19]
-+net@68[18] net@68[17] net@68[35] net@68[16] net@68[15] net@68[14] net@68[13]
-+net@68[12] net@68[11] net@68[10] net@68[9] net@68[8] net@68[7] net@68[34]
-+net@68[6] net@68[5] net@68[4] net@68[3] net@68[2] net@68[1] net@68[0]
-+net@68[33] net@68[32] net@68[31] net@68[30] net@68[29] net@68[28] net@68[27]
-+pred[D] net@84 pred[T] ps[do] ps[skip] net@57[26] net@57[25] net@57[24]
-+net@57[23] net@57[22] net@57[21] net@57[20] net@57[19] net@57[18] net@57[17]
-+net@57[35] net@57[16] net@57[15] net@57[14] net@57[13] net@57[12] net@57[11]
-+net@57[10] net@57[9] net@57[8] net@57[7] net@57[34] net@57[6] net@57[5]
-+net@57[4] net@57[3] net@57[2] net@57[1] net@57[0] net@57[33] net@57[32]
-+net@57[31] net@57[30] net@57[29] net@57[28] net@57[27]
-+signalBitFromInboundSwitchFabric net@76[8] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] net@88 outM1PredLit
-Xwire90@1 net@84 net@85 wire90-1923_7-layer_1-width_3
-Xwire90@2 torp net@82 wire90-3844_8-layer_1-width_3
-Xwire90@3 net@89 net@88 wire90-909_6-layer_1-width_3
-Xwire90@4 net@15 net@90 wire90-2011_2-layer_1-width_3
-.ENDS outputDock
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-476_7-R_34_667m a b
-Ccap@0 gnd net@14 1.748f
-Ccap@1 gnd net@8 1.748f
-Ccap@2 gnd net@11 1.748f
-Rres@0 net@14 a 2.754
-Rres@1 net@11 net@14 5.509
-Rres@2 b net@8 2.754
-Rres@3 net@8 net@11 5.509
-.ENDS wire-C_0_011f-476_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-476_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-476_7-R_34_667m
-.ENDS wire90-476_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-472_4-R_34_667m a b
-Ccap@0 gnd net@14 1.732f
-Ccap@1 gnd net@8 1.732f
-Ccap@2 gnd net@11 1.732f
-Rres@0 net@14 a 2.729
-Rres@1 net@11 net@14 5.459
-Rres@2 b net@8 2.729
-Rres@3 net@8 net@11 5.459
-.ENDS wire-C_0_011f-472_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-472_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-472_4-R_34_667m
-.ENDS wire90-472_4-layer_1-width_3
-
-*** CELL: centersJ:ctrAND3in100LT{sch}
-.SUBCKT ctrAND3in100LT inA inB inC out
-Xinv@3 net@104 out inv-X_100
-Xinv@4 inC net@143 inv-X_10
-Xnand2LT_@0 net@138 net@131 net@134 nand2LT_sy-X_30
-Xnor2n_sy@0 inA inB net@130 nor2n_sy-X_10
-Xwire90@0 net@130 net@131 wire90-476_7-layer_1-width_3
-Xwire90@4 net@134 net@104 wire90-1013_8-layer_1-width_3
-Xwire90@5 net@143 net@138 wire90-472_4-layer_1-width_3
-.ENDS ctrAND3in100LT
-
-*** CELL: gaspM:gaspTap{sch}
-.SUBCKT gaspTap fire mc pred s[1] succ[A] succ[B] take to[A] to[B] tok
-XctrAND3i@0 succ[A] succ[B] net@163 fire ctrAND3in100LT
-XdataDriv@0 tok fire take dataDriver60
-Xinv@0 pred net@240 inv-X_10
-XinvI@0 net@240 s[1] inv-X_10
-XpredDri6@1 fire mc pred predDri60wMC
-XsucANDdr@2 to[A] fire succ[A] sucANDdri60
-XsucANDdr@3 to[B] fire succ[B] sucANDdri60
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xwire90@0 net@240 net@163 wire90-602_3-layer_1-width_3
-.ENDS gaspTap
-
-*** CELL: scanM:scanFx2{sch}
-.SUBCKT scanFx2 dout[1] dout[2] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6]
-+sic[7] sic[8] sic[9] soc[1]
-XscanCell@3 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4]
-+scanCellF
-XscanCell@4 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 soc[1] sic[4]
-+scanCellF
-Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3
-.ENDS scanFx2
-
-*** CELL: stagesM:tapStage{sch}
-.SUBCKT tapStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12]
-+out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29]
-+out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2] sic[3] sic[4]
-+sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] soc[1] sor[1] succ[A] succ[B]
-Xaddr1in6@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@0 addr1in60Cx15
-Xdata1in6@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] net@3 data1in60Cx37
-XgaspTap@0 net@0 sir[9] pred net@54 succ[A] succ[B] net@3 to[A] to[B] ain[TT]
-+gaspTap
-XscanEx1@0 net@54 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1
-XscanFx2@0 to[A] to[B] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] soc[1] scanFx2
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-.ENDS tapStage
-
-*** CELL: stageGroupsM:tapPropStop{sch}
-.SUBCKT tapPropStop ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] cin fin fout in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
-+sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ[A] succ[B]
-Xinstruct@0 cin net@91 fin fout net@105[8] sod[2] sod[3] sod[4] sod[5] sid[6]
-+sid[7] sid[8] sid[9] sod[1] instructionCount
-XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@107[41] net@107[40]
-+net@107[39] net@107[38] net@107[37] net@107[50] net@107[49] net@107[48]
-+net@107[47] net@107[46] net@107[45] net@107[44] net@107[43] net@107[42]
-+net@107[51] net@91 properSt@1_fire in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
-+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@107[27]
-+net@107[26] net@107[25] net@107[24] net@107[23] net@107[22] net@107[21]
-+net@107[20] net@107[19] net@107[18] net@107[36] net@107[17] net@107[16]
-+net@107[15] net@107[14] net@107[13] net@107[12] net@107[11] net@107[10]
-+net@107[9] net@107[8] net@107[35] net@107[7] net@107[6] net@107[5] net@107[4]
-+net@107[3] net@107[2] net@107[1] net@107[0] net@107[34] net@107[33]
-+net@107[32] net@107[31] net@107[30] net@107[29] net@107[28] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] net@100[8] soc[2] soc[3] soc[4] soc[5] net@105[8]
-+sod[2] sod[3] sod[4] sod[5] net@101[8] sor[2] sor[3] sor[4] sor[5] net@98
-+properStopper
-XtapStage@2 net@107[41] net@107[40] net@107[39] net@107[38] net@107[37]
-+net@107[50] net@107[49] net@107[48] net@107[47] net@107[46] net@107[45]
-+net@107[44] net@107[43] net@107[42] net@107[51] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@107[27] net@107[26] net@107[25] net@107[24]
-+net@107[23] net@107[22] net@107[21] net@107[20] net@107[19] net@107[18]
-+net@107[36] net@107[17] net@107[16] net@107[15] net@107[14] net@107[13]
-+net@107[12] net@107[11] net@107[10] net@107[9] net@107[8] net@107[35]
-+net@107[7] net@107[6] net@107[5] net@107[4] net@107[3] net@107[2] net@107[1]
-+net@107[0] net@107[34] net@107[33] net@107[32] net@107[31] net@107[30]
-+net@107[29] net@107[28] out[10] out[11] out[12] out[13] out[14] out[15]
-+out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23]
-+out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31]
-+out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] net@85 net@100[8] soc[2] soc[3] soc[4] soc[5] sic[6]
-+sic[7] sic[8] sic[9] net@101[8] sor[2] sor[3] sor[4] sor[5] sir[6] sir[7]
-+sir[8] sir[9] soc[1] sor[1] succ[A] succ[B] tapStage
-Xwire90@2 net@98 net@85 wire90-2080_4-layer_1-width_3
-.ENDS tapPropStop
-
-*** CELL: stageGroupsM:southFifo{sch}
-.SUBCKT southFifo aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] cin
-+fin fout out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8]
-+out[9] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1]
-+sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3]
-+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5]
-+sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5]
-+succ[tap]
-XtapPropS@1 net@79[41] net@79[40] net@79[39] net@79[38] net@79[37] net@79[50]
-+net@79[49] net@79[48] net@79[47] net@79[46] net@79[45] net@79[44] net@79[43]
-+net@79[42] net@79[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] cin
-+fin fout net@79[27] net@79[26] net@79[25] net@79[24] net@79[23] net@79[22]
-+net@79[21] net@79[20] net@79[19] net@79[18] net@79[36] net@79[17] net@79[16]
-+net@79[15] net@79[14] net@79[13] net@79[12] net@79[11] net@79[10] net@79[9]
-+net@79[8] net@79[35] net@79[7] net@79[6] net@79[5] net@79[4] net@79[3]
-+net@79[2] net@79[1] net@79[0] net@79[34] net@79[33] net@79[32] net@79[31]
-+net@79[30] net@79[29] net@79[28] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] net@61 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6]
-+sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8]
-+sid[9] net@64[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+sor[2] sor[3] sor[4] sor[5] net@53 succ[tap] tapPropStop
-XupDown8w@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] net@77[41]
-+net@77[40] net@77[39] net@77[38] net@77[37] net@77[50] net@77[49] net@77[48]
-+net@77[47] net@77[46] net@77[45] net@77[44] net@77[43] net@77[42] net@77[51]
-+net@77[41] net@77[40] net@77[39] net@77[38] net@77[37] net@77[50] net@77[49]
-+net@77[48] net@77[47] net@77[46] net@77[45] net@77[44] net@77[43] net@77[42]
-+net@77[51] net@79[41] net@79[40] net@79[39] net@79[38] net@79[37] net@79[50]
-+net@79[49] net@79[48] net@79[47] net@79[46] net@79[45] net@79[44] net@79[43]
-+net@79[42] net@79[51] out[10] out[11] out[12] out[13] out[14] out[15] out[16]
-+out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24]
-+out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32]
-+out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7]
-+out[8] out[9] net@77[27] net@77[26] net@77[25] net@77[24] net@77[23]
-+net@77[22] net@77[21] net@77[20] net@77[19] net@77[18] net@77[36] net@77[17]
-+net@77[16] net@77[15] net@77[14] net@77[13] net@77[12] net@77[11] net@77[10]
-+net@77[9] net@77[8] net@77[35] net@77[7] net@77[6] net@77[5] net@77[4]
-+net@77[3] net@77[2] net@77[1] net@77[0] net@77[34] net@77[33] net@77[32]
-+net@77[31] net@77[30] net@77[29] net@77[28] net@77[27] net@77[26] net@77[25]
-+net@77[24] net@77[23] net@77[22] net@77[21] net@77[20] net@77[19] net@77[18]
-+net@77[36] net@77[17] net@77[16] net@77[15] net@77[14] net@77[13] net@77[12]
-+net@77[11] net@77[10] net@77[9] net@77[8] net@77[35] net@77[7] net@77[6]
-+net@77[5] net@77[4] net@77[3] net@77[2] net@77[1] net@77[0] net@77[34]
-+net@77[33] net@77[32] net@77[31] net@77[30] net@77[29] net@77[28] net@79[27]
-+net@79[26] net@79[25] net@79[24] net@79[23] net@79[22] net@79[21] net@79[20]
-+net@79[19] net@79[18] net@79[36] net@79[17] net@79[16] net@79[15] net@79[14]
-+net@79[13] net@79[12] net@79[11] net@79[10] net@79[9] net@79[8] net@79[35]
-+net@79[7] net@79[6] net@79[5] net@79[4] net@79[3] net@79[2] net@79[1]
-+net@79[0] net@79[34] net@79[33] net@79[32] net@79[31] net@79[30] net@79[29]
-+net@79[28] net@53 net@58 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@64[8] net@58 net@61 upDown8weak
-.ENDS southFifo
-
-*** CELL: stageGroupsM:tokenFIFO{sch}
-.SUBCKT tokenFIFO pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1] succ
-XaStage@3 aStage@3_fire sir[9] pred s[1] net@0 aStage
-XaStage@4 aStage@4_fire sir[9] net@1 s[2] net@2 aStage
-XaStage@5 aStage@5_fire sir[9] net@3 s[3] succ aStage
-XscanEx3h@1 s[1] s[2] s[3] sir[9] sir[3] sir[2] sir[5] sir[1] sor[1] scanEx3h
-Xtc[1] tranCap
-Xtc[2] tranCap
-Xtc[3] tranCap
-Xtc[4] tranCap
-Xtc[5] tranCap
-Xtc[6] tranCap
-Xtc[7] tranCap
-Xtc[8] tranCap
-Xtc[9] tranCap
-Xtc[10] tranCap
-Xtc[11] tranCap
-Xtc[12] tranCap
-Xtc[13] tranCap
-Xtc[14] tranCap
-Xtc[15] tranCap
-Xtc[16] tranCap
-Xwire90@0 net@0 net@1 wire90-291_8-layer_1-width_3
-Xwire90@1 net@2 net@3 wire90-291_8-layer_1-width_3
-.ENDS tokenFIFO
-
-.global gnd vdd
-
-*** TOP LEVEL CELL: marinaOutDock{sch}
-XnorthFif@1 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3]
-+dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] ain[10] ain[11] ain[12]
-+ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8]
-+ain[9] ain[T] net@38 fout dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15]
-+dsD[16] dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23]
-+dsD[24] dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31]
-+dsD[32] dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6]
-+dsD[7] dsD[8] dsD[9] din[10] din[11] din[12] din[13] din[14] din[15] din[16]
-+din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24]
-+din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32]
-+din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7]
-+din[8] din[9] dockSucc[D] net@116[8] net@116[7] net@116[6] net@116[5]
-+net@116[4] sic[6] sic[7] sic[8] sic[9] net@117[8] net@117[7] net@117[6]
-+net@117[5] net@117[4] sid[6] sid[7] sid[8] sid[9] net@109[8] net@109[7]
-+net@109[6] net@109[5] net@109[4] sir[6] sir[7] sir[8] sir[9] dockPred[D]
-+northFifo
-XoutputDo@0 net@14 din[10] din[11] din[12] din[13] din[14] din[15] din[16]
-+din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24]
-+din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32]
-+din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7]
-+din[8] din[9] ain[6] dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2]
-+dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] dsD[10] dsD[11]
-+dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] dsD[17] dsD[18] dsD[19] dsD[1]
-+dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25] dsD[26] dsD[27] dsD[28]
-+dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33] dsD[34] dsD[35] dsD[36]
-+dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8] dsD[9] net@44 iout[10]
-+iout[11] iout[12] iout[13] iout[14] iout[15] iout[16] iout[17] iout[18]
-+iout[20] iout[1] iout[21] iout[22] iout[23] iout[24] iout[25] iout[26]
-+iout[27] iout[28] iout[29] iout[30] iout[2] iout[31] iout[32] iout[33]
-+iout[34] iout[35] iout[36] iout[37] iout[3] iout[4] iout[5] iout[6] iout[7]
-+iout[8] iout[9] aout[T] dockPred[D] dockPred[T] ain[14] net@119[8] net@109[7]
-+net@109[6] net@109[5] net@109[4] sir[6] sir[7] sir[8] sir[9] net@120[8]
-+dockSucc[D] dockSucc[T] outputDock
-XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@44 fin
-+net@38 iout[10] iout[11] iout[12] iout[13] iout[14] iout[15] iout[16]
-+iout[17] iout[18] iout[19] iout[1] iout[20] iout[21] iout[22] iout[23]
-+iout[24] iout[25] iout[26] iout[27] iout[28] iout[29] iout[2] iout[30]
-+iout[31] iout[32] iout[33] iout[34] iout[35] iout[36] iout[37] iout[3]
-+iout[4] iout[5] iout[6] iout[7] iout[8] iout[9] sic[1] sic[2] sic[3] sic[4]
-+sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
-+sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@116[8] net@116[7] net@116[6] net@116[5] net@116[4] net@117[8]
-+net@117[7] net@117[6] net@117[5] net@117[4] net@119[8] net@109[7] net@109[6]
-+net@109[5] net@109[4] net@14 southFifo
-XtokenFIF@1 dockSucc[T] net@120[8] net@109[7] net@109[6] net@109[5]
-+net@109[4] sir[6] sir[7] sir[8] sir[9] net@109[8] dockPred[T] tokenFIFO
-.END
+++ /dev/null
-/* Verilog for cell 'marinaOutDock{sch}' from library 'aMarinaM' */
-/* Created on Mon Nov 17, 2008 08:47:24 */
-/* Last revised on Sat May 02, 2009 06:16:53 */
-/* Written on Sat May 16, 2009 16:19:19 by Electric VLSI Design System, version 8.08k */
-
-module orangeTSMC090nm__wire(a);
- input a;
-
- supply0 gnd;
-endmodule /* orangeTSMC090nm__wire */
-
-module orangeTSMC090nm__wire90(a);
- inout a;
-
- supply0 gnd;
- orangeTSMC090nm__wire wire_0(.a(a));
-endmodule /* orangeTSMC090nm__wire90 */
-
-module countersL__cntShift(ctgLO, myp1p, myp2p, sid, sod);
- input ctgLO;
- output myp1p;
- output myp2p;
- inout [1:9] sid;
- inout [1:1] sod;
-
- supply1 vdd;
- supply0 gnd;
- wire net_97, net_99;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (myp1p, net_97);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (myp2p, net_99);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_4 (net_99, ctgLO, sid[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_5 (net_97, ctgLO, sid[3]);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_9(.a(net_97));
- orangeTSMC090nm__wire90 wire90_10(.a(net_99));
-endmodule /* countersL__cntShift */
-
-module countersL__cntFreq(count, fin, myFin, ctgLO, fout);
- input count;
- input fin;
- input myFin;
- output ctgLO;
- output fout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_17, net_33, net_39;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_17, ctgLO);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (ctgLO, count);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_39, net_17, myFin);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_33, ctgLO, fin);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (fout, net_33, net_39);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_2(.a(net_17));
- orangeTSMC090nm__wire90 wire90_4(.a(net_33));
- orangeTSMC090nm__wire90 wire90_5(.a(net_39));
-endmodule /* countersL__cntFreq */
-
-module orangeTSMC090nm__NMOSxwk(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply0 gnd;
- /* begin Verilog_template for orangeTSMC090nm:NMOSfwk{sch}*/
- rtranif1 #(100) NMOSfwk_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__NMOSxwk */
-
-module orangeTSMC090nm__PMOSxwk(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply1 vdd;
- /* begin Verilog_template for orangeTSMC090nm:PMOSfwk{sch}*/
- rtranif0 #(100) PMOSfwk_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__PMOSxwk */
-
-module latchPartsK__latchKeep(out_B_, out_s_);
- output out_B_;
- output out_s_;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSxwk NMOSxwk_0(.g(out_B_), .d(out_s_), .s(gnd));
- orangeTSMC090nm__NMOSxwk NMOSxwk_1(.g(out_s_), .d(out_B_), .s(gnd));
- orangeTSMC090nm__PMOSxwk PMOSxwk_0(.g(out_B_), .d(out_s_), .s(vdd));
- orangeTSMC090nm__PMOSxwk PMOSxwk_1(.g(out_s_), .d(out_B_), .s(vdd));
-endmodule /* latchPartsK__latchKeep */
-
-module orangeTSMC090nm__NMOSx(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply0 gnd;
- /* begin Verilog_template for orangeTSMC090nm:NMOSf{sch}*/
- tranif1 #(100) NMOSf_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__NMOSx */
-
-module latchPartsK__latchPointF(hcl, in, x_F_, x_T_);
- input hcl;
- input [1:1] in;
- output x_F_;
- output x_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- orangeTSMC090nm__NMOSx PMOSx_0(.g(hcl), .d(in[1]), .s(x_T_));
- orangeTSMC090nm__NMOSx PMOSx_1(.g(hcl), .d(net_8), .s(x_F_));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_8, in[1]);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* latchPartsK__latchPointF */
-
-module latchesK__raw2inLatchF(hcl_A_, hcl_B_, inA, inB, out_F_);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output out_F_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_45;
-
- latchPartsK__latchKeep latchKee_0(.out_B_(out_F_), .out_s_(net_45));
- latchPartsK__latchPointF latchPoi_0(.hcl(hcl_A_), .in(inA[1:1]),
- .x_F_(out_F_), .x_T_(net_45));
- latchPartsK__latchPointF latchPoi_1(.hcl(hcl_B_), .in(inB[1:1]),
- .x_F_(out_F_), .x_T_(net_45));
- orangeTSMC090nm__wire90 wire90_0(.a(net_45));
-endmodule /* latchesK__raw2inLatchF */
-
-module latchesK__latch2in10A(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire dataBar;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(dataBar));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (out[1], dataBar);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_1(.a(dataBar));
-endmodule /* latchesK__latch2in10A */
-
-module redFive__nor2n_sy(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nor2n_sy */
-
-module countersL__cntScnOne(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire cA, cB, net_14, net_3;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_14, out);
- // end Verilog_template
- latchesK__latch2in10A latch2in_0(.hcl_A_(cB), .hcl_B_(p1p), .inA({net_3}),
- .inB({net_3}), .out({out}));
- latchesK__latch2in10A latch2in_1(.hcl_A_(cA), .hcl_B_(p2p), .inA({net_14}),
- .inB({sin}), .out({net_3}));
- redFive__nor2n_sy nor2n_sy_0(.ina(ctgLO), .inb(cB), .out(cA));
- redFive__nor2n_sy nor2n_sy_2(.ina(ctgLO), .inb(cin), .out(cB));
- orangeTSMC090nm__wire90 wire90_0(.a(net_14));
- orangeTSMC090nm__wire90 wire90_1(.a(net_3));
- orangeTSMC090nm__wire90 wire90_2(.a(cA));
- orangeTSMC090nm__wire90 wire90_3(.a(cB));
-endmodule /* countersL__cntScnOne */
-
-module countersL__cntScnFour(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_40, net_43, net_46;
-
- countersL__cntScnOne cntScnOn_0(.cin(net_46), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_46), .out(net_40));
- countersL__cntScnOne cntScnOn_1(.cin(cin), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(sin), .out(net_43));
- countersL__cntScnOne cntScnOn_2(.cin(net_43), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_43), .out(net_46));
- countersL__cntScnOne cntScnOn_3(.cin(net_40), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_40), .out(out));
- orangeTSMC090nm__wire90 wire90_4(.a(net_40));
- orangeTSMC090nm__wire90 wire90_5(.a(net_43));
- orangeTSMC090nm__wire90 wire90_6(.a(net_46));
-endmodule /* countersL__cntScnFour */
-
-module countersL__cntScnThree(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_43, net_46;
-
- countersL__cntScnOne cntScnOn_0(.cin(net_46), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_46), .out(out));
- countersL__cntScnOne cntScnOn_1(.cin(cin), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(sin), .out(net_43));
- countersL__cntScnOne cntScnOn_2(.cin(net_43), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_43), .out(net_46));
- orangeTSMC090nm__wire90 wire90_5(.a(net_43));
- orangeTSMC090nm__wire90 wire90_6(.a(net_46));
-endmodule /* countersL__cntScnThree */
-
-module countersL__cntScnTwelve(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_43, net_46;
-
- countersL__cntScnFour cntScnFo_0(.cin(net_46), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_46), .out(out));
- countersL__cntScnFour cntScnFo_1(.cin(cin), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(sin), .out(net_43));
- countersL__cntScnFour cntScnFo_2(.cin(net_43), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_43), .out(net_46));
- orangeTSMC090nm__wire90 wire90_5(.a(net_43));
- orangeTSMC090nm__wire90 wire90_6(.a(net_46));
-endmodule /* countersL__cntScnTwelve */
-
-module countersL__instructionCount(cin, count, fin, fout, sid, sod);
- input cin;
- input count;
- input fin;
- output fout;
- inout [1:9] sid;
- inout [1:1] sod;
-
- supply1 vdd;
- supply0 gnd;
- wire ctgLO, myp1p, myp2p, net_1, net_77, net_78;
-
- countersL__cntShift cntContr_0(.ctgLO(ctgLO), .myp1p(myp1p), .myp2p(myp2p),
- .sid(sid[1:9]), .sod(sod[1:1]));
- countersL__cntFreq cntFreq_0(.count(count), .fin(fin), .myFin(net_77),
- .ctgLO(ctgLO), .fout(fout));
- countersL__cntScnFour cntScnFo_1(.cin(cin), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(sid[1]), .out(net_1));
- countersL__cntScnThree cntScnTh_0(.cin(net_77), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(net_77), .out(net_78));
- countersL__cntScnTwelve cntScnTw_3(.cin(net_1), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(net_1), .out(net_77));
- countersL__cntScnTwelve cntScnTw_5(.cin(net_78), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(net_78), .out(sod[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_1));
- orangeTSMC090nm__wire90 wire90_1(.a(net_77));
- orangeTSMC090nm__wire90 wire90_2(.a(net_78));
- orangeTSMC090nm__wire90 wire90_3(.a(sod[1]));
-endmodule /* countersL__instructionCount */
-
-module latchesK__raw1inLatchF(hcl, in, out_F_);
- input hcl;
- input [1:1] in;
- output out_F_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_45;
-
- latchPartsK__latchKeep latchFlo_0(.out_B_(out_F_), .out_s_(net_45));
- latchPartsK__latchPointF latchPoi_0(.hcl(hcl), .in(in[1:1]), .x_F_(out_F_),
- .x_T_(net_45));
- orangeTSMC090nm__wire90 wire90_0(.a(net_45));
-endmodule /* latchesK__raw1inLatchF */
-
-module latchesK__latch1in60C(hcl, inS, outS);
- input hcl;
- input [1:1] inS;
- output [1:1] outS;
-
- supply1 vdd;
- supply0 gnd;
- wire net_14, net_16, net_17;
-
- latchesK__raw1inLatchF hi2inLat_0(.hcl(hcl), .in(inS[1:1]),
- .out_F_(net_14));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_16, net_14);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (net_17, net_16);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_2 (outS[1], net_17);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_14));
- orangeTSMC090nm__wire90 wire90_1(.a(net_16));
- orangeTSMC090nm__wire90 wire90_2(.a(net_17));
-endmodule /* latchesK__latch1in60C */
-
-module registersM__addr1in60Cx7(ain, fire, aout);
- input [1:7] ain;
- input fire;
- output [1:7] aout;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in60C lat_1_(.hcl(fire), .inS({ain[1]}), .outS({aout[1]}));
- latchesK__latch1in60C lat_2_(.hcl(fire), .inS({ain[2]}), .outS({aout[2]}));
- latchesK__latch1in60C lat_3_(.hcl(fire), .inS({ain[3]}), .outS({aout[3]}));
- latchesK__latch1in60C lat_4_(.hcl(fire), .inS({ain[4]}), .outS({aout[4]}));
- latchesK__latch1in60C lat_5_(.hcl(fire), .inS({ain[5]}), .outS({aout[5]}));
- latchesK__latch1in60C lat_6_(.hcl(fire), .inS({ain[6]}), .outS({aout[6]}));
- latchesK__latch1in60C lat_7_(.hcl(fire), .inS({ain[7]}), .outS({aout[7]}));
-endmodule /* registersM__addr1in60Cx7 */
-
-module registersM__addr1in60Cx15(ain, ain_TT_, fire, aout, aout_TT_);
- input [1:14] ain;
- input ain_TT_;
- input fire;
- output [1:14] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- registersM__addr1in60Cx7 addr1in6_0(.ain(ain[8:14]), .fire(fire),
- .aout(aout[8:14]));
- registersM__addr1in60Cx7 addr1in6_1(.ain(ain[1:7]), .fire(fire),
- .aout(aout[1:7]));
- latchesK__latch1in60C latch1in_0(.hcl(fire), .inS({ain_TT_}),
- .outS({aout_TT_}));
- orangeTSMC090nm__wire90 wire90_0(.a(fire));
- orangeTSMC090nm__wire90 wire90_1(.a(fire));
-endmodule /* registersM__addr1in60Cx15 */
-
-module registersM__data1in60Cx18(dcl, in, out);
- input dcl;
- input [1:18] in;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in60C lat_1_(.hcl(dcl), .inS({in[1]}), .outS({out[1]}));
- latchesK__latch1in60C lat_2_(.hcl(dcl), .inS({in[2]}), .outS({out[2]}));
- latchesK__latch1in60C lat_3_(.hcl(dcl), .inS({in[3]}), .outS({out[3]}));
- latchesK__latch1in60C lat_4_(.hcl(dcl), .inS({in[4]}), .outS({out[4]}));
- latchesK__latch1in60C lat_5_(.hcl(dcl), .inS({in[5]}), .outS({out[5]}));
- latchesK__latch1in60C lat_6_(.hcl(dcl), .inS({in[6]}), .outS({out[6]}));
- latchesK__latch1in60C lat_7_(.hcl(dcl), .inS({in[7]}), .outS({out[7]}));
- latchesK__latch1in60C lat_8_(.hcl(dcl), .inS({in[8]}), .outS({out[8]}));
- latchesK__latch1in60C lat_9_(.hcl(dcl), .inS({in[9]}), .outS({out[9]}));
- latchesK__latch1in60C lat_10_(.hcl(dcl), .inS({in[10]}), .outS({out[10]}));
- latchesK__latch1in60C lat_11_(.hcl(dcl), .inS({in[11]}), .outS({out[11]}));
- latchesK__latch1in60C lat_12_(.hcl(dcl), .inS({in[12]}), .outS({out[12]}));
- latchesK__latch1in60C lat_13_(.hcl(dcl), .inS({in[13]}), .outS({out[13]}));
- latchesK__latch1in60C lat_14_(.hcl(dcl), .inS({in[14]}), .outS({out[14]}));
- latchesK__latch1in60C lat_15_(.hcl(dcl), .inS({in[15]}), .outS({out[15]}));
- latchesK__latch1in60C lat_16_(.hcl(dcl), .inS({in[16]}), .outS({out[16]}));
- latchesK__latch1in60C lat_17_(.hcl(dcl), .inS({in[17]}), .outS({out[17]}));
- latchesK__latch1in60C lat_18_(.hcl(dcl), .inS({in[18]}), .outS({out[18]}));
-endmodule /* registersM__data1in60Cx18 */
-
-module registersM__data1in60Cx37(in, take, out);
- input [1:37] in;
- input take;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__data1in60Cx18 data1in6_1(.dcl(take), .in(in[1:18]),
- .out(out[1:18]));
- registersM__data1in60Cx18 data1in6_2(.dcl(take), .in(in[20:37]),
- .out(out[20:37]));
- latchesK__latch1in60C latch1in_0(.hcl(take), .inS({in[19]}),
- .outS({out[19]}));
- orangeTSMC090nm__wire90 wire90_2(.a(take));
- orangeTSMC090nm__wire90 wire90_3(.a(take));
-endmodule /* registersM__data1in60Cx37 */
-
-module orangeTSMC090nm__PMOSx(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply1 vdd;
- /* begin Verilog_template for orangeTSMC090nm:PMOSf{sch}*/
- tranif0 #(100) PMOSf_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__PMOSx */
-
-module arbiterM__half2inArb(inA, req_B_, cross, grant_B_);
- input inA;
- input req_B_;
- output cross;
- output grant_B_; trireg grant_B_;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__PMOSx NMOSx_0(.g(req_B_), .d(vdd), .s(grant_B_));
- orangeTSMC090nm__NMOSx PMOSx_0(.g(inA), .d(cross), .s(grant_B_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nor2n_0 (cross, inA, req_B_);
- // end Verilog_template
-endmodule /* arbiterM__half2inArb */
-
-module arbiterM__arbiter2(req_A_, req_B_, grant_A_, grant_B_);
- input req_A_;
- input req_B_;
- output grant_A_;
- output grant_B_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_5, net_8;
-
- arbiterM__half2inArb halfArb_2(.inA(net_5), .req_B_(req_A_), .cross(net_8),
- .grant_B_(grant_A_));
- arbiterM__half2inArb halfArb_3(.inA(net_8), .req_B_(req_B_), .cross(net_5),
- .grant_B_(grant_B_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
- orangeTSMC090nm__wire90 wire90_1(.a(net_5));
-endmodule /* arbiterM__arbiter2 */
-
-module centersJ__ctrAND2in100LT(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_135, net_139, net_144;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_8 (net_135, inB);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_139, inA);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_10 (out, net_144);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
- nand (strong0, strong1) #(100) nand2LT__0 (net_144, net_139, net_135);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_4(.a(net_135));
- orangeTSMC090nm__wire90 wire90_5(.a(net_144));
- orangeTSMC090nm__wire90 wire90_6(.a(net_139));
-endmodule /* centersJ__ctrAND2in100LT */
-
-module driversM__dataDriver60(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_7;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out, net_7);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_7, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_7));
-endmodule /* driversM__dataDriver60 */
-
-module redFive__pms3(g, g2, g3, d);
- input g;
- input g2;
- input g3;
- output d;
-
- supply1 vdd;
- wire net_2, net_5;
-
- orangeTSMC090nm__PMOSx PMOS_0(.g(g3), .d(d), .s(net_2));
- orangeTSMC090nm__PMOSx PMOS_1(.g(g2), .d(net_2), .s(net_5));
- orangeTSMC090nm__PMOSx PMOS_2(.g(g), .d(net_5), .s(vdd));
-endmodule /* redFive__pms3 */
-
-module driversM__predDri60wMC(in, mc, pred);
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- redFive__pms3 pms3_0(.g(mc), .g2(in), .g3(net_145), .d(pred));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
-endmodule /* driversM__predDri60wMC */
-
-module redFive__nms2(g, g2, d);
- input g;
- input g2;
- output d;
-
- supply0 gnd;
- wire net_0;
-
- orangeTSMC090nm__NMOSx NMOS_0(.g(g2), .d(d), .s(net_0));
- orangeTSMC090nm__NMOSx NMOS_1(.g(g), .d(net_0), .s(gnd));
-endmodule /* redFive__nms2 */
-
-module driversM__sucANDdri60(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_51, inA, inB);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_51), .g2(net_71), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucANDdri60 */
-
-module wiresL__tranCap();
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for orangeTSMC090nm:NMOSf{sch}*/
- tranif1 #(100) NMOSf_1 (gnd, gnd, vdd);
- // end Verilog_template
- /* begin Verilog_template for orangeTSMC090nm:PMOSf{sch}*/
- tranif0 #(100) PMOSf_2 (vdd, vdd, gnd);
- // end Verilog_template
-endmodule /* wiresL__tranCap */
-
-module gaspM__gaspDrain(clear, go, pred, silent, tok, fire, s, succ, take);
- input clear;
- input go;
- input pred;
- input silent;
- input tok;
- output fire;
- output [1:2] s;
- output succ;
- output take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_241, net_353, net_360, net_463, net_472;
-
- arbiterM__arbiter2 arbiter2_0(.req_A_(pred), .req_B_(net_360),
- .grant_A_(net_241), .grant_B_(net_353));
- centersJ__ctrAND2in100LT ctrAND2i_5(.inA(net_241), .inB(succ), .out(fire));
- driversM__dataDriver60 dataDriv_0(.inA(tok), .inB(fire), .out(take));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_360, go);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_472, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_463, silent);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[2], net_353);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[1], net_472);
- // end Verilog_template
- driversM__predDri60wMC predDri6_1(.in(fire), .mc(clear), .pred(pred));
- driversM__sucANDdri60 sucANDdr_4(.inA(net_463), .inB(fire), .succ(succ));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_241));
- orangeTSMC090nm__wire90 wire90_7(.a(net_360));
- orangeTSMC090nm__wire90 wire90_10(.a(net_353));
- orangeTSMC090nm__wire90 wire90_11(.a(s[2]));
- orangeTSMC090nm__wire90 wire90_15(.a(net_472));
- orangeTSMC090nm__wire90 wire90_16(.a(net_463));
-endmodule /* gaspM__gaspDrain */
-
-module latchesK__latch1in10A(hcl, in, out);
- input hcl;
- input [1:1] in;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18;
-
- latchesK__raw1inLatchF hi2inLat_0(.hcl(hcl), .in(in[1:1]), .out_F_(net_18));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (out[1], net_18);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
-endmodule /* latchesK__latch1in10A */
-
-module latchesK__latch2in10Alo(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire dataBar;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(dataBar));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (out[1], dataBar);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(dataBar));
-endmodule /* latchesK__latch2in10Alo */
-
-module scanM__scanCellE(dIn, p1p, p2p, rd, sin, sout);
- input [1:1] dIn;
- input p1p;
- input p2p;
- input rd;
- input sin;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_2;
-
- latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2}));
- latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}),
- .inB(dIn[1:1]), .out({sout}));
- orangeTSMC090nm__wire90 wire90_0(.a(net_2));
-endmodule /* scanM__scanCellE */
-
-module scanM__scanEx2(dIn, sir, sor);
- input [1:2] dIn;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_26;
-
- scanM__scanCellE scanCell_3(.dIn({dIn[1]}), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(sir[1]), .sout(net_26));
- scanM__scanCellE scanCell_4(.dIn({dIn[2]}), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(net_26), .sout(sor[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_26));
-endmodule /* scanM__scanEx2 */
-
-module latchPartsK__latchPointFmcHI(mc, x_F_, x_T_);
- input mc;
- output x_F_;
- output x_T_;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSx PMOSx_0(.g(mc), .d(gnd), .s(x_T_));
- orangeTSMC090nm__NMOSx PMOSx_1(.g(mc), .d(vdd), .s(x_F_));
-endmodule /* latchPartsK__latchPointFmcHI */
-
-module latchesK__raw2inLatchFmc(hcl, inA, mc, out_F_);
- input hcl;
- input [1:1] inA;
- input mc;
- output out_F_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_45;
-
- latchPartsK__latchKeep latchKee_0(.out_B_(out_F_), .out_s_(net_45));
- latchPartsK__latchPointF latchPoi_0(.hcl(hcl), .in(inA[1:1]), .x_F_(out_F_),
- .x_T_(net_45));
- latchPartsK__latchPointFmcHI latchPoi_1(.mc(mc), .x_F_(out_F_),
- .x_T_(net_45));
- orangeTSMC090nm__wire90 wire90_0(.a(net_45));
-endmodule /* latchesK__raw2inLatchFmc */
-
-module latchesK__latch2in10Alomc(hcl, inA, mc, out);
- input hcl;
- input [1:1] inA;
- input mc;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire dataBar;
-
- latchesK__raw2inLatchFmc hi2inLat_0(.hcl(hcl), .inA(inA[1:1]), .mc(mc),
- .out_F_(dataBar));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (out[1], dataBar);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(dataBar));
-endmodule /* latchesK__latch2in10Alomc */
-
-module scanM__scanCellF(mc, p1p, p2p, rd, sin, wr, dout, sout);
- input mc;
- input p1p;
- input p2p;
- input rd;
- input sin;
- input wr;
- output [1:1] dout;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_2;
-
- latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2}));
- latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}),
- .inB(dout[1:1]), .out({sout}));
- latchesK__latch2in10Alomc latch2in_1(.hcl(wr), .inA({sout}), .mc(mc),
- .out(dout[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_2));
-endmodule /* scanM__scanCellF */
-
-module scanM__scanCellFtall(mc, p1p, p2p, rd, sin, wr, dout, sout);
- input mc;
- input p1p;
- input p2p;
- input rd;
- input sin;
- input wr;
- output [1:1] dout;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_2;
-
- latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2}));
- latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}),
- .inB(dout[1:1]), .out({sout}));
- latchesK__latch2in10Alomc latch2in_1(.hcl(wr), .inA({sout}), .mc(mc),
- .out(dout[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_2));
-endmodule /* scanM__scanCellFtall */
-
-module scanM__scanFx3tallL(dout, dout_1, dout_2, sic, soc);
- output [1:1] dout;
- output [2:2] dout_1;
- output [3:3] dout_2;
- inout [1:9] sic;
- inout [1:1] soc;
-
- supply1 vdd;
- supply0 gnd;
- wire net_30, net_31;
-
- scanM__scanCellF scanCell_5(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]),
- .sout(net_31));
- scanM__scanCellF scanCell_6(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_31), .wr(sic[4]), .dout(dout_2[3:3]),
- .sout(soc[1]));
- scanM__scanCellFtall scanCell_7(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]),
- .sout(net_30));
- orangeTSMC090nm__wire90 wire90_0(.a(net_30));
- orangeTSMC090nm__wire90 wire90_1(.a(net_31));
-endmodule /* scanM__scanFx3tallL */
-
-module stagesM__drainStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ,
- sic, sir, soc, sor);
- input [14:1] ain;
- input ain_TT_;
- input [1:37] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output [1:37] out;
- output succ;
- inout [1:9] sic;
- inout [1:9] sir;
- inout [1:1] soc;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire clear, go, net_4, net_5, silent;
- wire [1:0] net_17;
-
- registersM__addr1in60Cx15 addr1in6_0(.ain({ain[1], ain[2], ain[3], ain[4],
- ain[5], ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12],
- ain[13], ain[14]}), .ain_TT_(ain_TT_), .fire(net_4), .aout({aout[1],
- aout[2], aout[3], aout[4], aout[5], aout[6], aout[7], aout[8], aout[9],
- aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- registersM__data1in60Cx37 data1in6_0(.in(in[1:37]), .take(net_5),
- .out(out[1:37]));
- gaspM__gaspDrain gaspDrai_0(.clear(clear), .go(go), .pred(pred),
- .silent(silent), .tok(ain_TT_), .fire(net_4), .s({net_17[1], net_17[0]}),
- .succ(succ), .take(net_5));
- scanM__scanEx2 scanEx2v_1(.dIn({net_17[1], net_17[0]}), .sir(sir[1:9]),
- .sor(sor[1:1]));
- scanM__scanFx3tallL scanFx3t_1(.dout({go}), .dout_1({clear}),
- .dout_2({silent}), .sic(sic[1:9]), .soc(soc[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
-endmodule /* stagesM__drainStage */
-
-module latchesK__latch2in60C(hcl_A_, hcl_B_, inA, inB, outS);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] outS;
-
- supply1 vdd;
- supply0 gnd;
- wire net_14, net_16, net_17;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(net_14));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_16, net_14);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (net_17, net_16);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_2 (outS[1], net_17);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_14));
- orangeTSMC090nm__wire90 wire90_1(.a(net_16));
- orangeTSMC090nm__wire90 wire90_2(.a(net_17));
-endmodule /* latchesK__latch2in60C */
-
-module latchGroupsK__latchWscM2(hcl, in, sin, out, sout, p1p, p2p, rd, wr);
- input hcl;
- input [1:1] in;
- input sin;
- output [1:1] out;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
- inout wr;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in60C hi2inLat_1(.hcl_A_(hcl), .hcl_B_(wr), .inA(in[1:1]),
- .inB({sout}), .outS(out[1:1]));
- scanM__scanCellE scanCell_3(.dIn(out[1:1]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(sout));
-endmodule /* latchGroupsK__latchWscM2 */
-
-module registersM__addr1in60Cx7scan(ain, fire, sin, aout, sout, p1p, p2p, rd,
- wr_A_);
- input [1:7] ain;
- input fire;
- input sin;
- output [1:7] aout;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
- inout wr_A_;
-
- supply1 vdd;
- supply0 gnd;
- wire [2:7] xin;
-
- latchGroupsK__latchWscM2 la_1_(.hcl(fire), .in({ain[1]}), .sin(sin),
- .out({aout[1]}), .sout(xin[2]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_2_(.hcl(fire), .in({ain[2]}), .sin(xin[2]),
- .out({aout[2]}), .sout(xin[3]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_3_(.hcl(fire), .in({ain[3]}), .sin(xin[3]),
- .out({aout[3]}), .sout(xin[4]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_4_(.hcl(fire), .in({ain[4]}), .sin(xin[4]),
- .out({aout[4]}), .sout(xin[5]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_5_(.hcl(fire), .in({ain[5]}), .sin(xin[5]),
- .out({aout[5]}), .sout(xin[6]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_6_(.hcl(fire), .in({ain[6]}), .sin(xin[6]),
- .out({aout[6]}), .sout(xin[7]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_7_(.hcl(fire), .in({ain[7]}), .sin(xin[7]),
- .out({aout[7]}), .sout(sout), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
-endmodule /* registersM__addr1in60Cx7scan */
-
-module registersM__data1in60Cx18scan(dcl, in, sin, out, sout, p1p, p2p, rd,
- wr_D_);
- input dcl;
- input [1:18] in;
- input sin;
- output [1:18] out;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
- inout wr_D_;
-
- supply1 vdd;
- supply0 gnd;
- wire [2:18] xin;
-
- latchGroupsK__latchWscM2 la_1_(.hcl(dcl), .in({in[1]}), .sin(sin),
- .out({out[1]}), .sout(xin[2]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_2_(.hcl(dcl), .in({in[2]}), .sin(xin[2]),
- .out({out[2]}), .sout(xin[3]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_3_(.hcl(dcl), .in({in[3]}), .sin(xin[3]),
- .out({out[3]}), .sout(xin[4]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_4_(.hcl(dcl), .in({in[4]}), .sin(xin[4]),
- .out({out[4]}), .sout(xin[5]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_5_(.hcl(dcl), .in({in[5]}), .sin(xin[5]),
- .out({out[5]}), .sout(xin[6]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_6_(.hcl(dcl), .in({in[6]}), .sin(xin[6]),
- .out({out[6]}), .sout(xin[7]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_7_(.hcl(dcl), .in({in[7]}), .sin(xin[7]),
- .out({out[7]}), .sout(xin[8]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_8_(.hcl(dcl), .in({in[8]}), .sin(xin[8]),
- .out({out[8]}), .sout(xin[9]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_9_(.hcl(dcl), .in({in[9]}), .sin(xin[9]),
- .out({out[9]}), .sout(xin[10]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_10_(.hcl(dcl), .in({in[10]}), .sin(xin[10]),
- .out({out[10]}), .sout(xin[11]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_11_(.hcl(dcl), .in({in[11]}), .sin(xin[11]),
- .out({out[11]}), .sout(xin[12]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_12_(.hcl(dcl), .in({in[12]}), .sin(xin[12]),
- .out({out[12]}), .sout(xin[13]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_13_(.hcl(dcl), .in({in[13]}), .sin(xin[13]),
- .out({out[13]}), .sout(xin[14]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_14_(.hcl(dcl), .in({in[14]}), .sin(xin[14]),
- .out({out[14]}), .sout(xin[15]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_15_(.hcl(dcl), .in({in[15]}), .sin(xin[15]),
- .out({out[15]}), .sout(xin[16]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_16_(.hcl(dcl), .in({in[16]}), .sin(xin[16]),
- .out({out[16]}), .sout(xin[17]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_17_(.hcl(dcl), .in({in[17]}), .sin(xin[17]),
- .out({out[17]}), .sout(xin[18]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_18_(.hcl(dcl), .in({in[18]}), .sin(xin[18]),
- .out({out[18]}), .sout(sout), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
-endmodule /* registersM__data1in60Cx18scan */
-
-module centersJ__ctrAND3in30(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_19, net_6, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_19, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (out, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_9, net_19, net_6);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_9));
- orangeTSMC090nm__wire90 wire90_2(.a(net_19));
-endmodule /* centersJ__ctrAND3in30 */
-
-module centersJ__ctrAND3in100A(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_19, net_6, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_19, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (out, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_9, net_19, net_6);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_9));
- orangeTSMC090nm__wire90 wire90_2(.a(net_19));
-endmodule /* centersJ__ctrAND3in100A */
-
-module gaspM__fillScanControl(wr_A_, wr_D_, si, so);
- output wr_A_;
- output wr_D_;
- inout [1:9] si;
- inout [1:1] so;
-
- supply1 vdd;
- supply0 gnd;
- wire net_4;
- wire [1:1] scanCell_2_dIn;
- wire [1:1] scanCell_3_dIn;
-
- driversM__dataDriver60 dataDriv_2(.inA(so[1]), .inB(si[4]), .out(wr_D_));
- driversM__dataDriver60 dataDriv_3(.inA(net_4), .inB(si[4]), .out(wr_A_));
- scanM__scanCellE scanCell_2(.dIn(scanCell_2_dIn[1:1]), .p1p(si[3]),
- .p2p(si[2]), .rd(si[5]), .sin(si[1]), .sout(net_4));
- scanM__scanCellE scanCell_3(.dIn(scanCell_3_dIn[1:1]), .p1p(si[3]),
- .p2p(si[2]), .rd(si[5]), .sin(net_4), .sout(so[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_4));
- orangeTSMC090nm__wire90 wire90_1(.a(si[4]));
-endmodule /* gaspM__fillScanControl */
-
-module driversM__latchDriver60(in, out);
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_16;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_16, in);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (out, net_16);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_16));
-endmodule /* driversM__latchDriver60 */
-
-module driversM__sucORdri60(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_51), .g2(net_71), .d(succ));
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_0 (net_51, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucORdri60 */
-
-module gaspM__gaspFill(block, fill, pred, fire, s, succ, take, wr_A_, wr_D_,
- si, so);
- input block;
- input fill;
- input pred;
- output fire;
- output [1:2] s;
- output succ;
- output take;
- output wr_A_;
- output wr_D_;
- inout [1:9] si;
- inout [1:1] so;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_B_, net_454, net_537;
-
- centersJ__ctrAND3in30 ctrAND3i_1(.inA(net_537), .inB(succ), .inC(fire),
- .out(fire_B_));
- centersJ__ctrAND3in100A ctrAND3i_3(.inA(net_454), .inB(succ), .inC(block),
- .out(fire));
- gaspM__fillScanControl fillScan_1(.wr_A_(wr_A_), .wr_D_(wr_D_), .si(si[1:9]),
- .so(so[1:1]));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_454, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_537, fill);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_454);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[2], net_537);
- // end Verilog_template
- driversM__latchDriver60 latchDri_1(.in(fire), .out(take));
- driversM__predDri60wMC predDri6_2(.in(fire), .mc(si[9]), .pred(pred));
- driversM__sucORdri60 sucORdri_2(.inA(fire), .inB(fire_B_), .succ(succ));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_537));
- orangeTSMC090nm__wire90 wire90_12(.a(net_454));
- orangeTSMC090nm__wire90 wire90_15(.a(fire_B_));
-endmodule /* gaspM__gaspFill */
-
-module scanM__scanAmp(in, out);
- inout [1:1] in;
- inout [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_1;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_1, in[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (out[1], net_1);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_1));
-endmodule /* scanM__scanAmp */
-
-module scanM__scanAMPx5(si, so);
- input [1:9] si;
- output [1:5] so;
-
- supply1 vdd;
- supply0 gnd;
- scanM__scanAmp sa_1_(.in({si[1]}), .out({so[1]}));
- scanM__scanAmp sa_2_(.in({si[2]}), .out({so[2]}));
- scanM__scanAmp sa_3_(.in({si[3]}), .out({so[3]}));
- scanM__scanAmp sa_4_(.in({si[4]}), .out({so[4]}));
- scanM__scanAmp sa_5_(.in({si[5]}), .out({so[5]}));
-endmodule /* scanM__scanAMPx5 */
-
-module scanM__scanFx3(dout, dout_1, dout_2, sic, soc);
- output [1:1] dout;
- output [2:2] dout_1;
- output [3:3] dout_2;
- inout [1:9] sic;
- inout [1:1] soc;
-
- supply1 vdd;
- supply0 gnd;
- wire net_30, net_31;
-
- scanM__scanCellF scanCell_4(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]),
- .sout(net_30));
- scanM__scanCellF scanCell_5(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]),
- .sout(net_31));
- scanM__scanCellF scanCell_6(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_31), .wr(sic[4]), .dout(dout_2[3:3]),
- .sout(soc[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_30));
- orangeTSMC090nm__wire90 wire90_1(.a(net_31));
-endmodule /* scanM__scanFx3 */
-
-module stagesM__fillStage(ain, ain_TT_, \in[1] , \in[2] , \in[3] , \in[4] ,
- \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12]
- , \in[13] , \in[14] , \in[15] , \in[16] , \in[17] , \in[18] , \in[20] ,
- \in[21] , \in[22] , \in[23] , \in[24] , \in[25] , \in[26] , \in[27] ,
- \in[28] , \in[29] , \in[30] , \in[31] , \in[32] , \in[33] , \in[34] ,
- \in[35] , \in[36] , \in[37] , in_1, pred, aout, aout_TT_, extra, fire,
- \out[1] , \out[2] , \out[3] , \out[4] , \out[5] , \out[6] , \out[7] ,
- \out[8] , \out[9] , \out[10] , \out[11] , \out[12] , \out[13] , \out[14]
- , \out[15] , \out[16] , \out[17] , \out[18] , \out[20] , \out[21] ,
- \out[22] , \out[23] , \out[24] , \out[25] , \out[26] , \out[27] ,
- \out[28] , \out[29] , \out[30] , \out[31] , \out[32] , \out[33] ,
- \out[34] , \out[35] , \out[36] , \out[37] , out_1, succ, sic, sid, sir,
- soc, sod, sor);
- input [1:14] ain;
- input ain_TT_;
- input \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] ,
- \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , \in[15] ,
- \in[16] , \in[17] , \in[18] , \in[20] , \in[21] , \in[22] , \in[23] ,
- \in[24] , \in[25] , \in[26] , \in[27] , \in[28] , \in[29] , \in[30] ,
- \in[31] , \in[32] , \in[33] , \in[34] , \in[35] , \in[36] , \in[37] ;
- input [19:19] in_1;
- input pred;
- output [1:14] aout;
- output aout_TT_;
- output extra;
- output fire;
- output \out[1] , \out[2] , \out[3] , \out[4] , \out[5] , \out[6] , \out[7] ,
- \out[8] , \out[9] , \out[10] , \out[11] , \out[12] , \out[13] , \out[14]
- , \out[15] , \out[16] , \out[17] , \out[18] , \out[20] , \out[21] ,
- \out[22] , \out[23] , \out[24] , \out[25] , \out[26] , \out[27] ,
- \out[28] , \out[29] , \out[30] , \out[31] , \out[32] , \out[33] ,
- \out[34] , \out[35] , \out[36] , \out[37] ;
- output [19:19] out_1;
- output succ;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire block, fill, net_0, net_61, net_62, net_64, net_65, net_66, sx_A_, sx_D_;
- wire [8:8] net_139;
- wire [8:8] net_142;
- wire [1:2] s;
- wire [1:5] sx;
- wire [1:1] sy;
- wire [1:1] sz;
-
- registersM__addr1in60Cx7scan addr1in6_0(.ain(ain[1:7]), .fire(fire),
- .sin(net_61), .aout(aout[1:7]), .sout(net_62), .p1p(sx[3]), .p2p(sx[2]),
- .rd(sx[5]), .wr_A_(sx_A_));
- registersM__addr1in60Cx7scan addr1in6_1(.ain(ain[8:14]), .fire(fire),
- .sin(net_62), .aout(aout[8:14]), .sout(net_66), .p1p(sx[3]), .p2p(sx[2]),
- .rd(sx[5]), .wr_A_(sx_A_));
- registersM__data1in60Cx18scan data1in6_0(.dcl(net_0), .in({ \in[1] , \in[2]
- , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] ,
- \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , \in[15] , \in[16]
- , \in[17] , \in[18] }), .sin(net_66), .out({ \out[1] , \out[2] ,
- \out[3] , \out[4] , \out[5] , \out[6] , \out[7] , \out[8] , \out[9]
- , \out[10] , \out[11] , \out[12] , \out[13] , \out[14] , \out[15] ,
- \out[16] , \out[17] , \out[18] }), .sout(net_65), .p1p(sx[3]),
- .p2p(sx[2]), .rd(sx[5]), .wr_D_(sx_D_));
- registersM__data1in60Cx18scan data1in6_1(.dcl(net_0), .in({ \in[20] ,
- \in[21] , \in[22] , \in[23] , \in[24] , \in[25] , \in[26] , \in[27]
- , \in[28] , \in[29] , \in[30] , \in[31] , \in[32] , \in[33] ,
- \in[34] , \in[35] , \in[36] , \in[37] }), .sin(net_64), .out({
- \out[20] , \out[21] , \out[22] , \out[23] , \out[24] , \out[25] ,
- \out[26] , \out[27] , \out[28] , \out[29] , \out[30] , \out[31] ,
- \out[32] , \out[33] , \out[34] , \out[35] , \out[36] , \out[37] }),
- .sout(sz[1]), .p1p(sx[3]), .p2p(sx[2]), .rd(sx[5]), .wr_D_(sx_D_));
- gaspM__gaspFill gaspFill_0(.block(block), .fill(fill), .pred(pred),
- .fire(fire), .s(s[1:2]), .succ(succ), .take(net_0), .wr_A_(sx_A_),
- .wr_D_(sx_D_), .si({sx[1], sx[2], sx[3], sx[4], sx[5], sid[6], sid[7],
- sid[8], sid[9]}), .so(sy[1:1]));
- latchGroupsK__latchWscM2 latchWsc_0(.hcl(net_0), .in(in_1[19:19]),
- .sin(net_65), .out(out_1[19:19]), .sout(net_64), .p1p(sx[3]),
- .p2p(sx[2]), .rd(sx[5]), .wr(sx_D_));
- latchGroupsK__latchWscM2 latchWsc_1(.hcl(fire), .in({ain_TT_}), .sin(sy[1]),
- .out({aout_TT_}), .sout(net_61), .p1p(sx[3]), .p2p(sx[2]), .rd(sx[5]),
- .wr(sx_A_));
- scanM__scanAMPx5 scanAMPx_2(.si(sid[1:9]), .so(sx[1:5]));
- scanM__scanAMPx5 scanAMPx_3(.si({sz[1], sx[2], sx[3], sx[4], sx[5], sid[6],
- sid[7], sid[8], sid[9]}), .so(sod[1:5]));
- scanM__scanAMPx5 scanAMPx_4(.si(sic[1:9]), .so({net_139[8], soc[2], soc[3],
- soc[4], soc[5]}));
- scanM__scanAMPx5 scanAMPx_5(.si(sir[1:9]), .so({net_142[8], sor[2], sor[3],
- sor[4], sor[5]}));
- scanM__scanEx2 scanEx2_0(.dIn(s[1:2]), .sir({net_142[8], sor[2], sor[3],
- sor[4], sor[5], sir[6], sir[7], sir[8], sir[9]}), .sor(sor[1:1]));
- scanM__scanFx3 scanFx3_0(.dout({block}), .dout_1({extra}), .dout_2({fill}),
- .sic({net_139[8], soc[2], soc[3], soc[4], soc[5], sic[6], sic[7], sic[8],
- sic[9]}), .soc(soc[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_0));
- orangeTSMC090nm__wire90 wire90_3(.a(fire));
- orangeTSMC090nm__wire90 wire90_4(.a(net_0));
- orangeTSMC090nm__wire90 wire90_5(.a(fire));
-endmodule /* stagesM__fillStage */
-
-module stageGroupsM__properStopper(ain, ain_TT_, in, pred, aout, aout_TT_,
- extra, fire, out, succ, sic, sid, sir, soc, sod, sor);
- input [14:1] ain;
- input ain_TT_;
- input [37:1] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output extra;
- output fire;
- output [37:1] out;
- output succ;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_41;
- wire [8:8] net_2;
- wire [8:8] net_3;
- wire [51:0] net_65;
-
- stagesM__drainStage drainSta_1(.ain({net_65[37], net_65[38], net_65[39],
- net_65[40], net_65[41], net_65[42], net_65[43], net_65[44], net_65[45],
- net_65[46], net_65[47], net_65[48], net_65[49], net_65[50]}),
- .ain_TT_(net_65[51]), .in({net_65[36], net_65[35], net_65[34],
- net_65[33], net_65[32], net_65[31], net_65[30], net_65[29], net_65[28],
- net_65[27], net_65[26], net_65[25], net_65[24], net_65[23], net_65[22],
- net_65[21], net_65[20], net_65[19], net_65[18], net_65[17], net_65[16],
- net_65[15], net_65[14], net_65[13], net_65[12], net_65[11], net_65[10],
- net_65[9], net_65[8], net_65[7], net_65[6], net_65[5], net_65[4],
- net_65[3], net_65[2], net_65[1], net_65[0]}), .pred(net_41),
- .aout(aout[14:1]), .aout_TT_(aout_TT_), .out({out[1], out[2], out[3],
- out[4], out[5], out[6], out[7], out[8], out[9], out[10], out[11],
- out[12], out[13], out[14], out[15], out[16], out[17], out[18], out[19],
- out[20], out[21], out[22], out[23], out[24], out[25], out[26], out[27],
- out[28], out[29], out[30], out[31], out[32], out[33], out[34], out[35],
- out[36], out[37]}), .succ(succ), .sic({net_3[8], soc[2], soc[3], soc[4],
- soc[5], sic[6], sic[7], sic[8], sic[9]}), .sir({net_2[8], sor[2], sor[3],
- sor[4], sor[5], sir[6], sir[7], sir[8], sir[9]}), .soc(soc[1:1]),
- .sor(sor[1:1]));
- stagesM__fillStage fillStag_1(.ain({ain[1], ain[2], ain[3], ain[4], ain[5],
- ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12], ain[13],
- ain[14]}), .ain_TT_(ain_TT_), .\in[1] (in[1]), .\in[2] (in[2]), .\in[3]
- (in[3]), .\in[4] (in[4]), .\in[5] (in[5]), .\in[6] (in[6]), .\in[7]
- (in[7]), .\in[8] (in[8]), .\in[9] (in[9]), .\in[10] (in[10]), .\in[11]
- (in[11]), .\in[12] (in[12]), .\in[13] (in[13]), .\in[14] (in[14]),
- .\in[15] (in[15]), .\in[16] (in[16]), .\in[17] (in[17]), .\in[18]
- (in[18]), .\in[20] (in[20]), .\in[21] (in[21]), .\in[22] (in[22]),
- .\in[23] (in[23]), .\in[24] (in[24]), .\in[25] (in[25]), .\in[26]
- (in[26]), .\in[27] (in[27]), .\in[28] (in[28]), .\in[29] (in[29]),
- .\in[30] (in[30]), .\in[31] (in[31]), .\in[32] (in[32]), .\in[33]
- (in[33]), .\in[34] (in[34]), .\in[35] (in[35]), .\in[36] (in[36]),
- .\in[37] (in[37]), .in_1(in[19:19]), .pred(pred), .aout({net_65[50],
- net_65[49], net_65[48], net_65[47], net_65[46], net_65[45], net_65[44],
- net_65[43], net_65[42], net_65[41], net_65[40], net_65[39], net_65[38],
- net_65[37]}), .aout_TT_(net_65[51]), .extra(extra), .fire(fire), .\out[1]
- (net_65[36]), .\out[2] (net_65[35]), .\out[3] (net_65[34]), .\out[4]
- (net_65[33]), .\out[5] (net_65[32]), .\out[6] (net_65[31]), .\out[7]
- (net_65[30]), .\out[8] (net_65[29]), .\out[9] (net_65[28]), .\out[10]
- (net_65[27]), .\out[11] (net_65[26]), .\out[12] (net_65[25]), .\out[13]
- (net_65[24]), .\out[14] (net_65[23]), .\out[15] (net_65[22]), .\out[16]
- (net_65[21]), .\out[17] (net_65[20]), .\out[18] (net_65[19]), .\out[20]
- (net_65[17]), .\out[21] (net_65[16]), .\out[22] (net_65[15]), .\out[23]
- (net_65[14]), .\out[24] (net_65[13]), .\out[25] (net_65[12]), .\out[26]
- (net_65[11]), .\out[27] (net_65[10]), .\out[28] (net_65[9]), .\out[29]
- (net_65[8]), .\out[30] (net_65[7]), .\out[31] (net_65[6]), .\out[32]
- (net_65[5]), .\out[33] (net_65[4]), .\out[34] (net_65[3]), .\out[35]
- (net_65[2]), .\out[36] (net_65[1]), .\out[37] (net_65[0]),
- .out_1(net_65[18:18]), .succ(net_41), .sic(sic[1:9]), .sid(sid[1:9]),
- .sir(sir[1:9]), .soc({net_3[8], soc[2], soc[3], soc[4], soc[5]}),
- .sod(sod[1:5]), .sor({net_2[8], sor[2], sor[3], sor[4], sor[5]}));
- orangeTSMC090nm__wire90 wire90_0(.a(net_41));
-endmodule /* stageGroupsM__properStopper */
-
-module stageGroupsM__fillDrainCount(ain, ain_TT_, fin, in, pred, aout,
- aout_TT_, fout, out, succ, sic, sid, sir, soc, sod, sor);
- input [14:1] ain;
- input ain_TT_;
- input fin;
- input [37:1] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output fout;
- output [37:1] out;
- output succ;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_48, net_53;
- wire [8:8] net_61;
-
- countersL__instructionCount instruct_0(.cin(net_53), .count(net_48),
- .fin(fin), .fout(fout), .sid({net_61[8], sod[2], sod[3], sod[4], sod[5],
- sid[6], sid[7], sid[8], sid[9]}), .sod(sod[1:1]));
- stageGroupsM__properStopper properSt_1(.ain(ain[14:1]), .ain_TT_(ain_TT_),
- .in(in[37:1]), .pred(pred), .aout(aout[14:1]), .aout_TT_(aout_TT_),
- .extra(net_48), .fire(net_53), .out(out[37:1]), .succ(succ),
- .sic(sic[1:9]), .sid(sid[1:9]), .sir(sir[1:9]), .soc(soc[1:5]),
- .sod({net_61[8], sod[2], sod[3], sod[4], sod[5]}), .sor(sor[1:5]));
- orangeTSMC090nm__wire90 wire90_1(.a(net_48));
-endmodule /* stageGroupsM__fillDrainCount */
-
-module scanM__scanCap(si);
- inout [4:9] si;
-
-endmodule /* scanM__scanCap */
-
-module latchPartsK__latchPointT(hcl, in, x_F_, x_T_);
- input hcl;
- input [1:1] in;
- output x_F_;
- output x_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- orangeTSMC090nm__NMOSx PMOSx_0(.g(hcl), .d(in[1]), .s(x_T_));
- orangeTSMC090nm__NMOSx PMOSx_1(.g(hcl), .d(net_8), .s(x_F_));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_8, in[1]);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* latchPartsK__latchPointT */
-
-module latchesK__raw1inLatchT(hcl_A_, inA, out_T_);
- input hcl_A_;
- input [1:1] inA;
- output out_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_7;
-
- latchPartsK__latchKeep latchFlo_0(.out_B_(out_T_), .out_s_(net_7));
- latchPartsK__latchPointT latchPoi_0(.hcl(hcl_A_), .in(inA[1:1]),
- .x_F_(net_7), .x_T_(out_T_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_7));
-endmodule /* latchesK__raw1inLatchT */
-
-module latchesK__latch1in20B(hcl, in, out);
- input hcl;
- input [1:1] in;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_23;
-
- latchesK__raw1inLatchT hi2inLat_0(.hcl_A_(hcl), .inA(in[1:1]),
- .out_T_(net_18));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out[1], net_23);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_23, net_18);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_23));
-endmodule /* latchesK__latch1in20B */
-
-module registersM__addr1in20Bx7(ain, fire, aout);
- input [1:7] ain;
- input fire;
- output [1:7] aout;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in20B lat_1_(.hcl(fire), .in({ain[1]}), .out({aout[1]}));
- latchesK__latch1in20B lat_2_(.hcl(fire), .in({ain[2]}), .out({aout[2]}));
- latchesK__latch1in20B lat_3_(.hcl(fire), .in({ain[3]}), .out({aout[3]}));
- latchesK__latch1in20B lat_4_(.hcl(fire), .in({ain[4]}), .out({aout[4]}));
- latchesK__latch1in20B lat_5_(.hcl(fire), .in({ain[5]}), .out({aout[5]}));
- latchesK__latch1in20B lat_6_(.hcl(fire), .in({ain[6]}), .out({aout[6]}));
- latchesK__latch1in20B lat_7_(.hcl(fire), .in({ain[7]}), .out({aout[7]}));
-endmodule /* registersM__addr1in20Bx7 */
-
-module registersM__addr1in20Bx15(ain, ain_TT_, fire, aout, aout_TT_);
- input [1:14] ain;
- input ain_TT_;
- input fire;
- output [1:14] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- registersM__addr1in20Bx7 addr1in2_1(.ain(ain[8:14]), .fire(fire),
- .aout(aout[8:14]));
- registersM__addr1in20Bx7 addr1in2_2(.ain(ain[1:7]), .fire(fire),
- .aout(aout[1:7]));
- latchesK__latch1in20B latch1in_1(.hcl(fire), .in({ain_TT_}),
- .out({aout_TT_}));
- orangeTSMC090nm__wire90 wire90_0(.a(fire));
- orangeTSMC090nm__wire90 wire90_1(.a(fire));
-endmodule /* registersM__addr1in20Bx15 */
-
-module registersM__ins1in20Bx18(hcl, in, out);
- input hcl;
- input [1:18] in;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in20B lx_1_(.hcl(hcl), .in({in[1]}), .out({out[1]}));
- latchesK__latch1in20B lx_2_(.hcl(hcl), .in({in[2]}), .out({out[2]}));
- latchesK__latch1in20B lx_3_(.hcl(hcl), .in({in[3]}), .out({out[3]}));
- latchesK__latch1in20B lx_4_(.hcl(hcl), .in({in[4]}), .out({out[4]}));
- latchesK__latch1in20B lx_5_(.hcl(hcl), .in({in[5]}), .out({out[5]}));
- latchesK__latch1in20B lx_6_(.hcl(hcl), .in({in[6]}), .out({out[6]}));
- latchesK__latch1in20B lx_7_(.hcl(hcl), .in({in[7]}), .out({out[7]}));
- latchesK__latch1in20B lx_8_(.hcl(hcl), .in({in[8]}), .out({out[8]}));
- latchesK__latch1in20B lx_9_(.hcl(hcl), .in({in[9]}), .out({out[9]}));
- latchesK__latch1in20B lx_10_(.hcl(hcl), .in({in[10]}), .out({out[10]}));
- latchesK__latch1in20B lx_11_(.hcl(hcl), .in({in[11]}), .out({out[11]}));
- latchesK__latch1in20B lx_12_(.hcl(hcl), .in({in[12]}), .out({out[12]}));
- latchesK__latch1in20B lx_13_(.hcl(hcl), .in({in[13]}), .out({out[13]}));
- latchesK__latch1in20B lx_14_(.hcl(hcl), .in({in[14]}), .out({out[14]}));
- latchesK__latch1in20B lx_15_(.hcl(hcl), .in({in[15]}), .out({out[15]}));
- latchesK__latch1in20B lx_16_(.hcl(hcl), .in({in[16]}), .out({out[16]}));
- latchesK__latch1in20B lx_17_(.hcl(hcl), .in({in[17]}), .out({out[17]}));
- latchesK__latch1in20B lx_18_(.hcl(hcl), .in({in[18]}), .out({out[18]}));
-endmodule /* registersM__ins1in20Bx18 */
-
-module registersM__data1in20Bx37(in, take, out);
- input [1:37] in;
- input take;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__ins1in20Bx18 ins1in20_0(.hcl(take), .in(in[20:37]),
- .out(out[20:37]));
- registersM__ins1in20Bx18 ins1in20_1(.hcl(take), .in(in[1:18]),
- .out(out[1:18]));
- latchesK__latch1in20B latch1in_1(.hcl(take), .in({in[19]}),
- .out({out[19]}));
- orangeTSMC090nm__wire90 wire90_2(.a(take));
- orangeTSMC090nm__wire90 wire90_3(.a(take));
-endmodule /* registersM__data1in20Bx37 */
-
-module driversM__predDri20wMC(in, mc, pred);
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- redFive__pms3 pms3_0(.g(net_145), .g2(in), .g3(mc), .d(pred));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
-endmodule /* driversM__predDri20wMC */
-
-module redFive__pms1(g, d);
- input g;
- output d;
-
- supply1 vdd;
- orangeTSMC090nm__PMOSx PMOS_0(.g(g), .d(d), .s(vdd));
-endmodule /* redFive__pms1 */
-
-module driversM__sucDri20(in, succ);
- input in;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_109, net_94;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_94, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_109, in);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_94), .g2(net_109), .d(succ));
- redFive__pms1 pms1_0(.g(net_109), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_94));
- orangeTSMC090nm__wire90 wire90_1(.a(net_109));
-endmodule /* driversM__sucDri20 */
-
-module gaspM__gaspWeak(mc, pred, tok, fire, s, succ, take);
- input mc;
- input pred;
- input tok;
- output fire;
- output [1:1] s;
- output succ;
- output take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- centersJ__ctrAND2in100LT ctrAND2i_0(.inA(net_8), .inB(succ), .out(fire));
- driversM__dataDriver60 dataDriv_0(.inA(tok), .inB(fire), .out(take));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_8, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_8);
- // end Verilog_template
- driversM__predDri20wMC predDri2_0(.in(fire), .mc(mc), .pred(pred));
- driversM__sucDri20 sucDri20_0(.in(fire), .succ(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
- orangeTSMC090nm__wire90 wire90_1(.a(fire));
-endmodule /* gaspM__gaspWeak */
-
-module scanM__scanEx1(dIn, sir, sor);
- input [1:1] dIn;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- scanM__scanCellE scanCell_1(.dIn(dIn[1:1]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(sir[1]), .sout(sor[1]));
-endmodule /* scanM__scanEx1 */
-
-module stagesM__weakStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ,
- sir, sor);
- input [14:1] ain;
- input ain_TT_;
- input [1:37] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output [1:37] out;
- output succ;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_39, net_47, net_59;
-
- registersM__addr1in20Bx15 addr1in2_0(.ain({ain[1], ain[2], ain[3], ain[4],
- ain[5], ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12],
- ain[13], ain[14]}), .ain_TT_(ain_TT_), .fire(net_59), .aout({aout[1],
- aout[2], aout[3], aout[4], aout[5], aout[6], aout[7], aout[8], aout[9],
- aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- registersM__data1in20Bx37 data1in2_0(.in(in[1:37]), .take(net_47),
- .out(out[1:37]));
- gaspM__gaspWeak gaspWeak_0(.mc(sir[9]), .pred(pred), .tok(ain_TT_),
- .fire(net_59), .s({net_39}), .succ(succ), .take(net_47));
- scanM__scanEx1 scanEx1_0(.dIn({net_39}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
-endmodule /* stagesM__weakStage */
-
-module stageGroupsM__upDown8weak(ainD, ainD_TT_, ainU, ainU_TT_, inD, inU,
- predD, predU, aoutD, aoutD_TT_, aoutU, aoutU_TT_, outD, outU, succD,
- succU, sir, sor);
- input [14:1] ainD;
- input ainD_TT_;
- input [14:1] ainU;
- input ainU_TT_;
- input [37:1] inD;
- input [37:1] inU;
- input predD;
- input predU;
- output [14:1] aoutD;
- output aoutD_TT_;
- output [14:1] aoutU;
- output aoutU_TT_;
- output [37:1] outD;
- output [37:1] outU;
- output succD;
- output succU;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_28, net_43, net_50, net_52, net_62, net_64;
- wire [8:8] net_117;
- wire [8:8] net_120;
- wire [8:8] net_123;
- wire [8:8] net_126;
- wire [8:8] net_129;
- wire [8:8] net_132;
- wire [8:8] net_135;
- wire [51:0] net_189;
- wire [51:0] net_190;
- wire [51:0] net_191;
- wire [51:0] net_192;
- wire [51:0] net_193;
- wire [51:0] net_194;
-
- stagesM__weakStage weakStag_18(.ain(ainU[14:1]), .ain_TT_(ainU_TT_),
- .in({inU[1], inU[2], inU[3], inU[4], inU[5], inU[6], inU[7], inU[8],
- inU[9], inU[10], inU[11], inU[12], inU[13], inU[14], inU[15], inU[16],
- inU[17], inU[18], inU[19], inU[20], inU[21], inU[22], inU[23], inU[24],
- inU[25], inU[26], inU[27], inU[28], inU[29], inU[30], inU[31], inU[32],
- inU[33], inU[34], inU[35], inU[36], inU[37]}), .pred(predU),
- .aout({net_189[37], net_189[38], net_189[39], net_189[40], net_189[41],
- net_189[42], net_189[43], net_189[44], net_189[45], net_189[46],
- net_189[47], net_189[48], net_189[49], net_189[50]}),
- .aout_TT_(net_189[51]), .out({net_189[36], net_189[35], net_189[34],
- net_189[33], net_189[32], net_189[31], net_189[30], net_189[29],
- net_189[28], net_189[27], net_189[26], net_189[25], net_189[24],
- net_189[23], net_189[22], net_189[21], net_189[20], net_189[19],
- net_189[18], net_189[17], net_189[16], net_189[15], net_189[14],
- net_189[13], net_189[12], net_189[11], net_189[10], net_189[9],
- net_189[8], net_189[7], net_189[6], net_189[5], net_189[4], net_189[3],
- net_189[2], net_189[1], net_189[0]}), .succ(net_28), .sir(sir[1:9]),
- .sor({net_117[8]}));
- stagesM__weakStage weakStag_19(.ain({net_189[37], net_189[38], net_189[39],
- net_189[40], net_189[41], net_189[42], net_189[43], net_189[44],
- net_189[45], net_189[46], net_189[47], net_189[48], net_189[49],
- net_189[50]}), .ain_TT_(net_189[51]), .in({net_189[36], net_189[35],
- net_189[34], net_189[33], net_189[32], net_189[31], net_189[30],
- net_189[29], net_189[28], net_189[27], net_189[26], net_189[25],
- net_189[24], net_189[23], net_189[22], net_189[21], net_189[20],
- net_189[19], net_189[18], net_189[17], net_189[16], net_189[15],
- net_189[14], net_189[13], net_189[12], net_189[11], net_189[10],
- net_189[9], net_189[8], net_189[7], net_189[6], net_189[5], net_189[4],
- net_189[3], net_189[2], net_189[1], net_189[0]}), .pred(net_28),
- .aout({net_190[37], net_190[38], net_190[39], net_190[40], net_190[41],
- net_190[42], net_190[43], net_190[44], net_190[45], net_190[46],
- net_190[47], net_190[48], net_190[49], net_190[50]}),
- .aout_TT_(net_190[51]), .out({net_190[36], net_190[35], net_190[34],
- net_190[33], net_190[32], net_190[31], net_190[30], net_190[29],
- net_190[28], net_190[27], net_190[26], net_190[25], net_190[24],
- net_190[23], net_190[22], net_190[21], net_190[20], net_190[19],
- net_190[18], net_190[17], net_190[16], net_190[15], net_190[14],
- net_190[13], net_190[12], net_190[11], net_190[10], net_190[9],
- net_190[8], net_190[7], net_190[6], net_190[5], net_190[4], net_190[3],
- net_190[2], net_190[1], net_190[0]}), .succ(net_62), .sir({net_120[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_123[8]}));
- stagesM__weakStage weakStag_20(.ain({net_190[37], net_190[38], net_190[39],
- net_190[40], net_190[41], net_190[42], net_190[43], net_190[44],
- net_190[45], net_190[46], net_190[47], net_190[48], net_190[49],
- net_190[50]}), .ain_TT_(net_190[51]), .in({net_190[36], net_190[35],
- net_190[34], net_190[33], net_190[32], net_190[31], net_190[30],
- net_190[29], net_190[28], net_190[27], net_190[26], net_190[25],
- net_190[24], net_190[23], net_190[22], net_190[21], net_190[20],
- net_190[19], net_190[18], net_190[17], net_190[16], net_190[15],
- net_190[14], net_190[13], net_190[12], net_190[11], net_190[10],
- net_190[9], net_190[8], net_190[7], net_190[6], net_190[5], net_190[4],
- net_190[3], net_190[2], net_190[1], net_190[0]}), .pred(net_62),
- .aout({net_191[37], net_191[38], net_191[39], net_191[40], net_191[41],
- net_191[42], net_191[43], net_191[44], net_191[45], net_191[46],
- net_191[47], net_191[48], net_191[49], net_191[50]}),
- .aout_TT_(net_191[51]), .out({net_191[36], net_191[35], net_191[34],
- net_191[33], net_191[32], net_191[31], net_191[30], net_191[29],
- net_191[28], net_191[27], net_191[26], net_191[25], net_191[24],
- net_191[23], net_191[22], net_191[21], net_191[20], net_191[19],
- net_191[18], net_191[17], net_191[16], net_191[15], net_191[14],
- net_191[13], net_191[12], net_191[11], net_191[10], net_191[9],
- net_191[8], net_191[7], net_191[6], net_191[5], net_191[4], net_191[3],
- net_191[2], net_191[1], net_191[0]}), .succ(net_64), .sir({net_126[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_129[8]}));
- stagesM__weakStage weakStag_21(.ain({net_191[37], net_191[38], net_191[39],
- net_191[40], net_191[41], net_191[42], net_191[43], net_191[44],
- net_191[45], net_191[46], net_191[47], net_191[48], net_191[49],
- net_191[50]}), .ain_TT_(net_191[51]), .in({net_191[36], net_191[35],
- net_191[34], net_191[33], net_191[32], net_191[31], net_191[30],
- net_191[29], net_191[28], net_191[27], net_191[26], net_191[25],
- net_191[24], net_191[23], net_191[22], net_191[21], net_191[20],
- net_191[19], net_191[18], net_191[17], net_191[16], net_191[15],
- net_191[14], net_191[13], net_191[12], net_191[11], net_191[10],
- net_191[9], net_191[8], net_191[7], net_191[6], net_191[5], net_191[4],
- net_191[3], net_191[2], net_191[1], net_191[0]}), .pred(net_64),
- .aout(aoutU[14:1]), .aout_TT_(aoutU_TT_), .out({outU[1], outU[2],
- outU[3], outU[4], outU[5], outU[6], outU[7], outU[8], outU[9], outU[10],
- outU[11], outU[12], outU[13], outU[14], outU[15], outU[16], outU[17],
- outU[18], outU[19], outU[20], outU[21], outU[22], outU[23], outU[24],
- outU[25], outU[26], outU[27], outU[28], outU[29], outU[30], outU[31],
- outU[32], outU[33], outU[34], outU[35], outU[36], outU[37]}),
- .succ(succU), .sir({net_132[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .sor({net_135[8]}));
- stagesM__weakStage weakStag_22(.ain({net_192[37], net_192[38], net_192[39],
- net_192[40], net_192[41], net_192[42], net_192[43], net_192[44],
- net_192[45], net_192[46], net_192[47], net_192[48], net_192[49],
- net_192[50]}), .ain_TT_(net_192[51]), .in({net_192[36], net_192[35],
- net_192[34], net_192[33], net_192[32], net_192[31], net_192[30],
- net_192[29], net_192[28], net_192[27], net_192[26], net_192[25],
- net_192[24], net_192[23], net_192[22], net_192[21], net_192[20],
- net_192[19], net_192[18], net_192[17], net_192[16], net_192[15],
- net_192[14], net_192[13], net_192[12], net_192[11], net_192[10],
- net_192[9], net_192[8], net_192[7], net_192[6], net_192[5], net_192[4],
- net_192[3], net_192[2], net_192[1], net_192[0]}), .pred(net_50),
- .aout(aoutD[14:1]), .aout_TT_(aoutD_TT_), .out({outD[1], outD[2],
- outD[3], outD[4], outD[5], outD[6], outD[7], outD[8], outD[9], outD[10],
- outD[11], outD[12], outD[13], outD[14], outD[15], outD[16], outD[17],
- outD[18], outD[19], outD[20], outD[21], outD[22], outD[23], outD[24],
- outD[25], outD[26], outD[27], outD[28], outD[29], outD[30], outD[31],
- outD[32], outD[33], outD[34], outD[35], outD[36], outD[37]}),
- .succ(succD), .sir({net_117[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .sor({net_120[8]}));
- stagesM__weakStage weakStag_23(.ain({net_193[37], net_193[38], net_193[39],
- net_193[40], net_193[41], net_193[42], net_193[43], net_193[44],
- net_193[45], net_193[46], net_193[47], net_193[48], net_193[49],
- net_193[50]}), .ain_TT_(net_193[51]), .in({net_193[36], net_193[35],
- net_193[34], net_193[33], net_193[32], net_193[31], net_193[30],
- net_193[29], net_193[28], net_193[27], net_193[26], net_193[25],
- net_193[24], net_193[23], net_193[22], net_193[21], net_193[20],
- net_193[19], net_193[18], net_193[17], net_193[16], net_193[15],
- net_193[14], net_193[13], net_193[12], net_193[11], net_193[10],
- net_193[9], net_193[8], net_193[7], net_193[6], net_193[5], net_193[4],
- net_193[3], net_193[2], net_193[1], net_193[0]}), .pred(net_43),
- .aout({net_192[37], net_192[38], net_192[39], net_192[40], net_192[41],
- net_192[42], net_192[43], net_192[44], net_192[45], net_192[46],
- net_192[47], net_192[48], net_192[49], net_192[50]}),
- .aout_TT_(net_192[51]), .out({net_192[36], net_192[35], net_192[34],
- net_192[33], net_192[32], net_192[31], net_192[30], net_192[29],
- net_192[28], net_192[27], net_192[26], net_192[25], net_192[24],
- net_192[23], net_192[22], net_192[21], net_192[20], net_192[19],
- net_192[18], net_192[17], net_192[16], net_192[15], net_192[14],
- net_192[13], net_192[12], net_192[11], net_192[10], net_192[9],
- net_192[8], net_192[7], net_192[6], net_192[5], net_192[4], net_192[3],
- net_192[2], net_192[1], net_192[0]}), .succ(net_50), .sir({net_123[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_126[8]}));
- stagesM__weakStage weakStag_24(.ain({net_194[37], net_194[38], net_194[39],
- net_194[40], net_194[41], net_194[42], net_194[43], net_194[44],
- net_194[45], net_194[46], net_194[47], net_194[48], net_194[49],
- net_194[50]}), .ain_TT_(net_194[51]), .in({net_194[36], net_194[35],
- net_194[34], net_194[33], net_194[32], net_194[31], net_194[30],
- net_194[29], net_194[28], net_194[27], net_194[26], net_194[25],
- net_194[24], net_194[23], net_194[22], net_194[21], net_194[20],
- net_194[19], net_194[18], net_194[17], net_194[16], net_194[15],
- net_194[14], net_194[13], net_194[12], net_194[11], net_194[10],
- net_194[9], net_194[8], net_194[7], net_194[6], net_194[5], net_194[4],
- net_194[3], net_194[2], net_194[1], net_194[0]}), .pred(net_52),
- .aout({net_193[37], net_193[38], net_193[39], net_193[40], net_193[41],
- net_193[42], net_193[43], net_193[44], net_193[45], net_193[46],
- net_193[47], net_193[48], net_193[49], net_193[50]}),
- .aout_TT_(net_193[51]), .out({net_193[36], net_193[35], net_193[34],
- net_193[33], net_193[32], net_193[31], net_193[30], net_193[29],
- net_193[28], net_193[27], net_193[26], net_193[25], net_193[24],
- net_193[23], net_193[22], net_193[21], net_193[20], net_193[19],
- net_193[18], net_193[17], net_193[16], net_193[15], net_193[14],
- net_193[13], net_193[12], net_193[11], net_193[10], net_193[9],
- net_193[8], net_193[7], net_193[6], net_193[5], net_193[4], net_193[3],
- net_193[2], net_193[1], net_193[0]}), .succ(net_43), .sir({net_129[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_132[8]}));
- stagesM__weakStage weakStag_25(.ain(ainD[14:1]), .ain_TT_(ainD_TT_),
- .in({inD[1], inD[2], inD[3], inD[4], inD[5], inD[6], inD[7], inD[8],
- inD[9], inD[10], inD[11], inD[12], inD[13], inD[14], inD[15], inD[16],
- inD[17], inD[18], inD[19], inD[20], inD[21], inD[22], inD[23], inD[24],
- inD[25], inD[26], inD[27], inD[28], inD[29], inD[30], inD[31], inD[32],
- inD[33], inD[34], inD[35], inD[36], inD[37]}), .pred(predD),
- .aout({net_194[37], net_194[38], net_194[39], net_194[40], net_194[41],
- net_194[42], net_194[43], net_194[44], net_194[45], net_194[46],
- net_194[47], net_194[48], net_194[49], net_194[50]}),
- .aout_TT_(net_194[51]), .out({net_194[36], net_194[35], net_194[34],
- net_194[33], net_194[32], net_194[31], net_194[30], net_194[29],
- net_194[28], net_194[27], net_194[26], net_194[25], net_194[24],
- net_194[23], net_194[22], net_194[21], net_194[20], net_194[19],
- net_194[18], net_194[17], net_194[16], net_194[15], net_194[14],
- net_194[13], net_194[12], net_194[11], net_194[10], net_194[9],
- net_194[8], net_194[7], net_194[6], net_194[5], net_194[4], net_194[3],
- net_194[2], net_194[1], net_194[0]}), .succ(net_52), .sir({net_135[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_1(.a(net_43));
- orangeTSMC090nm__wire90 wire90_2(.a(net_28));
- orangeTSMC090nm__wire90 wire90_3(.a(net_62));
- orangeTSMC090nm__wire90 wire90_4(.a(net_64));
- orangeTSMC090nm__wire90 wire90_5(.a(net_50));
- orangeTSMC090nm__wire90 wire90_6(.a(net_52));
-endmodule /* stageGroupsM__upDown8weak */
-
-module stageGroupsM__northFifo(ainU, ainU_TT_, fin, inU, predU, aoutD,
- aoutD_TT_, fout, outD, succD, sic, sid, sir);
- input [14:1] ainU;
- input ainU_TT_;
- input fin;
- input [37:1] inU;
- input predU;
- output [14:1] aoutD;
- output aoutD_TT_;
- output fout;
- output [37:1] outD;
- output succD;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
-
- supply1 vdd;
- supply0 gnd;
- wire net_229, net_263;
- wire [5:4] net_235;
- wire [5:4] net_236;
- wire [8:8] net_254;
- wire [51:0] net_256;
- wire [51:0] net_259;
- wire [5:4] net_262;
-
- stageGroupsM__fillDrainCount fillDrai_1(.ain({net_256[37], net_256[38],
- net_256[39], net_256[40], net_256[41], net_256[42], net_256[43],
- net_256[44], net_256[45], net_256[46], net_256[47], net_256[48],
- net_256[49], net_256[50]}), .ain_TT_(net_256[51]), .fin(fin),
- .in({net_256[0], net_256[1], net_256[2], net_256[3], net_256[4],
- net_256[5], net_256[6], net_256[7], net_256[8], net_256[9], net_256[10],
- net_256[11], net_256[12], net_256[13], net_256[14], net_256[15],
- net_256[16], net_256[17], net_256[18], net_256[19], net_256[20],
- net_256[21], net_256[22], net_256[23], net_256[24], net_256[25],
- net_256[26], net_256[27], net_256[28], net_256[29], net_256[30],
- net_256[31], net_256[32], net_256[33], net_256[34], net_256[35],
- net_256[36]}), .pred(net_263), .aout({net_259[37], net_259[38],
- net_259[39], net_259[40], net_259[41], net_259[42], net_259[43],
- net_259[44], net_259[45], net_259[46], net_259[47], net_259[48],
- net_259[49], net_259[50]}), .aout_TT_(net_259[51]), .fout(fout),
- .out({net_259[0], net_259[1], net_259[2], net_259[3], net_259[4],
- net_259[5], net_259[6], net_259[7], net_259[8], net_259[9], net_259[10],
- net_259[11], net_259[12], net_259[13], net_259[14], net_259[15],
- net_259[16], net_259[17], net_259[18], net_259[19], net_259[20],
- net_259[21], net_259[22], net_259[23], net_259[24], net_259[25],
- net_259[26], net_259[27], net_259[28], net_259[29], net_259[30],
- net_259[31], net_259[32], net_259[33], net_259[34], net_259[35],
- net_259[36]}), .succ(net_229), .sic(sic[1:9]), .sid(sid[1:9]),
- .sir({net_254[8], sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8],
- sir[9]}), .soc({sic[8], sic[7], sic[6], net_236[5], net_236[4]}),
- .sod({sid[8], sid[7], sid[6], net_235[5], net_235[4]}), .sor({sir[8],
- sir[7], sir[6], net_262[5], net_262[4]}));
- scanM__scanCap scanCap_5(.si({net_235[5], net_235[4], sid[6], sid[7], sid[8],
- sid[9]}));
- scanM__scanCap scanCap_6(.si({net_236[5], net_236[4], sic[6], sic[7], sic[8],
- sic[9]}));
- scanM__scanCap scanCap_7(.si({net_262[5], net_262[4], sir[6], sir[7], sir[8],
- sir[9]}));
- stageGroupsM__upDown8weak upDown8w_2(.ainD({net_259[37], net_259[38],
- net_259[39], net_259[40], net_259[41], net_259[42], net_259[43],
- net_259[44], net_259[45], net_259[46], net_259[47], net_259[48],
- net_259[49], net_259[50]}), .ainD_TT_(net_259[51]), .ainU(ainU[14:1]),
- .ainU_TT_(ainU_TT_), .inD({net_259[0], net_259[1], net_259[2],
- net_259[3], net_259[4], net_259[5], net_259[6], net_259[7], net_259[8],
- net_259[9], net_259[10], net_259[11], net_259[12], net_259[13],
- net_259[14], net_259[15], net_259[16], net_259[17], net_259[18],
- net_259[19], net_259[20], net_259[21], net_259[22], net_259[23],
- net_259[24], net_259[25], net_259[26], net_259[27], net_259[28],
- net_259[29], net_259[30], net_259[31], net_259[32], net_259[33],
- net_259[34], net_259[35], net_259[36]}), .inU(inU[37:1]),
- .predD(net_229), .predU(predU), .aoutD(aoutD[14:1]),
- .aoutD_TT_(aoutD_TT_), .aoutU({net_256[37], net_256[38], net_256[39],
- net_256[40], net_256[41], net_256[42], net_256[43], net_256[44],
- net_256[45], net_256[46], net_256[47], net_256[48], net_256[49],
- net_256[50]}), .aoutU_TT_(net_256[51]), .outD(outD[37:1]),
- .outU({net_256[0], net_256[1], net_256[2], net_256[3], net_256[4],
- net_256[5], net_256[6], net_256[7], net_256[8], net_256[9], net_256[10],
- net_256[11], net_256[12], net_256[13], net_256[14], net_256[15],
- net_256[16], net_256[17], net_256[18], net_256[19], net_256[20],
- net_256[21], net_256[22], net_256[23], net_256[24], net_256[25],
- net_256[26], net_256[27], net_256[28], net_256[29], net_256[30],
- net_256[31], net_256[32], net_256[33], net_256[34], net_256[35],
- net_256[36]}), .succD(succD), .succU(net_263), .sir(sir[1:9]),
- .sor({net_254[8]}));
- orangeTSMC090nm__wire90 wire90_6(.a(net_229));
- orangeTSMC090nm__wire90 wire90_18(.a(net_263));
-endmodule /* stageGroupsM__northFifo */
-
-module redFive__nor2n(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nor2{sch}*/
- nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nor2n */
-
-module centersJ__ctrAND4in30(inA, inB, inC, inD, out);
- input inA;
- input inB;
- input inC;
- input inD;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_3, net_43, net_58;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (out, net_3);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_3, net_43, net_58);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_1 (net_58, inA, inB);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(inD), .inb(inC), .out(net_43));
- orangeTSMC090nm__wire90 wire90_0(.a(net_43));
- orangeTSMC090nm__wire90 wire90_1(.a(net_3));
- orangeTSMC090nm__wire90 wire90_2(.a(net_58));
-endmodule /* centersJ__ctrAND4in30 */
-
-module latchesK__rsLatchA(mc, reset, set, out, outBar);
- input mc;
- input reset;
- input set;
- output out;
- output outBar;
-
- supply1 vdd;
- supply0 gnd;
- wire net_177, net_188;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(reset), .d(net_188), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(net_188), .s(gnd));
- orangeTSMC090nm__PMOSx PMOSx_3(.g(net_177), .d(net_188), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (outBar, net_188);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_177, set);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (out, outBar);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(outBar), .g2(net_177), .d(net_188));
- redFive__pms3 pms3_0(.g(mc), .g2(outBar), .g3(reset), .d(net_188));
- orangeTSMC090nm__wire90 wire90_0(.a(net_177));
- orangeTSMC090nm__wire90 wire90_1(.a(net_188));
-endmodule /* latchesK__rsLatchA */
-
-module driversM__sucORdri20(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_71), .g2(net_51), .d(succ));
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_0 (net_51, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucORdri20 */
-
-module gaspM__anAltEnd(mc, predA, predB, fire_A_, fire_B_, s, succ);
- input mc;
- input predA;
- input predB;
- output fire_A_;
- output fire_B_;
- output [1:3] s;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_1040, net_1082, net_822, net_824;
-
- centersJ__ctrAND4in30 ctrAND4i_2(.inA(net_822), .inB(succ), .inC(net_1040),
- .inD(fire_B_), .out(fire_A_));
- centersJ__ctrAND4in30 ctrAND4i_3(.inA(net_824), .inB(succ), .inC(fire_A_),
- .inD(net_1082), .out(fire_B_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (s[1], net_822);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (s[3], net_824);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_822, predA);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (net_824, predB);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_7 (s[2], net_1040);
- // end Verilog_template
- driversM__predDri20wMC predDri2_0(.in(fire_A_), .mc(mc), .pred(predA));
- driversM__predDri20wMC predDri2_1(.in(fire_B_), .mc(mc), .pred(predB));
- latchesK__rsLatchA rsLatchA_1(.mc(mc), .reset(fire_B_), .set(fire_A_),
- .out(net_1040), .outBar(net_1082));
- driversM__sucORdri20 sucORdri_0(.inA(fire_A_), .inB(fire_B_), .succ(succ));
- orangeTSMC090nm__wire90 wire90_34(.a(net_824));
- orangeTSMC090nm__wire90 wire90_35(.a(net_822));
- orangeTSMC090nm__wire90 wire90_36(.a(net_1082));
- orangeTSMC090nm__wire90 wire90_37(.a(net_1040));
-endmodule /* gaspM__anAltEnd */
-
-module latchesK__latch2in20A(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_16;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(net_16));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (out[1], net_16);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_1(.a(net_16));
-endmodule /* latchesK__latch2in20A */
-
-module registersM__ins2in20Ax18(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:18] inA;
- input [1:18] inB;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in20A lx_1_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[1]}),
- .inB({inB[1]}), .out({out[1]}));
- latchesK__latch2in20A lx_2_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[2]}),
- .inB({inB[2]}), .out({out[2]}));
- latchesK__latch2in20A lx_3_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[3]}),
- .inB({inB[3]}), .out({out[3]}));
- latchesK__latch2in20A lx_4_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[4]}),
- .inB({inB[4]}), .out({out[4]}));
- latchesK__latch2in20A lx_5_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[5]}),
- .inB({inB[5]}), .out({out[5]}));
- latchesK__latch2in20A lx_6_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[6]}),
- .inB({inB[6]}), .out({out[6]}));
- latchesK__latch2in20A lx_7_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[7]}),
- .inB({inB[7]}), .out({out[7]}));
- latchesK__latch2in20A lx_8_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[8]}),
- .inB({inB[8]}), .out({out[8]}));
- latchesK__latch2in20A lx_9_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[9]}),
- .inB({inB[9]}), .out({out[9]}));
- latchesK__latch2in20A lx_10_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[10]}), .inB({inB[10]}), .out({out[10]}));
- latchesK__latch2in20A lx_11_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[11]}), .inB({inB[11]}), .out({out[11]}));
- latchesK__latch2in20A lx_12_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[12]}), .inB({inB[12]}), .out({out[12]}));
- latchesK__latch2in20A lx_13_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[13]}), .inB({inB[13]}), .out({out[13]}));
- latchesK__latch2in20A lx_14_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[14]}), .inB({inB[14]}), .out({out[14]}));
- latchesK__latch2in20A lx_15_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[15]}), .inB({inB[15]}), .out({out[15]}));
- latchesK__latch2in20A lx_16_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[16]}), .inB({inB[16]}), .out({out[16]}));
- latchesK__latch2in20A lx_17_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[17]}), .inB({inB[17]}), .out({out[17]}));
- latchesK__latch2in20A lx_18_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[18]}), .inB({inB[18]}), .out({out[18]}));
-endmodule /* registersM__ins2in20Ax18 */
-
-module registersM__ins2in20Ax36(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:36] inA;
- input [1:36] inB;
- output [1:36] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__ins2in20Ax18 ins2in20_2(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[19:36]), .inB(inB[19:36]), .out(out[19:36]));
- registersM__ins2in20Ax18 ins2in20_3(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:18]), .inB(inB[1:18]), .out(out[1:18]));
- orangeTSMC090nm__wire90 wire90_0(.a(hcl_A_));
- orangeTSMC090nm__wire90 wire90_1(.a(hcl_A_));
- orangeTSMC090nm__wire90 wire90_2(.a(hcl_B_));
- orangeTSMC090nm__wire90 wire90_3(.a(hcl_B_));
-endmodule /* registersM__ins2in20Ax36 */
-
-module scanM__scanEx3(dIn, dIn_1, dIn_2, sir, sor);
- input [1:1] dIn;
- input [2:2] dIn_1;
- input [3:3] dIn_2;
- input [1:9] sir;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_26, net_45;
-
- scanM__scanCellE scanCell_1(.dIn(dIn[1:1]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(sir[1]), .sout(net_26));
- scanM__scanCellE scanCell_2(.dIn(dIn_1[2:2]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(net_26), .sout(net_45));
- scanM__scanCellE scanCell_3(.dIn(dIn_2[3:3]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(net_45), .sout(sor[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_26));
- orangeTSMC090nm__wire90 wire90_1(.a(net_45));
-endmodule /* scanM__scanEx3 */
-
-module stagesM__altEndDockStage(inA, inB, predA, predB, sir, out, sor, succ);
- input [1:36] inA;
- input [1:36] inB;
- input predA;
- input predB;
- input [1:9] sir;
- output [1:36] out;
- output [1:1] sor;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_A_, fire_B_, take_A_, take_B_;
- wire [1:3] s;
-
- gaspM__anAltEnd anAltEnd_1(.mc(sir[9]), .predA(predA), .predB(predB),
- .fire_A_(fire_A_), .fire_B_(fire_B_), .s(s[1:3]), .succ(succ));
- registersM__ins2in20Ax36 ins2in20_0(.hcl_A_(take_A_), .hcl_B_(take_B_),
- .inA(inA[1:36]), .inB(inB[1:36]), .out(out[1:36]));
- driversM__latchDriver60 latchDri_2(.in(fire_A_), .out(take_A_));
- driversM__latchDriver60 latchDri_3(.in(fire_B_), .out(take_B_));
- scanM__scanEx3 scanEx3_0(.dIn({s[1]}), .dIn_1({s[2]}), .dIn_2({s[3]}),
- .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- wiresL__tranCap tc_17_();
- wiresL__tranCap tc_18_();
- wiresL__tranCap tc_19_();
- wiresL__tranCap tc_20_();
- wiresL__tranCap tc_21_();
- orangeTSMC090nm__wire90 wire90_0(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_A_));
- orangeTSMC090nm__wire90 wire90_2(.a(take_B_));
- orangeTSMC090nm__wire90 wire90_3(.a(take_A_));
-endmodule /* stagesM__altEndDockStage */
-
-module centersJ__ctrAND4in30M(inA, inB, inC, inD, out, outM);
- input inA;
- input inB;
- input inC;
- input inD;
- output out;
- output outM;
-
- supply1 vdd;
- supply0 gnd;
- wire net_43, net_58;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (out, outM);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (outM, net_43, net_58);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_1 (net_58, inA, inB);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(inD), .inb(inC), .out(net_43));
- orangeTSMC090nm__wire90 wire90_0(.a(net_43));
- orangeTSMC090nm__wire90 wire90_2(.a(net_58));
-endmodule /* centersJ__ctrAND4in30M */
-
-module redFive__nand2n_sy(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nand2n_sy */
-
-module gaspM__anAltStart(mc, pred, fire_A_, fire_B_, s, succA, succB);
- input mc;
- input pred;
- output fire_A_;
- output fire_B_;
- output [1:2] s;
- output succA;
- output succB;
-
- supply1 vdd;
- supply0 gnd;
- wire net_143, net_410, net_422, net_634, net_905, net_909;
-
- centersJ__ctrAND4in30M ctrAND4i_1(.inA(net_634), .inB(succA), .inC(fire_B_),
- .inD(net_905), .out(fire_A_), .outM(net_410));
- centersJ__ctrAND4in30M ctrAND4i_3(.inA(net_634), .inB(succB), .inC(net_909),
- .inD(fire_A_), .out(fire_B_), .outM(net_143));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (s[1], net_634);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_634, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (s[2], net_905);
- // end Verilog_template
- redFive__nand2n_sy nand2n_s_0(.ina(net_143), .inb(net_410), .out(net_422));
- driversM__predDri20wMC predDri2_0(.in(net_422), .mc(mc), .pred(pred));
- latchesK__rsLatchA rsLatchA_1(.mc(mc), .reset(fire_B_), .set(fire_A_),
- .out(net_905), .outBar(net_909));
- driversM__sucDri20 sucDri20_0(.in(fire_A_), .succ(succA));
- driversM__sucDri20 sucDri20_1(.in(fire_B_), .succ(succB));
- orangeTSMC090nm__wire90 wire90_16(.a(net_410));
- orangeTSMC090nm__wire90 wire90_17(.a(net_143));
- orangeTSMC090nm__wire90 wire90_19(.a(net_905));
- orangeTSMC090nm__wire90 wire90_20(.a(net_422));
- orangeTSMC090nm__wire90 wire90_27(.a(net_909));
- orangeTSMC090nm__wire90 wire90_28(.a(net_634));
-endmodule /* gaspM__anAltStart */
-
-module registersM__ins1in20Bx36(hcl, in, out);
- input [1:1] hcl;
- input [1:36] in;
- output [1:36] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__ins1in20Bx18 ins1in20_0(.hcl(hcl[1]), .in(in[1:18]),
- .out(out[1:18]));
- registersM__ins1in20Bx18 ins1in20_1(.hcl(hcl[1]), .in(in[19:36]),
- .out(out[19:36]));
- orangeTSMC090nm__wire90 wire90_0(.a(hcl[1]));
- orangeTSMC090nm__wire90 wire90_1(.a(hcl[1]));
-endmodule /* registersM__ins1in20Bx36 */
-
-module stagesM__altStartDockStage(in, pred, sir, outA, outB, sor, succA,
- succB);
- input [1:36] in;
- input pred;
- input [1:9] sir;
- output [1:36] outA;
- output [1:36] outB;
- output [1:1] sor;
- output succA;
- output succB;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_A_, fire_B_, net_20, net_22;
- wire [1:0] net_48;
-
- gaspM__anAltStart anAltSta_1(.mc(sir[9]), .pred(pred), .fire_A_(fire_A_),
- .fire_B_(fire_B_), .s({net_48[1], net_48[0]}), .succA(succA),
- .succB(succB));
- registersM__ins1in20Bx36 ins1in20_0(.hcl({net_20}), .in(in[1:36]),
- .out(outA[1:36]));
- registersM__ins1in20Bx36 ins1in20_1(.hcl({net_22}), .in(in[1:36]),
- .out(outB[1:36]));
- driversM__latchDriver60 latchDri_2(.in(fire_A_), .out(net_20));
- driversM__latchDriver60 latchDri_3(.in(fire_B_), .out(net_22));
- scanM__scanEx2 scanEx2v_1(.dIn({net_48[1], net_48[0]}), .sir(sir[1:9]),
- .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- orangeTSMC090nm__wire90 wire90_0(.a(fire_A_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_2(.a(net_20));
- orangeTSMC090nm__wire90 wire90_3(.a(net_22));
-endmodule /* stagesM__altStartDockStage */
-
-module centersJ__ctrAND2in30(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_6, net_8;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (out, net_8);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (net_8, net_6);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_1 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_8));
-endmodule /* centersJ__ctrAND2in30 */
-
-module gaspM__aStage(mc, pred, fire, s, succ);
- input mc;
- input pred;
- output fire;
- output [1:1] s;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_494;
-
- centersJ__ctrAND2in30 ctrAND2i_4(.inA(net_494), .inB(succ), .out(fire));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (s[1], net_494);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_494, pred);
- // end Verilog_template
- driversM__predDri20wMC predDri2_1(.in(fire), .mc(mc), .pred(pred));
- driversM__sucDri20 sucDri20_1(.in(fire), .succ(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_494));
-endmodule /* gaspM__aStage */
-
-module stagesM__plainDockStage(in, pred, sir, out, sor, succ, take);
- input [1:36] in;
- input pred;
- input [1:9] sir;
- output [1:36] out;
- output [1:1] sor;
- output succ;
- output [1:1] take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_41;
- wire [1:1] fire;
-
- gaspM__aStage aStage_1(.mc(sir[9]), .pred(pred), .fire(fire[1]),
- .s({net_41}), .succ(succ));
- registersM__ins1in20Bx36 ins1in20_0(.hcl(take[1:1]), .in(in[1:36]),
- .out(out[1:36]));
- driversM__latchDriver60 latchDri_1(.in(fire[1]), .out(take[1]));
- scanM__scanEx1 scanEx1_0(.dIn({net_41}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- orangeTSMC090nm__wire90 wire90_1(.a(fire[1]));
-endmodule /* stagesM__plainDockStage */
-
-module stageGroupsM__dockWagNine(in, pred, sir, out, sor, succ, take);
- input [1:36] in;
- input pred;
- input [1:9] sir;
- output [1:36] out;
- output [1:1] sor;
- output succ;
- output [4:4] take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_105, net_107, net_109, net_111, net_58, net_60, net_64, net_69;
- wire [35:0] net_0;
- wire [35:0] net_1;
- wire [8:8] net_116;
- wire [8:8] net_125;
- wire [8:8] net_127;
- wire [8:8] net_128;
- wire [8:8] net_130;
- wire [8:8] net_134;
- wire [8:8] net_136;
- wire [35:0] net_16;
- wire [35:0] net_19;
- wire [35:0] net_2;
- wire [35:0] net_20;
- wire [35:0] net_21;
- wire [35:0] net_3;
- wire \take_1[6] ;
- wire \take_1[5] ;
- wire \take_1[3] ;
- wire \take_1[2] ;
- wire \take_1[1] ;
-
- stagesM__altEndDockStage altEndDo_0(.inA({net_16[35], net_16[34], net_16[33],
- net_16[32], net_16[31], net_16[30], net_16[29], net_16[28], net_16[27],
- net_16[26], net_16[25], net_16[24], net_16[23], net_16[22], net_16[21],
- net_16[20], net_16[19], net_16[18], net_16[17], net_16[16], net_16[15],
- net_16[14], net_16[13], net_16[12], net_16[11], net_16[10], net_16[9],
- net_16[8], net_16[7], net_16[6], net_16[5], net_16[4], net_16[3],
- net_16[2], net_16[1], net_16[0]}), .inB({net_19[35], net_19[34],
- net_19[33], net_19[32], net_19[31], net_19[30], net_19[29], net_19[28],
- net_19[27], net_19[26], net_19[25], net_19[24], net_19[23], net_19[22],
- net_19[21], net_19[20], net_19[19], net_19[18], net_19[17], net_19[16],
- net_19[15], net_19[14], net_19[13], net_19[12], net_19[11], net_19[10],
- net_19[9], net_19[8], net_19[7], net_19[6], net_19[5], net_19[4],
- net_19[3], net_19[2], net_19[1], net_19[0]}), .predA(net_69),
- .predB(net_58), .sir({net_134[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .out(out[1:36]), .sor(sor[1:1]), .succ(succ));
- stagesM__altStartDockStage altStart_0(.in(in[1:36]), .pred(pred),
- .sir(sir[1:9]), .outA({net_21[35], net_21[34], net_21[33], net_21[32],
- net_21[31], net_21[30], net_21[29], net_21[28], net_21[27], net_21[26],
- net_21[25], net_21[24], net_21[23], net_21[22], net_21[21], net_21[20],
- net_21[19], net_21[18], net_21[17], net_21[16], net_21[15], net_21[14],
- net_21[13], net_21[12], net_21[11], net_21[10], net_21[9], net_21[8],
- net_21[7], net_21[6], net_21[5], net_21[4], net_21[3], net_21[2],
- net_21[1], net_21[0]}), .outB({net_20[35], net_20[34], net_20[33],
- net_20[32], net_20[31], net_20[30], net_20[29], net_20[28], net_20[27],
- net_20[26], net_20[25], net_20[24], net_20[23], net_20[22], net_20[21],
- net_20[20], net_20[19], net_20[18], net_20[17], net_20[16], net_20[15],
- net_20[14], net_20[13], net_20[12], net_20[11], net_20[10], net_20[9],
- net_20[8], net_20[7], net_20[6], net_20[5], net_20[4], net_20[3],
- net_20[2], net_20[1], net_20[0]}), .sor({net_116[8]}), .succA(net_64),
- .succB(net_60));
- stagesM__plainDockStage plainDoc_0(.in({net_2[35], net_2[34], net_2[33],
- net_2[32], net_2[31], net_2[30], net_2[29], net_2[28], net_2[27],
- net_2[26], net_2[25], net_2[24], net_2[23], net_2[22], net_2[21],
- net_2[20], net_2[19], net_2[18], net_2[17], net_2[16], net_2[15],
- net_2[14], net_2[13], net_2[12], net_2[11], net_2[10], net_2[9],
- net_2[8], net_2[7], net_2[6], net_2[5], net_2[4], net_2[3], net_2[2],
- net_2[1], net_2[0]}), .pred(net_107), .sir({net_136[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_3[35],
- net_3[34], net_3[33], net_3[32], net_3[31], net_3[30], net_3[29],
- net_3[28], net_3[27], net_3[26], net_3[25], net_3[24], net_3[23],
- net_3[22], net_3[21], net_3[20], net_3[19], net_3[18], net_3[17],
- net_3[16], net_3[15], net_3[14], net_3[13], net_3[12], net_3[11],
- net_3[10], net_3[9], net_3[8], net_3[7], net_3[6], net_3[5], net_3[4],
- net_3[3], net_3[2], net_3[1], net_3[0]}), .sor({net_130[8]}),
- .succ(net_105), .take({ \take_1[5] }));
- stagesM__plainDockStage plainDoc_1(.in({net_20[35], net_20[34], net_20[33],
- net_20[32], net_20[31], net_20[30], net_20[29], net_20[28], net_20[27],
- net_20[26], net_20[25], net_20[24], net_20[23], net_20[22], net_20[21],
- net_20[20], net_20[19], net_20[18], net_20[17], net_20[16], net_20[15],
- net_20[14], net_20[13], net_20[12], net_20[11], net_20[10], net_20[9],
- net_20[8], net_20[7], net_20[6], net_20[5], net_20[4], net_20[3],
- net_20[2], net_20[1], net_20[0]}), .pred(net_60), .sir({net_125[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .out({net_2[35], net_2[34], net_2[33], net_2[32], net_2[31], net_2[30],
- net_2[29], net_2[28], net_2[27], net_2[26], net_2[25], net_2[24],
- net_2[23], net_2[22], net_2[21], net_2[20], net_2[19], net_2[18],
- net_2[17], net_2[16], net_2[15], net_2[14], net_2[13], net_2[12],
- net_2[11], net_2[10], net_2[9], net_2[8], net_2[7], net_2[6], net_2[5],
- net_2[4], net_2[3], net_2[2], net_2[1], net_2[0]}), .sor({net_136[8]}),
- .succ(net_107), .take(take[4:4]));
- stagesM__plainDockStage plainDoc_2(.in({net_3[35], net_3[34], net_3[33],
- net_3[32], net_3[31], net_3[30], net_3[29], net_3[28], net_3[27],
- net_3[26], net_3[25], net_3[24], net_3[23], net_3[22], net_3[21],
- net_3[20], net_3[19], net_3[18], net_3[17], net_3[16], net_3[15],
- net_3[14], net_3[13], net_3[12], net_3[11], net_3[10], net_3[9],
- net_3[8], net_3[7], net_3[6], net_3[5], net_3[4], net_3[3], net_3[2],
- net_3[1], net_3[0]}), .pred(net_105), .sir({net_130[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_19[35],
- net_19[34], net_19[33], net_19[32], net_19[31], net_19[30], net_19[29],
- net_19[28], net_19[27], net_19[26], net_19[25], net_19[24], net_19[23],
- net_19[22], net_19[21], net_19[20], net_19[19], net_19[18], net_19[17],
- net_19[16], net_19[15], net_19[14], net_19[13], net_19[12], net_19[11],
- net_19[10], net_19[9], net_19[8], net_19[7], net_19[6], net_19[5],
- net_19[4], net_19[3], net_19[2], net_19[1], net_19[0]}),
- .sor({net_134[8]}), .succ(net_58), .take({ \take_1[6] }));
- stagesM__plainDockStage plainDoc_3(.in({net_0[35], net_0[34], net_0[33],
- net_0[32], net_0[31], net_0[30], net_0[29], net_0[28], net_0[27],
- net_0[26], net_0[25], net_0[24], net_0[23], net_0[22], net_0[21],
- net_0[20], net_0[19], net_0[18], net_0[17], net_0[16], net_0[15],
- net_0[14], net_0[13], net_0[12], net_0[11], net_0[10], net_0[9],
- net_0[8], net_0[7], net_0[6], net_0[5], net_0[4], net_0[3], net_0[2],
- net_0[1], net_0[0]}), .pred(net_109), .sir({net_127[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_1[35],
- net_1[34], net_1[33], net_1[32], net_1[31], net_1[30], net_1[29],
- net_1[28], net_1[27], net_1[26], net_1[25], net_1[24], net_1[23],
- net_1[22], net_1[21], net_1[20], net_1[19], net_1[18], net_1[17],
- net_1[16], net_1[15], net_1[14], net_1[13], net_1[12], net_1[11],
- net_1[10], net_1[9], net_1[8], net_1[7], net_1[6], net_1[5], net_1[4],
- net_1[3], net_1[2], net_1[1], net_1[0]}), .sor({net_128[8]}),
- .succ(net_111), .take({ \take_1[2] }));
- stagesM__plainDockStage plainDoc_4(.in({net_21[35], net_21[34], net_21[33],
- net_21[32], net_21[31], net_21[30], net_21[29], net_21[28], net_21[27],
- net_21[26], net_21[25], net_21[24], net_21[23], net_21[22], net_21[21],
- net_21[20], net_21[19], net_21[18], net_21[17], net_21[16], net_21[15],
- net_21[14], net_21[13], net_21[12], net_21[11], net_21[10], net_21[9],
- net_21[8], net_21[7], net_21[6], net_21[5], net_21[4], net_21[3],
- net_21[2], net_21[1], net_21[0]}), .pred(net_64), .sir({net_116[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .out({net_0[35], net_0[34], net_0[33], net_0[32], net_0[31], net_0[30],
- net_0[29], net_0[28], net_0[27], net_0[26], net_0[25], net_0[24],
- net_0[23], net_0[22], net_0[21], net_0[20], net_0[19], net_0[18],
- net_0[17], net_0[16], net_0[15], net_0[14], net_0[13], net_0[12],
- net_0[11], net_0[10], net_0[9], net_0[8], net_0[7], net_0[6], net_0[5],
- net_0[4], net_0[3], net_0[2], net_0[1], net_0[0]}), .sor({net_127[8]}),
- .succ(net_109), .take({ \take_1[1] }));
- stagesM__plainDockStage plainDoc_5(.in({net_1[35], net_1[34], net_1[33],
- net_1[32], net_1[31], net_1[30], net_1[29], net_1[28], net_1[27],
- net_1[26], net_1[25], net_1[24], net_1[23], net_1[22], net_1[21],
- net_1[20], net_1[19], net_1[18], net_1[17], net_1[16], net_1[15],
- net_1[14], net_1[13], net_1[12], net_1[11], net_1[10], net_1[9],
- net_1[8], net_1[7], net_1[6], net_1[5], net_1[4], net_1[3], net_1[2],
- net_1[1], net_1[0]}), .pred(net_111), .sir({net_128[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_16[35],
- net_16[34], net_16[33], net_16[32], net_16[31], net_16[30], net_16[29],
- net_16[28], net_16[27], net_16[26], net_16[25], net_16[24], net_16[23],
- net_16[22], net_16[21], net_16[20], net_16[19], net_16[18], net_16[17],
- net_16[16], net_16[15], net_16[14], net_16[13], net_16[12], net_16[11],
- net_16[10], net_16[9], net_16[8], net_16[7], net_16[6], net_16[5],
- net_16[4], net_16[3], net_16[2], net_16[1], net_16[0]}),
- .sor({net_125[8]}), .succ(net_69), .take({ \take_1[3] }));
- orangeTSMC090nm__wire90 wire90_0(.a(net_64));
- orangeTSMC090nm__wire90 wire90_1(.a(net_60));
- orangeTSMC090nm__wire90 wire90_2(.a(net_109));
- orangeTSMC090nm__wire90 wire90_3(.a(net_105));
- orangeTSMC090nm__wire90 wire90_4(.a(net_111));
- orangeTSMC090nm__wire90 wire90_5(.a(net_58));
- orangeTSMC090nm__wire90 wire90_6(.a(net_107));
- orangeTSMC090nm__wire90 wire90_7(.a(net_69));
-endmodule /* stageGroupsM__dockWagNine */
-
-module centersJ__ctrAND3in30A(inA, inB, inC, out, outM);
- input inA;
- input inB;
- input inC;
- output out;
- output outM;
-
- supply1 vdd;
- supply0 gnd;
- wire net_6;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (out, outM);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (outM, net_6, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
-endmodule /* centersJ__ctrAND3in30A */
-
-module driversM__suc3ANDdri20(inA, inB, inC, succ);
- input inA;
- input inB;
- input inC;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (net_51, inA, inB, inC);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_71), .g2(net_51), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__suc3ANDdri20 */
-
-module driversM__sucANDdri20(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_51, inA, inB);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_71), .g2(net_51), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucANDdri20 */
-
-module gaspM__gaspEpi(mc, pred, tailBit, tokenLO, epi_OTHER_, epi_TAIL_,
- epi_TORP_, fire, s);
- input mc;
- input pred;
- input tailBit;
- input tokenLO;
- output epi_OTHER_;
- output epi_TAIL_;
- output epi_TORP_;
- output fire;
- output [1:1] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_1079, net_1119, net_1139, net_1147, net_987;
-
- centersJ__ctrAND3in30A ctrAND3i_3(.inA(net_987), .inB(epi_TORP_),
- .inC(net_1079), .out(fire), .outM(net_1119));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_987, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_987);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (net_1139, tokenLO);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_3 (net_1147, tailBit);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(epi_TAIL_), .inb(epi_OTHER_),
- .out(net_1079));
- driversM__predDri20wMC predDri2_0(.in(fire), .mc(mc), .pred(pred));
- driversM__suc3ANDdri20 suc3ANDd_0(.inA(tokenLO), .inB(net_1147), .inC(fire),
- .succ(epi_OTHER_));
- driversM__suc3ANDdri20 suc3ANDd_1(.inA(tokenLO), .inB(tailBit), .inC(fire),
- .succ(epi_TAIL_));
- driversM__sucANDdri20 sucANDdr_1(.inA(net_1139), .inB(fire),
- .succ(epi_TORP_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_987));
- orangeTSMC090nm__wire90 wire90_3(.a(net_1079));
- orangeTSMC090nm__wire90 wire90_4(.a(net_1139));
- orangeTSMC090nm__wire90 wire90_6(.a(net_1147));
-endmodule /* gaspM__gaspEpi */
-
-module stagesM__epiDockStage(do_epi_, in, in_T_, sir, epi, epi_OTHER_,
- epi_TAIL_, epi_TORP_, sor, take_epi_);
- input do_epi_;
- input [1:36] in;
- input in_T_;
- input [1:9] sir;
- output [1:36] epi;
- output epi_OTHER_;
- output epi_TAIL_;
- output epi_TORP_;
- output [1:1] sor;
- output take_epi_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_0, net_47;
-
- gaspM__gaspEpi anEpiSta_1(.mc(sir[9]), .pred(do_epi_), .tailBit(in[28]),
- .tokenLO(in_T_), .epi_OTHER_(epi_OTHER_), .epi_TAIL_(epi_TAIL_),
- .epi_TORP_(epi_TORP_), .fire(net_0), .s({net_47}));
- registersM__ins1in20Bx36 ins1in20_0(.hcl({take_epi_}), .in(in[1:36]),
- .out(epi[1:36]));
- driversM__latchDriver60 latchDri_1(.in(net_0), .out(take_epi_));
- scanM__scanEx1 scanEx1_0(.dIn({net_47}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tranCap_0();
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
-endmodule /* stagesM__epiDockStage */
-
-module gates3inM__nor3in6_6sym(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSx NMOSx_0(.g(inC), .d(out), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_7(.g(inB), .d(out), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_8(.g(inA), .d(out), .s(gnd));
- redFive__pms3 pms3_0(.g(inA), .g2(inB), .g3(inC), .d(out));
- redFive__pms3 pms3_1(.g(inC), .g2(inB), .g3(inA), .d(out));
-endmodule /* gates3inM__nor3in6_6sym */
-
-module oneHotM__onDeck(bits_ABORT_, bits_HEAD_, flag_A__clr_, flag_A__set_,
- flag_D__clr_, flag_D__set_, mc, pred, fire_od_, od_ABORT_, od_HEAD_,
- od_OTHER_, s);
- input bits_ABORT_;
- input bits_HEAD_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input mc;
- input pred;
- output fire_od_;
- output od_ABORT_;
- output od_HEAD_;
- output od_OTHER_;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_297, net_305, net_314, net_322, net_367, net_371, net_438, net_463;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_8 (net_314, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_438, bits_HEAD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_10 (net_463, bits_ABORT_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (s[2], net_297);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_5 (fire_od_, net_367);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_6 (s[1], net_314);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
- nand (strong0, strong1) #(100) nand2LT__2 (net_367, net_371, net_322);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_7 (net_305, flag_A__set_,
- flag_A__clr_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_8 (net_297, flag_D__set_,
- flag_D__clr_);
- // end Verilog_template
- gates3inM__nor3in6_6sym nor3in3__2(.inA(net_297), .inB(net_305),
- .inC(net_314), .out(net_322));
- gates3inM__nor3in6_6sym nor3in3__5(.inA(od_ABORT_), .inB(od_OTHER_),
- .inC(od_HEAD_), .out(net_371));
- driversM__predDri20wMC predDri2_2(.in(fire_od_), .mc(mc), .pred(pred));
- driversM__suc3ANDdri20 suc3ANDd_1(.inA(net_438), .inB(net_463),
- .inC(fire_od_), .succ(od_OTHER_));
- driversM__sucANDdri20 sucANDdr_0(.inA(bits_HEAD_), .inB(fire_od_),
- .succ(od_HEAD_));
- driversM__sucANDdri20 sucANDdr_4(.inA(bits_ABORT_), .inB(fire_od_),
- .succ(od_ABORT_));
- orangeTSMC090nm__wire90 wire90_10(.a(fire_od_));
- orangeTSMC090nm__wire90 wire90_11(.a(net_322));
- orangeTSMC090nm__wire90 wire90_13(.a(net_297));
- orangeTSMC090nm__wire90 wire90_15(.a(net_305));
- orangeTSMC090nm__wire90 wire90_16(.a(net_314));
- orangeTSMC090nm__wire90 wire90_18(.a(net_371));
- orangeTSMC090nm__wire90 wire90_19(.a(net_367));
- orangeTSMC090nm__wire90 wire90_20(.a(net_438));
- orangeTSMC090nm__wire90 wire90_21(.a(net_463));
-endmodule /* oneHotM__onDeck */
-
-module stagesM__onDeckDockStage(do_od_, flag_A__clr_, flag_A__set_,
- flag_D__clr_, flag_D__set_, m1, sir, od, od_ABORT_, od_HEAD_, od_OTHER_,
- sor, take_od_);
- input do_od_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input [1:36] m1;
- input [1:9] sir;
- output [1:36] od;
- output od_ABORT_;
- output od_HEAD_;
- output od_OTHER_;
- output [1:1] sor;
- output take_od_;
-
- supply1 vdd;
- supply0 gnd;
- wire [1:1] fire;
- wire [1:0] net_62;
-
- registersM__ins1in20Bx36 ins1in20_0(.hcl({take_od_}), .in(m1[1:36]),
- .out(od[1:36]));
- driversM__latchDriver60 latchDri_1(.in(fire[1]), .out(take_od_));
- oneHotM__onDeck onDeck_0(.bits_ABORT_(m1[29]), .bits_HEAD_(m1[30]),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .mc(sir[9]),
- .pred(do_od_), .fire_od_(fire[1]), .od_ABORT_(od_ABORT_),
- .od_HEAD_(od_HEAD_), .od_OTHER_(od_OTHER_), .s({net_62[1], net_62[0]}));
- scanM__scanEx2 scanEx2v_2(.dIn({net_62[1], net_62[0]}), .sir(sir[1:9]),
- .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- orangeTSMC090nm__wire90 wire90_1(.a(fire[1]));
-endmodule /* stagesM__onDeckDockStage */
-
-module centersJ__ctrAND1in30(in, out);
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_101, net_82;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_11 (net_82, net_101);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (out, net_82);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (net_101, in);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_1(.a(net_101));
- orangeTSMC090nm__wire90 wire90_2(.a(net_82));
-endmodule /* centersJ__ctrAND1in30 */
-
-module oneHotM__reQueueB(epi_TAIL_, mc, od_HEAD_, circulate, s);
- input epi_TAIL_;
- input mc;
- input od_HEAD_;
- output circulate;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_0, net_125, net_127, net_7;
-
- centersJ__ctrAND1in30 ctrAND1i_0(.in(net_0), .out(net_7));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_127, od_HEAD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (net_125, epi_TAIL_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_3 (s[1], net_127);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_4 (s[2], net_125);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_0, od_HEAD_, epi_TAIL_);
- // end Verilog_template
- driversM__predDri20wMC predDri2_1(.in(net_7), .mc(mc), .pred(epi_TAIL_));
- driversM__predDri20wMC predDri2_2(.in(net_7), .mc(mc), .pred(od_HEAD_));
- driversM__sucDri20 sucDri20_0(.in(net_7), .succ(circulate));
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
- orangeTSMC090nm__wire90 wire90_1(.a(net_7));
- orangeTSMC090nm__wire90 wire90_2(.a(net_125));
- orangeTSMC090nm__wire90 wire90_3(.a(net_127));
-endmodule /* oneHotM__reQueueB */
-
-module redFive__nand2n(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nand2n */
-
-module redFive__nms3(g, g2, g3, d);
- input g;
- input g2;
- input g3;
- output d;
-
- supply0 gnd;
- wire net_6, net_7;
-
- orangeTSMC090nm__NMOSx NMOS_0(.g(g3), .d(d), .s(net_6));
- orangeTSMC090nm__NMOSx NMOS_1(.g(g), .d(net_7), .s(gnd));
- orangeTSMC090nm__NMOSx NMOS_2(.g(g2), .d(net_6), .s(net_7));
-endmodule /* redFive__nms3 */
-
-module gates3inM__nand3in6_6sym(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__PMOSx PMOSx_1(.g(inA), .d(out), .s(vdd));
- orangeTSMC090nm__PMOSx PMOSx_3(.g(inC), .d(out), .s(vdd));
- orangeTSMC090nm__PMOSx PMOSx_4(.g(inB), .d(out), .s(vdd));
- redFive__nms3 nms3_0(.g(inA), .g2(inB), .g3(inC), .d(out));
- redFive__nms3 nms3_2(.g(inC), .g2(inB), .g3(inA), .d(out));
-endmodule /* gates3inM__nand3in6_6sym */
-
-module oneHotM__reQueueC(circulate, epi_OTHER_, mc, od_ABORT_, od_OTHER_,
- ps_do_, ps_skip_, fire_E_, fire_R_, s, succ);
- input circulate;
- input epi_OTHER_;
- input mc;
- input od_ABORT_;
- input od_OTHER_;
- input ps_do_;
- input ps_skip_;
- output fire_E_;
- output fire_R_;
- output [1:2] s;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire abortLO, fire_C_, net_274, net_277, net_280, net_283, net_311, net_313;
- wire net_320, net_324, net_361, net_376, net_396;
-
- centersJ__ctrAND3in30 ctrAND3i_0(.inA(succ), .inB(net_361), .inC(circulate),
- .out(fire_E_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_12 (abortLO, net_376);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_13 (net_361, epi_OTHER_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_14 (net_320, circulate);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (net_376, net_283);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_11 (net_396, abortLO);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_12 (s[2], net_361);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_13 (s[1], net_320);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_1 (net_274, od_OTHER_, ps_skip_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_2 (net_277, od_ABORT_, ps_skip_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_3 (net_280, od_OTHER_, ps_do_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_4 (net_283, od_ABORT_, ps_do_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_5 (net_324, net_313, net_311);
- // end Verilog_template
- redFive__nand2n nand2n_0(.ina(circulate), .inb(succ), .out(net_313));
- redFive__nand2n_sy nand2n_s_0(.ina(net_324), .inb(abortLO), .out(fire_C_));
- gates3inM__nand3in6_6sym nand3in6_1(.inA(net_274), .inB(net_277),
- .inC(net_280), .out(net_311));
- redFive__nor2n nor2n_1(.ina(net_324), .inb(net_320), .out(fire_R_));
- driversM__predDri20wMC predDri2_2(.in(fire_C_), .mc(mc), .pred(od_ABORT_));
- driversM__predDri20wMC predDri2_3(.in(fire_C_), .mc(mc), .pred(od_OTHER_));
- driversM__predDri20wMC predDri2_4(.in(fire_C_), .mc(mc), .pred(ps_do_));
- driversM__predDri20wMC predDri2_5(.in(fire_C_), .mc(mc), .pred(ps_skip_));
- driversM__predDri20wMC predDri2_6(.in(fire_E_), .mc(mc), .pred(epi_OTHER_));
- driversM__predDri20wMC predDri2_7(.in(net_396), .mc(mc), .pred(circulate));
- driversM__sucORdri20 sucORdri_0(.inA(fire_R_), .inB(fire_E_), .succ(succ));
- orangeTSMC090nm__wire90 wire90_12(.a(net_274));
- orangeTSMC090nm__wire90 wire90_13(.a(net_277));
- orangeTSMC090nm__wire90 wire90_14(.a(net_280));
- orangeTSMC090nm__wire90 wire90_15(.a(net_283));
- orangeTSMC090nm__wire90 wire90_16(.a(net_311));
- orangeTSMC090nm__wire90 wire90_17(.a(net_313));
- orangeTSMC090nm__wire90 wire90_18(.a(net_320));
- orangeTSMC090nm__wire90 wire90_19(.a(net_324));
- orangeTSMC090nm__wire90 wire90_20(.a(fire_C_));
- orangeTSMC090nm__wire90 wire90_23(.a(net_376));
- orangeTSMC090nm__wire90 wire90_24(.a(abortLO));
- orangeTSMC090nm__wire90 wire90_25(.a(net_396));
- orangeTSMC090nm__wire90 wire90_27(.a(net_361));
-endmodule /* oneHotM__reQueueC */
-
-module oneHotM__reQueue(epi_OTHER_, epi_TAIL_, mc, od_ABORT_, od_HEAD_,
- od_OTHER_, ps_do_, ps_skip_, fire_E_, fire_R_, rq_succ_, s);
- input epi_OTHER_;
- input epi_TAIL_;
- input mc;
- input od_ABORT_;
- input od_HEAD_;
- input od_OTHER_;
- input ps_do_;
- input ps_skip_;
- output fire_E_;
- output fire_R_;
- output rq_succ_;
- output [1:4] s;
-
- supply1 vdd;
- supply0 gnd;
- wire circulate;
-
- oneHotM__reQueueB reQueueB_1(.epi_TAIL_(epi_TAIL_), .mc(mc),
- .od_HEAD_(od_HEAD_), .circulate(circulate), .s(s[1:2]));
- oneHotM__reQueueC reQueueC_0(.circulate(circulate), .epi_OTHER_(epi_OTHER_),
- .mc(mc), .od_ABORT_(od_ABORT_), .od_OTHER_(od_OTHER_), .ps_do_(ps_do_),
- .ps_skip_(ps_skip_), .fire_E_(fire_E_), .fire_R_(fire_R_), .s(s[3:4]),
- .succ(rq_succ_));
- orangeTSMC090nm__wire90 wire90_0(.a(circulate));
-endmodule /* oneHotM__reQueue */
-
-module scanM__scanEx3plain(dIn, dIn_1, dIn_2, sin, \sir[2] , \sir[3] , \sir[5]
- , sout);
- input [1:1] dIn;
- input [2:2] dIn_1;
- input [3:3] dIn_2;
- input sin;
- input \sir[2] , \sir[3] , \sir[5] ;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_26, net_45;
-
- scanM__scanCellE scanCell_1(.dIn(dIn[1:1]), .p1p( \sir[3] ), .p2p( \sir[2] ),
- .rd( \sir[5] ), .sin(sin), .sout(net_26));
- scanM__scanCellE scanCell_2(.dIn(dIn_1[2:2]), .p1p( \sir[3] ), .p2p( \sir[2]
- ), .rd( \sir[5] ), .sin(net_26), .sout(net_45));
- scanM__scanCellE scanCell_3(.dIn(dIn_2[3:3]), .p1p( \sir[3] ), .p2p( \sir[2]
- ), .rd( \sir[5] ), .sin(net_45), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_26));
- orangeTSMC090nm__wire90 wire90_1(.a(net_45));
-endmodule /* scanM__scanEx3plain */
-
-module stagesM__rqDockStage(epi_OTHER_, epi_TAIL_, inE, inP, od_ABORT_,
- od_HEAD_, od_OTHER_, ps_do_, ps_skip_, sir, rq, rq_succ_, sor, take_E_,
- take_P_);
- input epi_OTHER_;
- input epi_TAIL_;
- input [1:36] inE;
- input [1:36] inP;
- input od_ABORT_;
- input od_HEAD_;
- input od_OTHER_;
- input ps_do_;
- input ps_skip_;
- input [1:9] sir;
- output [1:36] rq;
- output rq_succ_;
- output [1:1] sor;
- output take_E_;
- output take_P_;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_E_, fire_R_, sin;
- wire [1:4] s;
-
- registersM__ins2in20Ax36 ins2in20_0(.hcl_A_(take_E_), .hcl_B_(take_P_),
- .inA(inE[1:36]), .inB(inP[1:36]), .out(rq[1:36]));
- driversM__latchDriver60 latchDri_2(.in(fire_E_), .out(take_E_));
- driversM__latchDriver60 latchDri_3(.in(fire_R_), .out(take_P_));
- oneHotM__reQueue reQueue_0(.epi_OTHER_(epi_OTHER_), .epi_TAIL_(epi_TAIL_),
- .mc(sir[9]), .od_ABORT_(od_ABORT_), .od_HEAD_(od_HEAD_),
- .od_OTHER_(od_OTHER_), .ps_do_(ps_do_), .ps_skip_(ps_skip_),
- .fire_E_(fire_E_), .fire_R_(fire_R_), .rq_succ_(rq_succ_), .s(s[1:4]));
- scanM__scanEx1 scanEx1_0(.dIn({s[1]}), .sir(sir[1:9]), .sor({sin}));
- scanM__scanEx3plain scanEx3p_1(.dIn({s[2]}), .dIn_1({s[3]}), .dIn_2({s[4]}),
- .sin(sin), .\sir[2] (sir[2]), .\sir[3] (sir[3]), .\sir[5] (sir[5]),
- .sout(sor[1]));
- wiresL__tranCap tranCap_0();
- orangeTSMC090nm__wire90 wire90_0(.a(fire_R_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_E_));
-endmodule /* stagesM__rqDockStage */
-
-module stageGroupsM__epiRQod(do_epi_, do_od_, flag_A__clr_, flag_A__set_,
- flag_D__clr_, flag_D__set_, in, in_T_, m1, ps_do_, ps_skip_, sir,
- epi_TORP_, rq, rq_succ_, sor);
- input do_epi_;
- input do_od_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input [1:36] in;
- input in_T_;
- input [1:36] m1;
- input ps_do_;
- input ps_skip_;
- input [1:9] sir;
- output epi_TORP_;
- output [1:36] rq;
- output rq_succ_;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire epi_OTHER_, epi_TAIL_, od_ABORT_, od_HEAD_, od_OTHER_, take_E_, take_P_;
- wire take_epi_, take_od_;
- wire [8:8] net_0;
- wire [8:8] net_36;
- wire [35:0] net_45;
- wire [35:0] net_46;
-
- stagesM__epiDockStage epiDockS_0(.do_epi_(do_epi_), .in(in[1:36]),
- .in_T_(in_T_), .sir(sir[1:9]), .epi({net_45[35], net_45[34], net_45[33],
- net_45[32], net_45[31], net_45[30], net_45[29], net_45[28], net_45[27],
- net_45[26], net_45[25], net_45[24], net_45[23], net_45[22], net_45[21],
- net_45[20], net_45[19], net_45[18], net_45[17], net_45[16], net_45[15],
- net_45[14], net_45[13], net_45[12], net_45[11], net_45[10], net_45[9],
- net_45[8], net_45[7], net_45[6], net_45[5], net_45[4], net_45[3],
- net_45[2], net_45[1], net_45[0]}), .epi_OTHER_(epi_OTHER_),
- .epi_TAIL_(epi_TAIL_), .epi_TORP_(epi_TORP_), .sor({net_0[8]}),
- .take_epi_(take_epi_));
- stagesM__onDeckDockStage onDeckDo_0(.do_od_(do_od_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .m1(m1[1:36]),
- .sir({net_36[8], sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8],
- sir[9]}), .od({net_46[35], net_46[34], net_46[33], net_46[32],
- net_46[31], net_46[30], net_46[29], net_46[28], net_46[27], net_46[26],
- net_46[25], net_46[24], net_46[23], net_46[22], net_46[21], net_46[20],
- net_46[19], net_46[18], net_46[17], net_46[16], net_46[15], net_46[14],
- net_46[13], net_46[12], net_46[11], net_46[10], net_46[9], net_46[8],
- net_46[7], net_46[6], net_46[5], net_46[4], net_46[3], net_46[2],
- net_46[1], net_46[0]}), .od_ABORT_(od_ABORT_), .od_HEAD_(od_HEAD_),
- .od_OTHER_(od_OTHER_), .sor(sor[1:1]), .take_od_(take_od_));
- stagesM__rqDockStage rqDockSt_0(.epi_OTHER_(epi_OTHER_),
- .epi_TAIL_(epi_TAIL_), .inE({net_45[35], net_45[34], net_45[33],
- net_45[32], net_45[31], net_45[30], net_45[29], net_45[28], net_45[27],
- net_45[26], net_45[25], net_45[24], net_45[23], net_45[22], net_45[21],
- net_45[20], net_45[19], net_45[18], net_45[17], net_45[16], net_45[15],
- net_45[14], net_45[13], net_45[12], net_45[11], net_45[10], net_45[9],
- net_45[8], net_45[7], net_45[6], net_45[5], net_45[4], net_45[3],
- net_45[2], net_45[1], net_45[0]}), .inP({net_46[35], net_46[34],
- net_46[33], net_46[32], net_46[31], net_46[30], net_46[29], net_46[28],
- net_46[27], net_46[26], net_46[25], net_46[24], net_46[23], net_46[22],
- net_46[21], net_46[20], net_46[19], net_46[18], net_46[17], net_46[16],
- net_46[15], net_46[14], net_46[13], net_46[12], net_46[11], net_46[10],
- net_46[9], net_46[8], net_46[7], net_46[6], net_46[5], net_46[4],
- net_46[3], net_46[2], net_46[1], net_46[0]}), .od_ABORT_(od_ABORT_),
- .od_HEAD_(od_HEAD_), .od_OTHER_(od_OTHER_), .ps_do_(ps_do_),
- .ps_skip_(ps_skip_), .sir({net_0[8], sir[2], sir[3], sir[4], sir[5],
- sir[6], sir[7], sir[8], sir[9]}), .rq(rq[1:36]), .rq_succ_(rq_succ_),
- .sor({net_36[8]}), .take_E_(take_E_), .take_P_(take_P_));
-endmodule /* stageGroupsM__epiRQod */
-
-module wiresL__bitAssignments();
-endmodule /* wiresL__bitAssignments */
-
-module centersJ__ctrAND3in60(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_6, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (out, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (net_9, net_6, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2{sch}*/
- nor (strong0, strong1) #(100) nor2nn_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_9));
-endmodule /* centersJ__ctrAND3in60 */
-
-module driversM__predDri40(in, pred);
- input in;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
-endmodule /* driversM__predDri40 */
-
-module gaspM__gaspLit(do_ins_, ready, sel_Lt_, fire_L_);
- input do_ins_;
- input ready;
- input sel_Lt_;
- output fire_L_;
-
- supply1 vdd;
- supply0 gnd;
- wire invI_1_out, net_233, net_248, net_251;
-
- centersJ__ctrAND3in60 ctrAND3i_0(.inA(net_248), .inB(net_233), .inC(ready),
- .out(fire_L_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_251, fire_L_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_248, net_251);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (invI_1_out, net_251);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_233, sel_Lt_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(net_248), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_233));
- orangeTSMC090nm__wire90 wire90_2(.a(net_251));
- orangeTSMC090nm__wire90 wire90_3(.a(net_248));
-endmodule /* gaspM__gaspLit */
-
-module driversM__latchAndDriver60(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out, net_8);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_8, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* driversM__latchAndDriver60 */
-
-module stagesM__litDrivers(fire_M_, sel_Dc_, sel_Do_, sel_To_, ready, succ_D_,
- succ_T_, take_A_, take_C_);
- input fire_M_;
- input sel_Dc_;
- input sel_Do_;
- input sel_To_;
- output ready;
- output succ_D_;
- output succ_T_;
- output take_A_;
- output take_C_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_56, net_59;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_56, sel_Dc_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (take_C_, net_59);
- // end Verilog_template
- driversM__latchAndDriver60 latchAnd_1(.inA(sel_Dc_), .inB(fire_M_),
- .out(take_A_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_59, fire_M_, net_56);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(succ_T_), .inb(succ_D_), .out(ready));
- driversM__sucANDdri60 sucANDdr_0(.inA(sel_Do_), .inB(fire_M_),
- .succ(succ_D_));
- driversM__sucANDdri60 sucANDdr_1(.inA(sel_To_), .inB(fire_M_),
- .succ(succ_T_));
- orangeTSMC090nm__wire90 wire90_2(.a(net_56));
- orangeTSMC090nm__wire90 wire90_3(.a(net_59));
-endmodule /* stagesM__litDrivers */
-
-module registersM__data2in60Cx18(dcl_A_, dcl_B_, inA, inB, out);
- input dcl_A_;
- input dcl_B_;
- input [1:18] inA;
- input [1:18] inB;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in60C hiL_1_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[1]}), .inB({inB[1]}), .outS({out[1]}));
- latchesK__latch2in60C hiL_2_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[2]}), .inB({inB[2]}), .outS({out[2]}));
- latchesK__latch2in60C hiL_3_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[3]}), .inB({inB[3]}), .outS({out[3]}));
- latchesK__latch2in60C hiL_4_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[4]}), .inB({inB[4]}), .outS({out[4]}));
- latchesK__latch2in60C hiL_5_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[5]}), .inB({inB[5]}), .outS({out[5]}));
- latchesK__latch2in60C hiL_6_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[6]}), .inB({inB[6]}), .outS({out[6]}));
- latchesK__latch2in60C hiL_7_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[7]}), .inB({inB[7]}), .outS({out[7]}));
- latchesK__latch2in60C hiL_8_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[8]}), .inB({inB[8]}), .outS({out[8]}));
- latchesK__latch2in60C hiL_9_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[9]}), .inB({inB[9]}), .outS({out[9]}));
- latchesK__latch2in60C hiL_10_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[10]}), .inB({inB[10]}), .outS({out[10]}));
- latchesK__latch2in60C hiL_11_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[11]}), .inB({inB[11]}), .outS({out[11]}));
- latchesK__latch2in60C hiL_12_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[12]}), .inB({inB[12]}), .outS({out[12]}));
- latchesK__latch2in60C hiL_13_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[13]}), .inB({inB[13]}), .outS({out[13]}));
- latchesK__latch2in60C hiL_14_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[14]}), .inB({inB[14]}), .outS({out[14]}));
- latchesK__latch2in60C hiL_15_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[15]}), .inB({inB[15]}), .outS({out[15]}));
- latchesK__latch2in60C hiL_16_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[16]}), .inB({inB[16]}), .outS({out[16]}));
- latchesK__latch2in60C hiL_17_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[17]}), .inB({inB[17]}), .outS({out[17]}));
- latchesK__latch2in60C hiL_18_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[18]}), .inB({inB[18]}), .outS({out[18]}));
-endmodule /* registersM__data2in60Cx18 */
-
-module registersM__data2in60Cx37(inA, inB, take_A_, take_B_, out);
- input [1:37] inA;
- input [1:37] inB;
- input take_A_;
- input take_B_;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__data2in60Cx18 data2in6_1(.dcl_A_(take_A_), .dcl_B_(take_B_),
- .inA(inA[1:18]), .inB(inB[1:18]), .out(out[1:18]));
- registersM__data2in60Cx18 data2in6_2(.dcl_A_(take_A_), .dcl_B_(take_B_),
- .inA(inA[20:37]), .inB(inB[20:37]), .out(out[20:37]));
- latchesK__latch2in60C latch2in_4(.hcl_A_(take_A_), .hcl_B_(take_B_),
- .inA({inA[19]}), .inB({inB[19]}), .outS({out[19]}));
- orangeTSMC090nm__wire90 wire90_0(.a(take_A_));
- orangeTSMC090nm__wire90 wire90_4(.a(take_B_));
- orangeTSMC090nm__wire90 wire90_5(.a(take_B_));
- orangeTSMC090nm__wire90 wire90_6(.a(take_A_));
-endmodule /* registersM__data2in60Cx37 */
-
-module latchesK__latch1in09_6Bi(hcl, in, out);
- input hcl;
- input [1:1] in;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_23;
-
- latchesK__raw1inLatchF hi2inLat_0(.hcl(hcl), .in(in[1:1]), .out_F_(net_18));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out[1], net_23);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_23, net_18);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_23));
-endmodule /* latchesK__latch1in09_6Bi */
-
-module redFive__pms2(g, g2, d);
- input g;
- input g2;
- output d;
-
- supply1 vdd;
- wire net_2;
-
- orangeTSMC090nm__PMOSx PMOS_0(.g(g), .d(net_2), .s(vdd));
- orangeTSMC090nm__PMOSx PMOS_1(.g(g2), .d(d), .s(net_2));
-endmodule /* redFive__pms2 */
-
-module redFive__triInv(en, enB, in, out);
- input en;
- input enB;
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2_0(.g(in), .g2(en), .d(out));
- redFive__pms2 pms2_0(.g(in), .g2(enB), .d(out));
-endmodule /* redFive__triInv */
-
-module gates2inM__mux5(inA, inB, s_F_, s_T_, out);
- input [1:1] inA;
- input [1:1] inB;
- input s_F_;
- input s_T_;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__triInv triInv_0(.en(s_T_), .enB(s_F_), .in(inA[1]), .out(out[1]));
- redFive__triInv triInv_1(.en(s_F_), .enB(s_T_), .in(inB[1]), .out(out[1]));
-endmodule /* gates2inM__mux5 */
-
-module latchGroupsK__dataMux(hcl, in, inB, s_F_, s_T_, out);
- input hcl;
- input [1:1] in;
- input [1:1] inB;
- input s_F_;
- input s_T_;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_5;
-
- latchesK__latch1in09_6Bi latch1in_1(.hcl(hcl), .in(in[1:1]), .out({net_5}));
- gates2inM__mux5 mux5_0(.inA({net_5}), .inB(inB[1:1]), .s_F_(s_F_),
- .s_T_(s_T_), .out(out[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_5));
-endmodule /* latchGroupsK__dataMux */
-
-module registersM__shadowMux4(in, s_F_, s_T_, sign, out);
- input [1:4] in;
- input s_F_;
- input s_T_;
- input sign;
- output [1:4] out;
-
- supply1 vdd;
- supply0 gnd;
- wire [1:4] x;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_1_ (x[1], in[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_2_ (x[2], in[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_3_ (x[3], in[3]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_4_ (x[4], in[4]);
- // end Verilog_template
- gates2inM__mux5 m_1_(.inA({x[1]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[1]}));
- gates2inM__mux5 m_2_(.inA({x[2]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[2]}));
- gates2inM__mux5 m_3_(.inA({x[3]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[3]}));
- gates2inM__mux5 m_4_(.inA({x[4]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[4]}));
- orangeTSMC090nm__wire90 wire90_0(.a(x[1]));
- orangeTSMC090nm__wire90 wire90_1(.a(x[2]));
- orangeTSMC090nm__wire90 wire90_2(.a(x[3]));
- orangeTSMC090nm__wire90 wire90_3(.a(x[4]));
-endmodule /* registersM__shadowMux4 */
-
-module registersM__signLogic( \inB[15] , \inB[20] , s_F_, s_T_, sign);
- input \inB[15] , \inB[20] ;
- output s_F_;
- output s_T_;
- output sign;
-
- supply1 vdd;
- supply0 gnd;
- wire net_12, net_14, net_7;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (sign, net_12);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_7, \inB[20] );
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (s_T_, net_7);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (s_F_, s_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_12, net_14);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (net_14, net_7, \inB[15] );
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_2(.a(net_12));
- orangeTSMC090nm__wire90 wire90_4(.a(net_7));
- orangeTSMC090nm__wire90 wire90_5(.a(net_14));
-endmodule /* registersM__signLogic */
-
-module registersM__shadow(hcl, inB, inn, outt);
- input hcl;
- input [15:20] inB;
- input [1:18] inn;
- output [16:37] outt;
-
- supply1 vdd;
- supply0 gnd;
- wire s_F_, s_T_, sign;
-
- latchGroupsK__dataMux dl_1_(.hcl(hcl), .in({inn[1]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[20]}));
- latchGroupsK__dataMux dl_2_(.hcl(hcl), .in({inn[2]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[21]}));
- latchGroupsK__dataMux dl_3_(.hcl(hcl), .in({inn[3]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[22]}));
- latchGroupsK__dataMux dl_4_(.hcl(hcl), .in({inn[4]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[23]}));
- latchGroupsK__dataMux dl_5_(.hcl(hcl), .in({inn[5]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[24]}));
- latchGroupsK__dataMux dl_6_(.hcl(hcl), .in({inn[6]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[25]}));
- latchGroupsK__dataMux dl_7_(.hcl(hcl), .in({inn[7]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[26]}));
- latchGroupsK__dataMux dl_8_(.hcl(hcl), .in({inn[8]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[27]}));
- latchGroupsK__dataMux dl_9_(.hcl(hcl), .in({inn[9]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[28]}));
- latchGroupsK__dataMux dr_1_(.hcl(hcl), .in({inn[18]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[37]}));
- latchGroupsK__dataMux dr_2_(.hcl(hcl), .in({inn[17]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[36]}));
- latchGroupsK__dataMux dr_3_(.hcl(hcl), .in({inn[16]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[35]}));
- latchGroupsK__dataMux dr_4_(.hcl(hcl), .in({inn[15]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[34]}));
- latchGroupsK__dataMux dr_5_(.hcl(hcl), .in({inn[14]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[33]}));
- latchGroupsK__dataMux dr_6_(.hcl(hcl), .in({inn[13]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[32]}));
- latchGroupsK__dataMux dr_7_(.hcl(hcl), .in({inn[12]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[31]}));
- latchGroupsK__dataMux dr_8_(.hcl(hcl), .in({inn[11]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[30]}));
- latchGroupsK__dataMux dr_9_(.hcl(hcl), .in({inn[10]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[29]}));
- registersM__shadowMux4 shadowMu_1(.in(inB[16:19]), .s_F_(s_F_), .s_T_(s_T_),
- .sign(sign), .out(outt[16:19]));
- registersM__signLogic signLogi_0(.\inB[15] (inB[15]), .\inB[20] (inB[20]),
- .s_F_(s_F_), .s_T_(s_T_), .sign(sign));
- orangeTSMC090nm__wire90 wire90_1(.a(s_F_));
- orangeTSMC090nm__wire90 wire90_2(.a(s_T_));
- orangeTSMC090nm__wire90 wire90_3(.a(sign));
-endmodule /* registersM__shadow */
-
-module registersM__newDregister(dp, ps, take_A_, take_B_, out);
- input [1:37] dp;
- input [1:20] ps;
- input take_A_;
- input take_B_;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_66;
- wire [16:37] ss;
-
- registersM__data2in60Cx37 data2in6_0(.inA(dp[1:37]), .inB({ps[1], ps[2],
- ps[3], ps[4], ps[5], ps[6], ps[7], ps[8], ps[9], ps[10], ps[11], ps[12],
- ps[13], ps[14], ps[15], ss[16], ss[17], ss[18], ss[19], ss[20], ss[21],
- ss[22], ss[23], ss[24], ss[25], ss[26], ss[27], ss[28], ss[29], ss[30],
- ss[31], ss[32], ss[33], ss[34], ss[35], ss[36], ss[37]}),
- .take_A_(take_A_), .take_B_(take_B_), .out(out[1:37]));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_66, take_B_);
- // end Verilog_template
- registersM__shadow shadow_0(.hcl(net_66), .inB(ps[15:20]), .inn(out[1:18]),
- .outt(ss[16:37]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_66));
-endmodule /* registersM__newDregister */
-
-module registersM__addr2in60Cx7(ainA, ainB, fire_A_, fire_B_, aout);
- input [1:7] ainA;
- input [1:7] ainB;
- input fire_A_;
- input fire_B_;
- output [1:7] aout;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in60C hiL_1_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[1]}), .inB({ainB[1]}), .outS({aout[1]}));
- latchesK__latch2in60C hiL_2_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[2]}), .inB({ainB[2]}), .outS({aout[2]}));
- latchesK__latch2in60C hiL_3_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[3]}), .inB({ainB[3]}), .outS({aout[3]}));
- latchesK__latch2in60C hiL_4_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[4]}), .inB({ainB[4]}), .outS({aout[4]}));
- latchesK__latch2in60C hiL_5_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[5]}), .inB({ainB[5]}), .outS({aout[5]}));
- latchesK__latch2in60C hiL_6_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[6]}), .inB({ainB[6]}), .outS({aout[6]}));
- latchesK__latch2in60C hiL_7_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[7]}), .inB({ainB[7]}), .outS({aout[7]}));
-endmodule /* registersM__addr2in60Cx7 */
-
-module registersM__addr2in60Cx15(ainA, ainA_TT_, ainB, ainB_TT_, fire_A_,
- fire_B_, aout, aout_TT_);
- input [1:14] ainA;
- input ainA_TT_;
- input [1:14] ainB;
- input ainB_TT_;
- input fire_A_;
- input fire_B_;
- output [1:14] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- registersM__addr2in60Cx7 addr2in6_1(.ainA(ainA[1:7]), .ainB(ainB[1:7]),
- .fire_A_(fire_A_), .fire_B_(fire_B_), .aout(aout[1:7]));
- registersM__addr2in60Cx7 addr2in6_2(.ainA(ainA[8:14]), .ainB(ainB[8:14]),
- .fire_A_(fire_A_), .fire_B_(fire_B_), .aout(aout[8:14]));
- latchesK__latch2in60C latch2in_4(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA_TT_}), .inB({ainB_TT_}), .outS({aout_TT_}));
- orangeTSMC090nm__wire90 wire90_3(.a(fire_A_));
- orangeTSMC090nm__wire90 wire90_4(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_5(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_6(.a(fire_A_));
-endmodule /* registersM__addr2in60Cx15 */
-
-module driversM__latchAndDriver30(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out, net_8);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_8, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* driversM__latchAndDriver30 */
-
-module registersM__newPathReg(dp, fire_M_, ps, aout, aout_TT_);
- input [1:12] dp;
- input fire_M_;
- input [1:15] ps;
- output [14:1] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_25, net_28, net_58, ps_15not_, take_dp_, take_ps_;
-
- registersM__addr2in60Cx15 addr2in6_0(.ainA({dp[1], dp[2], dp[3], dp[4],
- dp[5], dp[6], dp[7], dp[8], dp[9], dp[10], dp[11], dp[12], dp[12],
- dp[12]}), .ainA_TT_(ps_15not_), .ainB({ps[1], ps[2], ps[3], ps[4], ps[5],
- ps[6], ps[7], ps[8], ps[9], ps[10], ps[11], ps[12], ps[13], ps[13]}),
- .ainB_TT_(ps_15not_), .fire_A_(take_dp_), .fire_B_(take_ps_),
- .aout({aout[1], aout[2], aout[3], aout[4], aout[5], aout[6], aout[7],
- aout[8], aout[9], aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_28, ps[13]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_25, ps[14]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (ps_15not_, ps[15]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (take_dp_, net_58);
- // end Verilog_template
- driversM__latchAndDriver30 latchAnd_1(.inA(ps[14]), .inB(fire_M_),
- .out(take_ps_));
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_1 (net_58, net_25, net_28, fire_M_);
- // end Verilog_template
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- orangeTSMC090nm__wire90 wire90_0(.a(take_ps_));
- orangeTSMC090nm__wire90 wire90_1(.a(take_dp_));
- orangeTSMC090nm__wire90 wire90_3(.a(net_28));
- orangeTSMC090nm__wire90 wire90_4(.a(net_25));
- orangeTSMC090nm__wire90 wire90_5(.a(ps_15not_));
- orangeTSMC090nm__wire90 wire90_6(.a(net_58));
-endmodule /* registersM__newPathReg */
-
-module stagesM__litDandP(do_ins_, dp, dp_B_, fire_M_, \ps[1] , \ps[2] , \ps[3]
- , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] , \ps[9] , \ps[10] , \ps[11]
- , \ps[12] , \ps[13] , \ps[14] , \ps[15] , \ps[16] , \ps[17] , \ps[18] ,
- \ps[19] , \ps[20] , \ps[27] , signalBitFromInboundSwitchFabric, dsA,
- dsA_TT_, dsD, flag_C_, succ_D_, succ_T_);
- input do_ins_;
- input [1:37] dp;
- input dp_B_;
- input fire_M_;
- input \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] ,
- \ps[9] , \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] ,
- \ps[16] , \ps[17] , \ps[18] , \ps[19] , \ps[20] , \ps[27] ;
- input signalBitFromInboundSwitchFabric;
- output [14:1] dsA;
- output dsA_TT_;
- output [1:37] dsD;
- output flag_C_;
- output succ_D_;
- output succ_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_108, net_140, take_A_, take_B_;
-
- wiresL__bitAssignments bitAssig_0();
- gaspM__gaspLit gaspLit_1(.do_ins_(do_ins_), .ready(net_108), .sel_Lt_(
- \ps[27] ), .fire_L_(take_B_));
- latchesK__latch2in60C latch2in_0(.hcl_A_(take_A_), .hcl_B_(net_140),
- .inA({dp_B_}), .inB({signalBitFromInboundSwitchFabric}),
- .outS({flag_C_}));
- stagesM__litDrivers litDrive_0(.fire_M_(fire_M_), .sel_Dc_( \ps[17] ),
- .sel_Do_( \ps[16] ), .sel_To_( \ps[15] ), .ready(net_108),
- .succ_D_(succ_D_), .succ_T_(succ_T_), .take_A_(take_A_),
- .take_C_(net_140));
- registersM__newDregister newDregi_0(.dp(dp[1:37]), .ps({ \ps[1] , \ps[2] ,
- \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] , \ps[9] ,
- \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] , \ps[16]
- , \ps[17] , \ps[18] , \ps[19] , \ps[20] }), .take_A_(take_A_),
- .take_B_(take_B_), .out(dsD[1:37]));
- registersM__newPathReg newPathR_0(.dp(dp[26:37]), .fire_M_(fire_M_), .ps({
- \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] ,
- \ps[8] , \ps[9] , \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] ,
- \ps[15] }), .aout(dsA[14:1]), .aout_TT_(dsA_TT_));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_108));
- orangeTSMC090nm__wire90 wire90_4(.a(net_140));
-endmodule /* stagesM__litDandP */
-
-module redFive__nms1(g, d);
- input g;
- output d;
-
- supply0 gnd;
- orangeTSMC090nm__NMOSx NMOS_1(.g(g), .d(d), .s(gnd));
-endmodule /* redFive__nms1 */
-
-module redFive__pms2_sy(g, g2, d);
- input g;
- input g2;
- output d;
-
- supply1 vdd;
- redFive__pms2 pms2_0(.g(g), .g2(g2), .d(d));
- redFive__pms2 pms2_1(.g(g2), .g2(g), .d(d));
-endmodule /* redFive__pms2_sy */
-
-module oneHotM__sucDri10Pair(bit, when, out_1__F_, out_1__T_);
- input [1:1] bit;
- input when;
- output out_1__F_;
- output out_1__T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_112, net_139, net_4, net_66, net_92;
-
- orangeTSMC090nm__NMOSx NMOSx_2(.g(net_66), .d(out_1__F_), .s(net_139));
- orangeTSMC090nm__NMOSx NMOSx_3(.g(bit[1]), .d(out_1__F_), .s(net_139));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_66, when);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_92, out_1__F_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (net_112, out_1__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_4, when, bit[1]);
- // end Verilog_template
- redFive__nms1 nms1_2(.g(net_92), .d(net_139));
- redFive__nms2 nms2b_0(.g(net_112), .g2(net_4), .d(out_1__T_));
- redFive__pms1 pms1_0(.g(net_4), .d(out_1__T_));
- redFive__pms2_sy pms2_sy_0(.g(net_66), .g2(bit[1]), .d(out_1__F_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_4));
- orangeTSMC090nm__wire90 wire90_1(.a(net_66));
- orangeTSMC090nm__wire90 wire90_3(.a(net_112));
- orangeTSMC090nm__wire90 wire90_4(.a(net_92));
- orangeTSMC090nm__wire90 wire90_5(.a(net_139));
-endmodule /* oneHotM__sucDri10Pair */
-
-module oneHotM__sucDri10Pairx6(bit, when, m1cate_1__F_, m1cate_1__T_,
- m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_,
- m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_,
- ready);
- input [1:6] bit;
- input when;
- output m1cate_1__F_;
- output m1cate_1__T_;
- output m1cate_2__F_;
- output m1cate_2__T_;
- output m1cate_3__F_;
- output m1cate_3__T_;
- output m1cate_4__F_;
- output m1cate_4__T_;
- output m1cate_5__F_;
- output m1cate_5__T_;
- output m1cate_6__F_;
- output m1cate_6__T_;
- output ready;
-
- supply1 vdd;
- supply0 gnd;
- oneHotM__sucDri10Pair dd_1_(.bit({bit[1]}), .when(when),
- .out_1__F_(m1cate_1__F_), .out_1__T_(m1cate_1__T_));
- oneHotM__sucDri10Pair dd_2_(.bit({bit[2]}), .when(when),
- .out_1__F_(m1cate_2__F_), .out_1__T_(m1cate_2__T_));
- oneHotM__sucDri10Pair dd_3_(.bit({bit[3]}), .when(when),
- .out_1__F_(m1cate_3__F_), .out_1__T_(m1cate_3__T_));
- oneHotM__sucDri10Pair dd_4_(.bit({bit[4]}), .when(when),
- .out_1__F_(m1cate_4__F_), .out_1__T_(m1cate_4__T_));
- oneHotM__sucDri10Pair dd_5_(.bit({bit[5]}), .when(when),
- .out_1__F_(m1cate_5__F_), .out_1__T_(m1cate_5__T_));
- oneHotM__sucDri10Pair dd_6_(.bit({bit[6]}), .when(when),
- .out_1__F_(m1cate_6__F_), .out_1__T_(m1cate_6__T_));
- redFive__nor2n_sy nor2n_sy_0(.ina(m1cate_1__T_), .inb(m1cate_1__F_),
- .out(ready));
-endmodule /* oneHotM__sucDri10Pairx6 */
-
-module oneHotM__minusOne(bit, headBit, mc, pred, fire_m1_, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, s, succ_m1_);
- input [1:6] bit;
- input headBit;
- input mc;
- input pred;
- output fire_m1_;
- output m1cate_1__F_;
- output m1cate_1__T_;
- output m1cate_2__F_;
- output m1cate_2__T_;
- output m1cate_3__F_;
- output m1cate_3__T_;
- output m1cate_4__F_;
- output m1cate_4__T_;
- output m1cate_5__F_;
- output m1cate_5__T_;
- output m1cate_6__F_;
- output m1cate_6__T_;
- output [1:1] s;
- output succ_m1_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_235, net_391, net_398, net_406, net_414;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_7 (net_235, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_235);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (fire_m1_, net_398);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_398, net_414, net_391);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(headBit), .inb(net_398), .out(net_406));
- redFive__nor2n_sy nor2n_sy_1(.ina(succ_m1_), .inb(net_235), .out(net_391));
- driversM__predDri20wMC predDri2_0(.in(fire_m1_), .mc(mc), .pred(pred));
- oneHotM__sucDri10Pairx6 sucDri10_1(.bit(bit[1:6]), .when(net_406),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_),
- .ready(net_414));
- driversM__sucDri20 sucDri20_1(.in(fire_m1_), .succ(succ_m1_));
- orangeTSMC090nm__wire90 wire90_10(.a(fire_m1_));
- orangeTSMC090nm__wire90 wire90_11(.a(net_235));
- orangeTSMC090nm__wire90 wire90_12(.a(net_414));
- orangeTSMC090nm__wire90 wire90_13(.a(net_391));
- orangeTSMC090nm__wire90 wire90_14(.a(net_398));
- orangeTSMC090nm__wire90 wire90_15(.a(net_406));
-endmodule /* oneHotM__minusOne */
-
-module stagesM__mOneDockStage(pred_R_, ring, sir, m1, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, sor, succ_m1_, take_m1_);
- input pred_R_;
- input [1:36] ring;
- input [1:9] sir;
- output [1:36] m1;
- output m1cate_1__F_;
- output m1cate_1__T_;
- output m1cate_2__F_;
- output m1cate_2__T_;
- output m1cate_3__F_;
- output m1cate_3__T_;
- output m1cate_4__F_;
- output m1cate_4__T_;
- output m1cate_5__F_;
- output m1cate_5__T_;
- output m1cate_6__F_;
- output m1cate_6__T_;
- output [1:1] sor;
- output succ_m1_;
- output take_m1_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_47;
- wire [1:1] fire;
-
- registersM__ins1in20Bx36 ins1in20_0(.hcl({take_m1_}), .in(ring[1:36]),
- .out(m1[1:36]));
- driversM__latchDriver60 latchDri_1(.in(fire[1]), .out(take_m1_));
- oneHotM__minusOne minusOne_0(.bit(ring[31:36]), .headBit(ring[30]),
- .mc(sir[9]), .pred(pred_R_), .fire_m1_(fire[1]),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .s({net_47}),
- .succ_m1_(succ_m1_));
- scanM__scanEx1 scanEx1_0(.dIn({net_47}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- wiresL__tranCap tc_17_();
- wiresL__tranCap tc_18_();
- wiresL__tranCap tc_19_();
- orangeTSMC090nm__wire90 wire90_1(.a(fire[1]));
-endmodule /* stagesM__mOneDockStage */
-
-module loopCountM__mux10_2(in, sF, sT, out);
- input [1:1] in;
- input sF;
- input sT;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2b_0(.g(sT), .g2(in[1]), .d(out[1]));
- redFive__pms2 pms2_0(.g(sF), .g2(in[1]), .d(out[1]));
-endmodule /* loopCountM__mux10_2 */
-
-module loopCountM__mux10_2x7(in, sF, sT, out);
- input [1:7] in;
- input sF;
- input sT;
- output [1:7] out;
-
- supply1 vdd;
- supply0 gnd;
- loopCountM__mux10_2 mux10_2_0(.in({in[1]}), .sF(sF), .sT(sT),
- .out({out[1]}));
- loopCountM__mux10_2 mux10_2_1(.in({in[2]}), .sF(sF), .sT(sT),
- .out({out[2]}));
- loopCountM__mux10_2 mux10_2_2(.in({in[3]}), .sF(sF), .sT(sT),
- .out({out[3]}));
- loopCountM__mux10_2 mux10_2_3(.in({in[4]}), .sF(sF), .sT(sT),
- .out({out[4]}));
- loopCountM__mux10_2 mux10_2_4(.in({in[5]}), .sF(sF), .sT(sT),
- .out({out[5]}));
- loopCountM__mux10_2 mux10_2_5(.in({in[6]}), .sF(sF), .sT(sT),
- .out({out[6]}));
- loopCountM__mux10_2 mux10_2_6(.in({in[7]}), .sF(sF), .sT(sT),
- .out({out[7]}));
-endmodule /* loopCountM__mux10_2x7 */
-
-module loopCountM__muxForPS(in, sel, out);
- input [1:7] in;
- input sel;
- output [1:7] out;
-
- supply1 vdd;
- supply0 gnd;
- wire sF, sT;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (sT, sel);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_1 (sF, sT);
- // end Verilog_template
- loopCountM__mux10_2x7 mux10_2x_0(.in(in[1:7]), .sF(sF), .sT(sT),
- .out(out[1:7]));
- orangeTSMC090nm__wire90 wire90_0(.a(sT));
- orangeTSMC090nm__wire90 wire90_1(.a(sF));
-endmodule /* loopCountM__muxForPS */
-
-module registersM__dockPSreg(do_ins_, m1, outLO, ps);
- input do_ins_;
- input [1:27] m1;
- output [1:7] outLO;
- output [1:27] ps;
-
- supply1 vdd;
- supply0 gnd;
- wire [1:1] hold;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (hold[1], do_ins_);
- // end Verilog_template
- latchesK__latch1in20B lx_1_(.hcl(hold[1]), .in({m1[1]}), .out({ps[1]}));
- latchesK__latch1in20B lx_2_(.hcl(hold[1]), .in({m1[2]}), .out({ps[2]}));
- latchesK__latch1in20B lx_3_(.hcl(hold[1]), .in({m1[3]}), .out({ps[3]}));
- latchesK__latch1in20B lx_4_(.hcl(hold[1]), .in({m1[4]}), .out({ps[4]}));
- latchesK__latch1in20B lx_5_(.hcl(hold[1]), .in({m1[5]}), .out({ps[5]}));
- latchesK__latch1in20B lx_6_(.hcl(hold[1]), .in({m1[6]}), .out({ps[6]}));
- latchesK__latch1in20B lx_7_(.hcl(hold[1]), .in({m1[7]}), .out({ps[7]}));
- latchesK__latch1in20B lx_8_(.hcl(hold[1]), .in({m1[8]}), .out({ps[8]}));
- latchesK__latch1in20B lx_9_(.hcl(hold[1]), .in({m1[9]}), .out({ps[9]}));
- latchesK__latch1in20B lx_10_(.hcl(hold[1]), .in({m1[10]}), .out({ps[10]}));
- latchesK__latch1in20B lx_11_(.hcl(hold[1]), .in({m1[11]}), .out({ps[11]}));
- latchesK__latch1in20B lx_12_(.hcl(hold[1]), .in({m1[12]}), .out({ps[12]}));
- latchesK__latch1in20B lx_13_(.hcl(hold[1]), .in({m1[13]}), .out({ps[13]}));
- latchesK__latch1in20B lx_14_(.hcl(hold[1]), .in({m1[14]}), .out({ps[14]}));
- latchesK__latch1in20B lx_15_(.hcl(hold[1]), .in({m1[15]}), .out({ps[15]}));
- latchesK__latch1in20B lx_16_(.hcl(hold[1]), .in({m1[16]}), .out({ps[16]}));
- latchesK__latch1in20B lx_17_(.hcl(hold[1]), .in({m1[17]}), .out({ps[17]}));
- latchesK__latch1in20B lx_18_(.hcl(hold[1]), .in({m1[18]}), .out({ps[18]}));
- latchesK__latch1in20B lx_19_(.hcl(hold[1]), .in({m1[19]}), .out({ps[19]}));
- latchesK__latch1in20B lx_20_(.hcl(hold[1]), .in({m1[20]}), .out({ps[20]}));
- latchesK__latch1in20B lx_21_(.hcl(hold[1]), .in({m1[21]}), .out({ps[21]}));
- latchesK__latch1in20B lx_22_(.hcl(hold[1]), .in({m1[22]}), .out({ps[22]}));
- latchesK__latch1in20B lx_23_(.hcl(hold[1]), .in({m1[23]}), .out({ps[23]}));
- latchesK__latch1in20B lx_24_(.hcl(hold[1]), .in({m1[24]}), .out({ps[24]}));
- latchesK__latch1in20B lx_25_(.hcl(hold[1]), .in({m1[25]}), .out({ps[25]}));
- latchesK__latch1in20B lx_26_(.hcl(hold[1]), .in({m1[26]}), .out({ps[26]}));
- latchesK__latch1in20B lx_27_(.hcl(hold[1]), .in({m1[27]}), .out({ps[27]}));
- loopCountM__muxForPS muxForOD_0(.in({ps[1], ps[2], ps[3], ps[4], ps[5],
- ps[6], ps[8]}), .sel(ps[20]), .out(outLO[1:7]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- orangeTSMC090nm__wire90 wire90_0(.a(hold[1]));
-endmodule /* registersM__dockPSreg */
-
-module redFive__xor2(ina, inaB, inb, inbB, out);
- input ina;
- input inaB;
- input inb;
- input inbB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2_0(.g(inb), .g2(ina), .d(out));
- redFive__nms2 nms2_1(.g(inbB), .g2(inaB), .d(out));
- redFive__pms2 pms2_0(.g(inbB), .g2(ina), .d(out));
- redFive__pms2 pms2_1(.g(inb), .g2(inaB), .d(out));
-endmodule /* redFive__xor2 */
-
-module oneHotM__ohXor(flag_F_, flag_T_, in_1__F_, in_1__T_, out);
- input flag_F_;
- input flag_T_;
- input in_1__F_;
- input in_1__T_;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__xor2 xor2_0(.ina(in_1__T_), .inaB(in_1__F_), .inb(flag_T_),
- .inbB(flag_F_), .out(out));
-endmodule /* oneHotM__ohXor */
-
-module oneHotM__xor6x12(flag_1__F_, flag_1__T_, flag_2__F_, flag_2__T_,
- flag_3__F_, flag_3__T_, in_1__F_, in_1__T_, in_2__F_, in_2__T_, in_3__F_,
- in_3__T_, in_4__F_, in_4__T_, in_5__F_, in_5__T_, in_6__F_, in_6__T_,
- all, any);
- input flag_1__F_;
- input flag_1__T_;
- input flag_2__F_;
- input flag_2__T_;
- input flag_3__F_;
- input flag_3__T_;
- input in_1__F_;
- input in_1__T_;
- input in_2__F_;
- input in_2__T_;
- input in_3__F_;
- input in_3__T_;
- input in_4__F_;
- input in_4__T_;
- input in_5__F_;
- input in_5__T_;
- input in_6__F_;
- input in_6__T_;
- output all;
- output any;
-
- supply1 vdd;
- supply0 gnd;
- wire match_12F_, match_12T_, match_34F_, match_34T_, match_56F_, match_56T_;
-
- gates3inM__nand3in6_6sym nand3in6_2(.inA(match_12T_), .inB(match_34T_),
- .inC(match_56T_), .out(any));
- gates3inM__nor3in6_6sym nor3in3__1(.inA(match_56F_), .inB(match_34F_),
- .inC(match_12F_), .out(all));
- oneHotM__ohXor ohMux_6(.flag_F_(flag_1__F_), .flag_T_(flag_1__T_),
- .in_1__F_(in_2__F_), .in_1__T_(in_1__F_), .out(match_12F_));
- oneHotM__ohXor ohMux_7(.flag_F_(flag_1__F_), .flag_T_(flag_1__T_),
- .in_1__F_(in_2__T_), .in_1__T_(in_1__T_), .out(match_12T_));
- oneHotM__ohXor ohMux_8(.flag_F_(flag_2__F_), .flag_T_(flag_2__T_),
- .in_1__F_(in_4__F_), .in_1__T_(in_3__F_), .out(match_34F_));
- oneHotM__ohXor ohMux_9(.flag_F_(flag_2__F_), .flag_T_(flag_2__T_),
- .in_1__F_(in_4__T_), .in_1__T_(in_3__T_), .out(match_34T_));
- oneHotM__ohXor ohMux_10(.flag_F_(flag_3__F_), .flag_T_(flag_3__T_),
- .in_1__F_(in_6__F_), .in_1__T_(in_5__F_), .out(match_56F_));
- oneHotM__ohXor ohMux_11(.flag_F_(flag_3__F_), .flag_T_(flag_3__T_),
- .in_1__F_(in_6__T_), .in_1__T_(in_5__T_), .out(match_56T_));
- orangeTSMC090nm__wire90 wire90_0(.a(match_34F_));
- orangeTSMC090nm__wire90 wire90_1(.a(match_34T_));
- orangeTSMC090nm__wire90 wire90_2(.a(match_56F_));
- orangeTSMC090nm__wire90 wire90_3(.a(match_56T_));
- orangeTSMC090nm__wire90 wire90_4(.a(match_12F_));
- orangeTSMC090nm__wire90 wire90_5(.a(match_12T_));
-endmodule /* oneHotM__xor6x12 */
-
-module oneHotM__aFlag(flag_1__clr_, flag_1__set_, flag_A__F_, flag_A__T_,
- flag_B__F_, flag_B__T_, flag_C__F_, flag_C__T_, in_1__T_, in_2__T_,
- in_3__T_, in_4__T_, in_5__T_, in_6__T_, mc, flag_1__F_, flag_1__T_);
- input flag_1__clr_;
- input flag_1__set_;
- input flag_A__F_;
- input flag_A__T_;
- input flag_B__F_;
- input flag_B__T_;
- input flag_C__F_;
- input flag_C__T_;
- input in_1__T_;
- input in_2__T_;
- input in_3__T_;
- input in_4__T_;
- input in_5__T_;
- input in_6__T_;
- input mc;
- output flag_1__F_;
- output flag_1__T_;
-
- supply1 vdd;
- supply0 gnd;
- wire in_1__F_, in_2__F_, in_3__F_, in_4__F_, in_5__F_, in_6__F_, net_172;
- wire net_2, net_22, net_234, net_235, net_236, net_240, net_265, net_305;
- wire net_306, net_308, net_5, net_50, net_68, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (flag_1__T_, net_235);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (flag_1__F_, net_234);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (net_265, net_2);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_305, mc);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (net_308, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_11 (net_306, net_172);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1_ (in_1__F_, in_1__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2_ (in_2__F_, in_2__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3_ (in_3__F_, in_3__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4_ (in_4__F_, in_4__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5_ (in_5__F_, in_5__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6_ (in_6__F_, in_6__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_9, net_5, net_2);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_172, net_68, net_2);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_236, net_50, net_265);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_3 (net_240, net_22, net_265);
- // end Verilog_template
- redFive__nand2n nand2n_0(.ina(net_9), .inb(net_22), .out(net_50));
- redFive__nand2n nand2n_1(.ina(net_172), .inb(net_50), .out(net_22));
- redFive__nand2n nand2n_2(.ina(net_236), .inb(net_235), .out(net_234));
- redFive__nand2n nand2n_3(.ina(net_240), .inb(net_234), .out(net_235));
- redFive__nor2n_sy nor2n_sy_0(.ina(flag_1__clr_), .inb(flag_1__set_),
- .out(net_2));
- driversM__sucANDdri20 sucANDdr_0(.inA(net_305), .inB(net_308),
- .succ(flag_1__set_));
- driversM__sucANDdri20 sucANDdr_3(.inA(net_305), .inB(net_306),
- .succ(flag_1__clr_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_5));
- orangeTSMC090nm__wire90 wire90_4(.a(net_22));
- orangeTSMC090nm__wire90 wire90_5(.a(net_50));
- orangeTSMC090nm__wire90 wire90_6(.a(net_9));
- orangeTSMC090nm__wire90 wire90_8(.a(net_68));
- orangeTSMC090nm__wire90 wire90_19(.a(net_172));
- orangeTSMC090nm__wire90 wire90_22(.a(net_240));
- orangeTSMC090nm__wire90 wire90_23(.a(net_236));
- orangeTSMC090nm__wire90 wire90_24(.a(net_235));
- orangeTSMC090nm__wire90 wire90_25(.a(net_234));
- orangeTSMC090nm__wire90 wire90_26(.a(net_2));
- orangeTSMC090nm__wire90 wire90_27(.a(net_265));
- orangeTSMC090nm__wire90 wire90_28(.a(net_305));
- oneHotM__xor6x12 xor6x12_0(.flag_1__F_(flag_A__F_), .flag_1__T_(flag_A__T_),
- .flag_2__F_(flag_B__F_), .flag_2__T_(flag_B__T_),
- .flag_3__F_(flag_C__F_), .flag_3__T_(flag_C__T_), .in_1__F_(in_1__F_),
- .in_1__T_(in_1__T_), .in_2__F_(in_2__F_), .in_2__T_(in_2__T_),
- .in_3__F_(in_3__F_), .in_3__T_(in_3__T_), .in_4__F_(in_4__F_),
- .in_4__T_(in_4__T_), .in_5__F_(in_5__F_), .in_5__T_(in_5__T_),
- .in_6__F_(in_6__F_), .in_6__T_(in_6__T_), .all(net_68), .any(net_5));
-endmodule /* oneHotM__aFlag */
-
-module scanM__scanEx3h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:3] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_20;
-
- scanM__scanCellE scanCell_10(.dIn({dIn[1]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(net_18));
- scanM__scanCellE scanCell_11(.dIn({dIn[2]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_18), .sout(net_20));
- scanM__scanCellE scanCell_12(.dIn({dIn[3]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_20), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_20));
-endmodule /* scanM__scanEx3h */
-
-module oneHotM__flags(flag_A__clr_, flag_A__set_, flag_B__clr_, flag_B__set_,
- flag_C__T_, m1, sin, sout, mc, p1p, p2p, rd);
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_C__T_;
- input [1:12] m1;
- input sin;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire flag_A__F_, flag_A__T_, flag_B__F_, flag_B__T_, flag_C__F_;
- wire [1:3] s;
-
- oneHotM__aFlag aFlag_0(.flag_1__clr_(flag_A__clr_),
- .flag_1__set_(flag_A__set_), .flag_A__F_(flag_A__F_),
- .flag_A__T_(flag_A__T_), .flag_B__F_(flag_B__F_),
- .flag_B__T_(flag_B__T_), .flag_C__F_(flag_C__F_),
- .flag_C__T_(flag_C__T_), .in_1__T_(m1[1]), .in_2__T_(m1[2]),
- .in_3__T_(m1[3]), .in_4__T_(m1[4]), .in_5__T_(m1[5]), .in_6__T_(m1[6]),
- .mc(mc), .flag_1__F_(flag_A__F_), .flag_1__T_(flag_A__T_));
- oneHotM__aFlag aFlag_1(.flag_1__clr_(flag_B__clr_),
- .flag_1__set_(flag_B__set_), .flag_A__F_(flag_A__F_),
- .flag_A__T_(flag_A__T_), .flag_B__F_(flag_B__F_),
- .flag_B__T_(flag_B__T_), .flag_C__F_(flag_C__F_),
- .flag_C__T_(flag_C__T_), .in_1__T_(m1[7]), .in_2__T_(m1[8]),
- .in_3__T_(m1[9]), .in_4__T_(m1[10]), .in_5__T_(m1[11]),
- .in_6__T_(m1[12]), .mc(mc), .flag_1__F_(flag_B__F_),
- .flag_1__T_(flag_B__T_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (flag_C__F_, flag_C__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], flag_A__F_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[2], flag_B__F_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (s[3], flag_C__F_);
- // end Verilog_template
- scanM__scanEx3h scanEx3h_0(.dIn(s[1:3]), .sin(sin), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
-endmodule /* oneHotM__flags */
-
-module loopCountM__calculate(bit, bit_1, bit_2, bit_3, bit_4, bit_5, do, do_1,
- do_2, do_3, do_4, zero, zoo);
- input [1:1] bit;
- input [2:2] bit_1;
- input [3:3] bit_2;
- input [4:4] bit_3;
- input [5:5] bit_4;
- input [6:6] bit_5;
- output [2:2] do;
- output [3:3] do_1;
- output [4:4] do_2;
- output [5:5] do_3;
- output [6:6] do_4;
- output zero;
- output zoo;
-
- supply1 vdd;
- supply0 gnd;
- wire net_128, net_198, net_221, net_257, net_267, net_56, net_58;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (do[2], net_257);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_128, bit_1[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_257, bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_58, bit_2[3], bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_56, bit_3[4], bit_1[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_267, bit_2[3], bit_4[5]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (net_221, bit_4[5], bit_2[3],
- bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_1 (net_198, bit_5[6], bit_3[4],
- bit_1[2]);
- // end Verilog_template
- redFive__nor2n nor2n_1(.ina(net_128), .inb(net_257), .out(do_1[3]));
- redFive__nor2n nor2n_2(.ina(net_58), .inb(net_128), .out(do_2[4]));
- redFive__nor2n nor2n_3(.ina(net_56), .inb(net_58), .out(do_3[5]));
- redFive__nor2n nor2n_4(.ina(net_221), .inb(net_56), .out(do_4[6]));
- redFive__nor2n nor2n_5(.ina(net_198), .inb(net_267), .out(zoo));
- redFive__nor2n nor2n_6(.ina(net_198), .inb(net_221), .out(zero));
- orangeTSMC090nm__wire90 wire90_0(.a(net_221));
- orangeTSMC090nm__wire90 wire90_1(.a(net_58));
- orangeTSMC090nm__wire90 wire90_3(.a(net_56));
- orangeTSMC090nm__wire90 wire90_5(.a(net_198));
- orangeTSMC090nm__wire90 wire90_6(.a(net_128));
- orangeTSMC090nm__wire90 wire90_8(.a(net_267));
-endmodule /* loopCountM__calculate */
-
-module latchesK__mlat1in5s(c_F_, c_T_, in, inC, out);
- input c_F_;
- input c_T_;
- input in;
- input inC;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_166;
-
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (out[1], net_166, inC);
- // end Verilog_template
- redFive__nms2 nms2_2(.g(in), .g2(c_T_), .d(net_166));
- redFive__nms2 nms2_3(.g(out[1]), .g2(c_F_), .d(net_166));
- redFive__pms2 pms2_0(.g(out[1]), .g2(c_T_), .d(net_166));
- redFive__pms2 pms2_1(.g(in), .g2(c_F_), .d(net_166));
- orangeTSMC090nm__wire90 wire90_19(.a(net_166));
-endmodule /* latchesK__mlat1in5s */
-
-module latchesK__mlat1in5i(c_F_, c_T_, in, out);
- input c_F_;
- input c_T_;
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_114;
-
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_114, out);
- // end Verilog_template
- redFive__nms2 nms2_2(.g(in), .g2(c_T_), .d(out));
- redFive__nms2 nms2_3(.g(net_114), .g2(c_F_), .d(out));
- redFive__pms2 pms2_0(.g(net_114), .g2(c_T_), .d(out));
- redFive__pms2 pms2_1(.g(in), .g2(c_F_), .d(out));
- orangeTSMC090nm__wire90 wire90_19(.a(net_114));
-endmodule /* latchesK__mlat1in5i */
-
-module latchesK__mlat2in10i(clA_F_, clA_T_, clB_F_, clB_T_, inA, inB, out);
- input clA_F_;
- input clA_T_;
- input clB_F_;
- input clB_T_;
- input inA;
- input inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_33;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_33, out[1]);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(inB), .g2(clB_T_), .d(out[1]));
- redFive__nms2 nms2_1(.g(inA), .g2(clA_T_), .d(out[1]));
- redFive__nms3 nms3_0(.g(clB_F_), .g2(clA_F_), .g3(net_33), .d(out[1]));
- redFive__pms2 pms2_0(.g(inB), .g2(clB_F_), .d(out[1]));
- redFive__pms2 pms2_1(.g(inA), .g2(clA_F_), .d(out[1]));
- redFive__pms3 pms3_0(.g(clA_T_), .g2(clB_T_), .g3(net_33), .d(out[1]));
- orangeTSMC090nm__wire90 wire90_1(.a(net_33));
-endmodule /* latchesK__mlat2in10i */
-
-module loopCountM__ringB(count_F_, count_T_, do, inLO, load_F_, load_T_, bit);
- input count_F_;
- input count_T_;
- input [1:1] do;
- input [1:1] inLO;
- input load_F_;
- input load_T_;
- output [1:1] bit;
-
- supply1 vdd;
- supply0 gnd;
- wire net_60, net_65, net_67, net_77, net_9, xx_F_, xx_T_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (bit[1], net_60);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_67, bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_65, net_67);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_3 (xx_F_, xx_T_);
- // end Verilog_template
- latchesK__mlat1in5i mlat1in5_0(.c_F_(xx_T_), .c_T_(xx_F_), .in(net_65),
- .out(net_9));
- latchesK__mlat1in5i mlat1in5_1(.c_F_(count_T_), .c_T_(count_F_), .in(do[1]),
- .out(net_77));
- latchesK__mlat2in10i mlat2in1_0(.clA_F_(load_F_), .clA_T_(load_T_),
- .clB_F_(xx_F_), .clB_T_(xx_T_), .inA(inLO[1]), .inB(net_9),
- .out({net_60}));
- redFive__nor2n nor2n_0(.ina(net_77), .inb(count_F_), .out(xx_T_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_67));
- orangeTSMC090nm__wire90 wire90_2(.a(net_65));
- orangeTSMC090nm__wire90 wire90_3(.a(net_60));
- orangeTSMC090nm__wire90 wire90_5(.a(net_9));
- orangeTSMC090nm__wire90 wire90_6(.a(xx_F_));
- orangeTSMC090nm__wire90 wire90_7(.a(net_77));
- orangeTSMC090nm__wire90 wire90_8(.a(xx_T_));
-endmodule /* loopCountM__ringB */
-
-module loopCountM__ilcEven(do, do_1, do_2, ilc_decLO_, ilc_torpLO_, \inLO[2] ,
- \inLO[4] , \inLO[6] , \inLO[8] , load_T_, zero, \bitt[2] , \bitt[4] ,
- \bitt[6] , \bitt[8] );
- input [2:2] do;
- input [4:4] do_1;
- input [6:6] do_2;
- input ilc_decLO_;
- input ilc_torpLO_;
- input \inLO[2] , \inLO[4] , \inLO[6] , \inLO[8] ;
- input load_T_;
- input zero;
- output \bitt[2] , \bitt[4] , \bitt[6] , \bitt[8] ;
-
- supply1 vdd;
- supply0 gnd;
- wire count_F_, count_T_, load_F_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_7 (count_F_, count_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_8 (load_F_, load_T_);
- // end Verilog_template
- latchesK__mlat1in5s mlat1in5_1(.c_F_(load_F_), .c_T_(load_T_), .in( \inLO[8]
- ), .inC(ilc_torpLO_), .out({ \bitt[8] }));
- redFive__nor2n nor2n_0(.ina(zero), .inb(ilc_decLO_), .out(count_T_));
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_2[6:6]), .inLO({ \inLO[6] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[6] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[4:4]), .inLO({ \inLO[4] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[4] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[2:2]), .inLO({ \inLO[2] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[2] }));
- orangeTSMC090nm__wire90 wire90_8(.a(count_F_));
- orangeTSMC090nm__wire90 wire90_9(.a(load_F_));
- orangeTSMC090nm__wire90 wire90_10(.a(count_T_));
-endmodule /* loopCountM__ilcEven */
-
-module latchesK__mlat2in5s(clA_F_, clA_T_, clB_F_, clB_T_, inA, inB, inC,
- out);
- input clA_F_;
- input clA_T_;
- input clB_F_;
- input clB_T_;
- input inA;
- input inB;
- input inC;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_4;
-
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (out[1], net_4, inC);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(inB), .g2(clB_T_), .d(net_4));
- redFive__nms2 nms2_1(.g(inA), .g2(clA_T_), .d(net_4));
- redFive__nms3 nms3_0(.g(clA_F_), .g2(out[1]), .g3(clB_F_), .d(net_4));
- redFive__pms2 pms2_0(.g(inB), .g2(clB_F_), .d(net_4));
- redFive__pms2 pms2_1(.g(inA), .g2(clA_F_), .d(net_4));
- redFive__pms3 pms3_0(.g(clA_T_), .g2(out[1]), .g3(clB_T_), .d(net_4));
- orangeTSMC090nm__wire90 wire90_0(.a(net_4));
-endmodule /* latchesK__mlat2in5s */
-
-module loopCountM__ilcOdd(do, do_1, do_2, ilc_decLO_, ilc_torpLO_, \inLO[1] ,
- \inLO[3] , \inLO[5] , load_T_, zero, \bitt[1] , \bitt[3] , \bitt[5] ,
- \bitt[7] );
- input [3:3] do;
- input [5:5] do_1;
- input [7:7] do_2;
- input ilc_decLO_;
- input ilc_torpLO_;
- input \inLO[1] , \inLO[3] , \inLO[5] ;
- input load_T_;
- input zero;
- output \bitt[1] , \bitt[3] , \bitt[5] , \bitt[7] ;
-
- supply1 vdd;
- supply0 gnd;
- wire check_F_, check_T_, count_F_, count_T_, load_F_, net_511;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_5 (count_F_, count_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_6 (load_F_, load_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_7 (check_F_, check_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_8 (check_T_, ilc_decLO_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_12 ( \bitt[7] , net_511);
- // end Verilog_template
- latchesK__mlat2in5s mlat2in5_4(.clA_F_(load_F_), .clA_T_(load_T_),
- .clB_F_(check_F_), .clB_T_(check_T_), .inA(gnd), .inB(do_2[7]),
- .inC(ilc_torpLO_), .out({net_511}));
- redFive__nor2n nor2n_0(.ina(zero), .inb(ilc_decLO_), .out(count_T_));
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[5:5]), .inLO({ \inLO[5] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[5] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[3:3]), .inLO({ \inLO[3] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[3] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do({vdd}), .inLO({ \inLO[1] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[1] }));
- orangeTSMC090nm__wire90 wire90_4(.a(count_F_));
- orangeTSMC090nm__wire90 wire90_5(.a(load_F_));
- orangeTSMC090nm__wire90 wire90_6(.a(check_F_));
- orangeTSMC090nm__wire90 wire90_7(.a(count_T_));
- orangeTSMC090nm__wire90 wire90_8(.a(check_T_));
- orangeTSMC090nm__wire90 wire90_9(.a(net_511));
-endmodule /* loopCountM__ilcOdd */
-
-module gates3inM__orNand10(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_14;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(inC), .d(out), .s(net_14));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(inB), .d(out), .s(net_14));
- redFive__nms1 nms1_0(.g(inA), .d(net_14));
- redFive__pms1 pms1_0(.g(inA), .d(net_14));
- redFive__pms2 pms2_0(.g(inC), .g2(inB), .d(out));
-endmodule /* gates3inM__orNand10 */
-
-module loopCountM__ilc(ilc_decLO_, ilc_load_, ilc_torpLO_, \inLO[1] , \inLO[2]
- , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , bitt, ilc_do_,
- ilc_mo_);
- input ilc_decLO_;
- input ilc_load_;
- input ilc_torpLO_;
- input \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] ;
- output [1:8] bitt;
- output ilc_do_;
- output ilc_mo_;
-
- supply1 vdd;
- supply0 gnd;
- wire ovf, zero;
- wire [7:2] do;
-
- loopCountM__calculate calculat_0(.bit({bitt[1]}), .bit_1({bitt[2]}),
- .bit_2({bitt[3]}), .bit_3({bitt[4]}), .bit_4({bitt[5]}),
- .bit_5({bitt[6]}), .do(do[2:2]), .do_1(do[3:3]), .do_2(do[4:4]),
- .do_3(do[5:5]), .do_4(do[6:6]), .zero(zero), .zoo(do[7]));
- loopCountM__ilcEven ilcEven_0(.do(do[2:2]), .do_1(do[4:4]), .do_2(do[6:6]),
- .ilc_decLO_(ilc_decLO_), .ilc_torpLO_(ilc_torpLO_), .\inLO[2] ( \inLO[2]
- ), .\inLO[4] ( \inLO[4] ), .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8]
- ), .load_T_(ilc_load_), .zero(zero), .\bitt[2] (bitt[2]), .\bitt[4]
- (bitt[4]), .\bitt[6] (bitt[6]), .\bitt[8] (bitt[8]));
- loopCountM__ilcOdd ilcOdd_0(.do(do[3:3]), .do_1(do[5:5]), .do_2(do[7:7]),
- .ilc_decLO_(ilc_decLO_), .ilc_torpLO_(ilc_torpLO_), .\inLO[1] ( \inLO[1]
- ), .\inLO[3] ( \inLO[3] ), .\inLO[5] ( \inLO[5] ), .load_T_(ilc_load_),
- .zero(zero), .\bitt[1] (bitt[1]), .\bitt[3] (bitt[3]), .\bitt[5]
- (bitt[5]), .\bitt[7] (bitt[7]));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (ovf, bitt[7]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (ilc_do_, bitt[8], bitt[7], zero);
- // end Verilog_template
- gates3inM__orNand10 orNand10_0(.inA(bitt[8]), .inB(ovf), .inC(do[7]),
- .out(ilc_mo_));
- orangeTSMC090nm__wire90 wire90_1(.a(do[2]));
- orangeTSMC090nm__wire90 wire90_2(.a(do[3]));
- orangeTSMC090nm__wire90 wire90_3(.a(do[4]));
- orangeTSMC090nm__wire90 wire90_4(.a(do[5]));
- orangeTSMC090nm__wire90 wire90_5(.a(do[6]));
- orangeTSMC090nm__wire90 wire90_48(.a(bitt[7]));
- orangeTSMC090nm__wire90 wire90_49(.a(bitt[8]));
- orangeTSMC090nm__wire90 wire90_51(.a(zero));
-endmodule /* loopCountM__ilc */
-
-module gates3inM__nand3in44s(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (out, inA, inB, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_1 (out, inB, inA, inC);
- // end Verilog_template
-endmodule /* gates3inM__nand3in44s */
-
-module moveM__moveRepeat(do_ins_, in_D_, in_T_, sel_Di_, sel_Mv_, sel_Ti_,
- sel_Tp_, succ_sf_, torp, fire_T_, winLO_M_);
- input do_ins_;
- input in_D_;
- input in_T_;
- input sel_Di_;
- input sel_Mv_;
- input sel_Ti_;
- input sel_Tp_;
- input succ_sf_;
- input torp;
- output fire_T_;
- output winLO_M_;
-
- supply1 vdd;
- supply0 gnd;
- wire invI_7_out, net_11, net_12, net_150, net_217, net_221, net_32, net_38;
- wire net_43, net_44, net_53, net_57, net_60, net_86, net_98;
-
- arbiterM__arbiter2 arbiter2_0(.req_A_(torp), .req_B_(in_D_),
- .grant_A_(net_12), .grant_B_(net_11));
- arbiterM__arbiter2 arbiter2_1(.req_A_(torp), .req_B_(in_T_),
- .grant_A_(net_32), .grant_B_(net_53));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (fire_T_, net_150);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_6 (net_217, net_221);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_7 (invI_7_out, net_217);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_86, net_217, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_5 (net_221, winLO_M_, sel_Mv_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_6 (net_38, sel_Tp_, do_ins_);
- // end Verilog_template
- redFive__nand2n nand2n_0(.ina(sel_Di_), .inb(net_11), .out(net_57));
- redFive__nand2n nand2n_1(.ina(sel_Ti_), .inb(net_53), .out(net_60));
- gates3inM__nand3in44s nand3in4_0(.inA(net_57), .inB(net_60), .inC(net_98),
- .out(winLO_M_));
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_0 (net_150, net_43, net_44);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(net_38), .inb(net_12), .out(net_44));
- redFive__nor2n nor2n_1(.ina(net_38), .inb(net_32), .out(net_43));
- redFive__nor2n nor2n_2(.ina(succ_sf_), .inb(net_86), .out(net_98));
- orangeTSMC090nm__wire90 wire90_0(.a(net_12));
- orangeTSMC090nm__wire90 wire90_1(.a(net_32));
- orangeTSMC090nm__wire90 wire90_2(.a(net_53));
- orangeTSMC090nm__wire90 wire90_3(.a(net_11));
- orangeTSMC090nm__wire90 wire90_4(.a(net_38));
- orangeTSMC090nm__wire90 wire90_6(.a(net_44));
- orangeTSMC090nm__wire90 wire90_7(.a(net_43));
- orangeTSMC090nm__wire90 wire90_8(.a(net_60));
- orangeTSMC090nm__wire90 wire90_9(.a(net_57));
- orangeTSMC090nm__wire90 wire90_11(.a(net_86));
- orangeTSMC090nm__wire90 wire90_13(.a(net_98));
- orangeTSMC090nm__wire90 wire90_15(.a(net_150));
- orangeTSMC090nm__wire90 wire90_19(.a(net_217));
- orangeTSMC090nm__wire90 wire90_20(.a(net_221));
-endmodule /* moveM__moveRepeat */
-
-module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_,
- pred_T_, sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, succ_sf_, doneLO_M_,
- fire_M_, flag_D__set_, ilc_decLO_, ilc_torpLO_, s);
- input do_ins_;
- input epi_torp_;
- input ilc_do_;
- input ilc_mo_;
- input mc;
- input pred_D_;
- input pred_T_;
- input sel_Di_;
- input sel_Mv_;
- input sel_Ti_;
- input sel_Tp_;
- input succ_sf_;
- output doneLO_M_;
- output fire_M_;
- output flag_D__set_;
- output ilc_decLO_;
- output ilc_torpLO_;
- output [1:3] s;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_T_, net_194, net_200, net_201, net_205, net_206, net_220, net_227;
- wire net_250, net_29, net_326;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_326, fire_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_10 (net_220, ilc_do_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_13 (net_194, pred_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_14 (net_227, pred_D_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_15 (net_29, epi_torp_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_16 (ilc_torpLO_, fire_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_9 (s[1], net_194);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (s[2], net_227);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_11 (s[3], net_29);
- // end Verilog_template
- moveM__moveRepeat moveRepe_0(.do_ins_(do_ins_), .in_D_(pred_D_),
- .in_T_(pred_T_), .sel_Di_(sel_Di_), .sel_Mv_(sel_Mv_), .sel_Ti_(sel_Ti_),
- .sel_Tp_(sel_Tp_), .succ_sf_(succ_sf_), .torp(epi_torp_),
- .fire_T_(fire_T_), .winLO_M_(ilc_decLO_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_206, ilc_do_, sel_Di_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_3 (net_205, ilc_do_, sel_Ti_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_4 (doneLO_M_, sel_Tp_, net_250);
- // end Verilog_template
- redFive__nor2n nor2n_1(.ina(ilc_mo_), .inb(ilc_decLO_), .out(net_250));
- redFive__nor2n nor2n_5(.ina(net_206), .inb(ilc_decLO_), .out(net_201));
- redFive__nor2n nor2n_6(.ina(net_205), .inb(ilc_decLO_), .out(net_200));
- redFive__nor2n nor2n_7(.ina(net_220), .inb(ilc_decLO_), .out(fire_M_));
- redFive__pms1 pms1_0(.g(net_326), .d(flag_D__set_));
- driversM__predDri20wMC predDri2_0(.in(fire_T_), .mc(mc), .pred(epi_torp_));
- driversM__predDri20wMC predDri2_3(.in(net_201), .mc(mc), .pred(pred_D_));
- driversM__predDri20wMC predDri2_4(.in(net_200), .mc(mc), .pred(pred_T_));
- driversM__predDri40 predDri4_0(.in(net_250), .pred(do_ins_));
- driversM__predDri40 predDri4_1(.in(fire_T_), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_9(.a(net_206));
- orangeTSMC090nm__wire90 wire90_10(.a(net_220));
- orangeTSMC090nm__wire90 wire90_11(.a(net_200));
- orangeTSMC090nm__wire90 wire90_12(.a(net_201));
- orangeTSMC090nm__wire90 wire90_13(.a(net_205));
- orangeTSMC090nm__wire90 wire90_15(.a(net_250));
- orangeTSMC090nm__wire90 wire90_16(.a(fire_T_));
- orangeTSMC090nm__wire90 wire90_17(.a(net_326));
-endmodule /* moveM__moveOut */
-
-module scanM__scanEx1h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:1] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- scanM__scanCellE scanCell_10(.dIn(dIn[1:1]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(sout));
-endmodule /* scanM__scanEx1h */
-
-module scanM__scanEx2h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:2] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18;
-
- scanM__scanCellE scanCell_10(.dIn({dIn[1]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(net_18));
- scanM__scanCellE scanCell_11(.dIn({dIn[2]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_18), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
-endmodule /* scanM__scanEx2h */
-
-module scanM__scanEx4h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:4] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_20, net_24;
-
- scanM__scanCellE scanCell_10(.dIn({dIn[1]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(net_18));
- scanM__scanCellE scanCell_11(.dIn({dIn[2]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_18), .sout(net_20));
- scanM__scanCellE scanCell_12(.dIn({dIn[3]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_20), .sout(net_24));
- scanM__scanCellE scanCell_13(.dIn({dIn[4]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_24), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_20));
- orangeTSMC090nm__wire90 wire90_2(.a(net_24));
-endmodule /* scanM__scanEx4h */
-
-module moveM__ilcMoveOut(do_ins_, epi_torp_, ilc_load_, \inLO[1] , \inLO[2] ,
- \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , pred_D_, pred_T_,
- sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, sin, succ_sf_, doneLO_M_, fire_M_,
- flag_D__set_, sout, mc, p1p, p2p, rd);
- input do_ins_;
- input epi_torp_;
- input ilc_load_;
- input \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] ;
- input pred_D_;
- input pred_T_;
- input sel_Di_;
- input sel_Mv_;
- input sel_Ti_;
- input sel_Tp_;
- input sin;
- input succ_sf_;
- output doneLO_M_;
- output fire_M_;
- output flag_D__set_;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire ilc_decLO_, ilc_do_, ilc_mo_, ilc_torpLO_, net_50, net_84, net_85;
- wire [1:8] bitt;
- wire [1:3] s;
-
- loopCountM__ilc ilc_0(.ilc_decLO_(ilc_decLO_), .ilc_load_(ilc_load_),
- .ilc_torpLO_(ilc_torpLO_), .\inLO[1] ( \inLO[1] ), .\inLO[2] ( \inLO[2]
- ), .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] ( \inLO[5]
- ), .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .bitt(bitt[1:8]),
- .ilc_do_(ilc_do_), .ilc_mo_(ilc_mo_));
- moveM__moveOut outDockM_0(.do_ins_(do_ins_), .epi_torp_(epi_torp_),
- .ilc_do_(ilc_do_), .ilc_mo_(ilc_mo_), .mc(mc), .pred_D_(pred_D_),
- .pred_T_(pred_T_), .sel_Di_(sel_Di_), .sel_Mv_(sel_Mv_),
- .sel_Ti_(sel_Ti_), .sel_Tp_(sel_Tp_), .succ_sf_(succ_sf_),
- .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
- .ilc_decLO_(ilc_decLO_), .ilc_torpLO_(ilc_torpLO_), .s(s[1:3]));
- scanM__scanEx1h scanEx1h_0(.dIn({s[3]}), .sin(net_84), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx2h scanEx2h_0(.dIn(s[1:2]), .sin(net_85), .mc(mc),
- .sout(net_84), .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx4h scanEx4h_0(.dIn({bitt[1], bitt[3], bitt[5], bitt[7]}),
- .sin(sin), .mc(mc), .sout(net_50), .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx4h scanEx4h_1(.dIn({bitt[2], bitt[4], bitt[6], bitt[8]}),
- .sin(net_50), .mc(mc), .sout(net_85), .p1p(p1p), .p2p(p2p), .rd(rd));
- orangeTSMC090nm__wire90 wire90_1(.a(ilc_mo_));
- orangeTSMC090nm__wire90 wire90_2(.a(ilc_do_));
- orangeTSMC090nm__wire90 wire90_3(.a(bitt[8]));
- orangeTSMC090nm__wire90 wire90_4(.a(bitt[1]));
- orangeTSMC090nm__wire90 wire90_5(.a(bitt[2]));
- orangeTSMC090nm__wire90 wire90_6(.a(bitt[3]));
- orangeTSMC090nm__wire90 wire90_7(.a(bitt[4]));
- orangeTSMC090nm__wire90 wire90_8(.a(bitt[5]));
- orangeTSMC090nm__wire90 wire90_9(.a(bitt[6]));
- orangeTSMC090nm__wire90 wire90_10(.a(bitt[7]));
- orangeTSMC090nm__wire90 wire90_11(.a(ilc_decLO_));
- orangeTSMC090nm__wire90 wire90_12(.a(ilc_torpLO_));
-endmodule /* moveM__ilcMoveOut */
-
-module loopCountM__muxForD(in, sel, outLO);
- input [1:6] in;
- input sel;
- output [1:7] outLO;
-
- supply1 vdd;
- supply0 gnd;
- wire sF, sT;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (sF, sel);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_1 (sT, sF);
- // end Verilog_template
- loopCountM__mux10_2x7 mux10_2x_0(.in({in[1], in[2], in[3], in[4], in[5],
- in[6], gnd}), .sF(sF), .sT(sT), .out(outLO[1:7]));
- orangeTSMC090nm__wire90 wire90_0(.a(sF));
- orangeTSMC090nm__wire90 wire90_1(.a(sT));
-endmodule /* loopCountM__muxForD */
-
-module predicateM__nand3in20sr(inA, inB, inC, resetLO, out);
- input inA;
- input inB;
- input inC;
- input resetLO;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms3 nms3a_0(.g(inA), .g2(inB), .g3(inC), .d(out));
- redFive__pms1 pms1_0(.g(inC), .d(out));
- redFive__pms1 pms1_1(.g(inB), .d(out));
- redFive__pms1 pms1_2(.g(inA), .d(out));
- redFive__pms1 pms1_3(.g(resetLO), .d(out));
-endmodule /* predicateM__nand3in20sr */
-
-module predicateM__flagNOP(do_ins_, ps_Fl_);
- input do_ins_;
- input ps_Fl_;
-
- supply1 vdd;
- supply0 gnd;
- wire invI_2_out, invI_3_out, net_0, net_15, net_22, net_4;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_22, net_15);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_4, net_22);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (net_15, net_0);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (invI_2_out, net_15);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_3 (invI_3_out, net_22);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_0, ps_Fl_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(net_4), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
- orangeTSMC090nm__wire90 wire90_1(.a(net_15));
- orangeTSMC090nm__wire90 wire90_2(.a(net_4));
- orangeTSMC090nm__wire90 wire90_3(.a(net_22));
-endmodule /* predicateM__flagNOP */
-
-module driversM__predCond20wMC(cond, in, mc, pred);
- input cond;
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145, net_210;
-
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- orangeTSMC090nm__PMOSx PMOSx_0(.g(in), .d(pred), .s(net_210));
- orangeTSMC090nm__PMOSx PMOSx_1(.g(cond), .d(pred), .s(net_210));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(cond), .g2(in), .d(pred));
- redFive__pms2 pms2a_0(.g(mc), .g2(net_145), .d(net_210));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
- orangeTSMC090nm__wire90 wire90_1(.a(net_210));
-endmodule /* driversM__predCond20wMC */
-
-module driversM__predCond20wMS(cond, in, mc, pred);
- input cond;
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145, net_210, net_240;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(cond), .d(pred), .s(net_210));
- orangeTSMC090nm__PMOSx PMOSx_1(.g(in), .d(pred), .s(net_210));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_240, mc);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(cond), .g2(in), .d(pred));
- redFive__pms1 pms1_0(.g(net_240), .d(pred));
- redFive__pms2 pms2a_0(.g(mc), .g2(net_145), .d(net_210));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
- orangeTSMC090nm__wire90 wire90_1(.a(net_210));
-endmodule /* driversM__predCond20wMS */
-
-module predicateM__predFlagDri(fire_do_, flag_A__clr_, flag_A__set_,
- flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, mc, sel_Fl_,
- sel_rD_);
- input fire_do_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input mc;
- input sel_Fl_;
- input sel_rD_;
-
- supply1 vdd;
- supply0 gnd;
- wiresL__bitAssignments bitAssig_0();
- driversM__predCond20wMC pc_1_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_A__set_));
- driversM__predCond20wMC pc_2_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_A__clr_));
- driversM__predCond20wMC pc_3_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_B__set_));
- driversM__predCond20wMC pc_4_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_B__clr_));
- driversM__predCond20wMC predCond_0(.cond(sel_rD_), .in(fire_do_), .mc(mc),
- .pred(flag_D__clr_));
- driversM__predCond20wMS predCond_1(.cond(sel_rD_), .in(fire_do_), .mc(mc),
- .pred(flag_D__set_));
-endmodule /* predicateM__predFlagDri */
-
-module driversM__sucDri40keep(in, mc, succ);
- input in;
- input mc;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_110, net_113;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_110), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_110, in);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (net_113, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:invK{sch}*/
- not (weak0, weak1) #(100) invK_0 (succ, net_113);
- // end Verilog_template
- redFive__nms1 nms1_0(.g(mc), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_113));
- orangeTSMC090nm__wire90 wire90_1(.a(net_110));
-endmodule /* driversM__sucDri40keep */
-
-module predicateM__ohPredDo(fire_do_, fire_skip_, flag_A__clr_, flag_A__set_,
- flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, m1_Fl_, m1_rD_,
- mc, ps_Fl_, do_ins_, ps_do_, ps_skip_, s);
- input fire_do_;
- input fire_skip_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input m1_Fl_;
- input m1_rD_;
- input mc;
- input ps_Fl_;
- output do_ins_;
- output ps_do_;
- output ps_skip_;
- output [3:3] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_156;
-
- wiresL__bitAssignments bitAssig_0();
- predicateM__flagNOP flagNOP_0(.do_ins_(do_ins_), .ps_Fl_(ps_Fl_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_156, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[3], net_156);
- // end Verilog_template
- predicateM__predFlagDri predFlag_1(.fire_do_(fire_do_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .mc(mc),
- .sel_Fl_(m1_Fl_), .sel_rD_(m1_rD_));
- driversM__sucDri20 sucDri20_0(.in(fire_skip_), .succ(ps_skip_));
- driversM__sucDri20 sucDri20_1(.in(fire_do_), .succ(ps_do_));
- driversM__sucDri40keep sucDri40_0(.in(fire_do_), .mc(mc), .succ(do_ins_));
- orangeTSMC090nm__wire90 wire90_2(.a(fire_skip_));
- orangeTSMC090nm__wire90 wire90_3(.a(net_156));
-endmodule /* predicateM__ohPredDo */
-
-module predicateM__ohSRxor(flag_F_, flag_T_, resetLO, sel, out);
- input flag_F_;
- input flag_T_;
- input resetLO;
- input [1:2] sel;
- output out; trireg out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2b_4(.g(flag_T_), .g2(sel[1]), .d(out));
- redFive__nms2 nms2b_5(.g(flag_F_), .g2(sel[2]), .d(out));
- redFive__pms1 pms1_0(.g(resetLO), .d(out));
- redFive__pms2 pms2_0(.g(flag_T_), .g2(sel[2]), .d(out));
- redFive__pms2 pms2_1(.g(flag_F_), .g2(sel[1]), .d(out));
-endmodule /* predicateM__ohSRxor */
-
-module predicateM__ohSRxor6x12(flag_A__clr_, flag_A__set_, flag_B__clr_,
- flag_B__set_, flag_D__clr_, flag_D__set_, in_1__F_, in_1__T_, in_2__F_,
- in_2__T_, in_3__F_, in_3__T_, in_4__F_, in_4__T_, in_5__F_, in_5__T_,
- in_6__F_, in_6__T_, resetLO, all, any);
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input in_1__F_;
- input in_1__T_;
- input in_2__F_;
- input in_2__T_;
- input in_3__F_;
- input in_3__T_;
- input in_4__F_;
- input in_4__T_;
- input in_5__F_;
- input in_5__T_;
- input in_6__F_;
- input in_6__T_;
- input resetLO;
- output all;
- output any;
-
- supply1 vdd;
- supply0 gnd;
- wire match_12F_, match_12T_, match_34F_, match_34T_, match_56F_, match_56T_;
-
- gates3inM__nand3in6_6sym nand3in6_3(.inA(match_12T_), .inB(match_34T_),
- .inC(match_56T_), .out(any));
- gates3inM__nor3in6_6sym nor3in3__2(.inA(match_12F_), .inB(match_34F_),
- .inC(match_56F_), .out(all));
- predicateM__ohSRxor ohSRxor_6(.flag_F_(flag_A__clr_), .flag_T_(flag_A__set_),
- .resetLO(resetLO), .sel({in_1__T_, in_2__T_}), .out(match_12T_));
- predicateM__ohSRxor ohSRxor_7(.flag_F_(flag_A__clr_), .flag_T_(flag_A__set_),
- .resetLO(resetLO), .sel({in_1__F_, in_2__F_}), .out(match_12F_));
- predicateM__ohSRxor ohSRxor_8(.flag_F_(flag_B__clr_), .flag_T_(flag_B__set_),
- .resetLO(resetLO), .sel({in_3__F_, in_4__F_}), .out(match_34F_));
- predicateM__ohSRxor ohSRxor_9(.flag_F_(flag_B__clr_), .flag_T_(flag_B__set_),
- .resetLO(resetLO), .sel({in_3__T_, in_4__T_}), .out(match_34T_));
- predicateM__ohSRxor ohSRxor_10(.flag_F_(flag_D__clr_),
- .flag_T_(flag_D__set_), .resetLO(resetLO), .sel({in_5__F_, in_6__F_}),
- .out(match_56F_));
- predicateM__ohSRxor ohSRxor_11(.flag_F_(flag_D__clr_),
- .flag_T_(flag_D__set_), .resetLO(resetLO), .sel({in_5__T_, in_6__T_}),
- .out(match_56T_));
- orangeTSMC090nm__wire90 wire90_1(.a(match_34T_));
- orangeTSMC090nm__wire90 wire90_3(.a(match_56T_));
- orangeTSMC090nm__wire90 wire90_4(.a(match_12F_));
- orangeTSMC090nm__wire90 wire90_5(.a(match_12T_));
- orangeTSMC090nm__wire90 wire90_6(.a(match_34F_));
- orangeTSMC090nm__wire90 wire90_7(.a(match_56F_));
-endmodule /* predicateM__ohSRxor6x12 */
-
-module predicateM__ohPredPred(fire_both_, flag_A__clr_, flag_A__set_,
- flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, mc, any, do, resetLO, s);
- input fire_both_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input mc;
- output any;
- output do;
- output resetLO;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_49, net_62, net_67;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (resetLO, net_49);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_18, fire_both_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_49, net_18);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_4 (s[1], net_62);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_5 (s[2], net_67);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_5 (net_67, flag_A__clr_,
- flag_A__set_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_6 (net_62, m1cate_1__F_,
- m1cate_1__T_);
- // end Verilog_template
- predicateM__ohSRxor6x12 ohSRxor6_1(.flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_),
- .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .in_1__F_(m1cate_1__F_),
- .in_1__T_(m1cate_1__T_), .in_2__F_(m1cate_2__F_),
- .in_2__T_(m1cate_2__T_), .in_3__F_(m1cate_3__F_),
- .in_3__T_(m1cate_3__T_), .in_4__F_(m1cate_4__F_),
- .in_4__T_(m1cate_4__T_), .in_5__F_(m1cate_5__F_),
- .in_5__T_(m1cate_5__T_), .in_6__F_(m1cate_6__F_),
- .in_6__T_(m1cate_6__T_), .resetLO(net_18), .all(do), .any(any));
- driversM__predDri20wMC pp_1_(.in(fire_both_), .mc(mc), .pred(m1cate_1__T_));
- driversM__predDri20wMC pp_2_(.in(fire_both_), .mc(mc), .pred(m1cate_1__F_));
- driversM__predDri20wMC pp_3_(.in(fire_both_), .mc(mc), .pred(m1cate_2__T_));
- driversM__predDri20wMC pp_4_(.in(fire_both_), .mc(mc), .pred(m1cate_2__F_));
- driversM__predDri20wMC pp_5_(.in(fire_both_), .mc(mc), .pred(m1cate_3__T_));
- driversM__predDri20wMC pp_6_(.in(fire_both_), .mc(mc), .pred(m1cate_3__F_));
- driversM__predDri20wMC pp_7_(.in(fire_both_), .mc(mc), .pred(m1cate_4__T_));
- driversM__predDri20wMC pp_8_(.in(fire_both_), .mc(mc), .pred(m1cate_4__F_));
- driversM__predDri20wMC pp_9_(.in(fire_both_), .mc(mc), .pred(m1cate_5__T_));
- driversM__predDri20wMC pp_10_(.in(fire_both_), .mc(mc),
- .pred(m1cate_5__F_));
- driversM__predDri20wMC pp_11_(.in(fire_both_), .mc(mc),
- .pred(m1cate_6__T_));
- driversM__predDri20wMC pp_12_(.in(fire_both_), .mc(mc),
- .pred(m1cate_6__F_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_18));
- orangeTSMC090nm__wire90 wire90_3(.a(net_49));
- orangeTSMC090nm__wire90 wire90_4(.a(net_62));
- orangeTSMC090nm__wire90 wire90_5(.a(net_67));
-endmodule /* predicateM__ohPredPred */
-
-module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
- flag_B__set_, flag_D__clr_, flag_D__set_, m1_Fl_, m1_rD_, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, ps_Fl_, sin, do_ins_, ps_do_, ps_skip_, sout, mc, p1p, p2p,
- rd);
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input m1_Fl_;
- input m1_rD_;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input ps_Fl_;
- input sin;
- output do_ins_;
- output ps_do_;
- output ps_skip_;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_both_, fire_do_, fire_skip_, net_11, net_19, net_41, net_46, net_63;
- wire net_82, net_92;
- wire [1:3] s;
-
- wiresL__bitAssignments bitAssig_0();
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (fire_do_, net_82);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (fire_skip_, net_63);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (net_41, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (net_63, net_92, net_11);
- // end Verilog_template
- redFive__nand2n_sy nand2n_s_0(.ina(net_63), .inb(net_82), .out(fire_both_));
- predicateM__nand3in20sr nand3in2_1(.inA(net_46), .inB(net_41), .inC(net_11),
- .resetLO(net_19), .out(net_82));
- redFive__nor2n_sy nor2n_sy_0(.ina(ps_skip_), .inb(ps_do_), .out(net_11));
- predicateM__ohPredDo ohPredDo_1(.fire_do_(fire_do_), .fire_skip_(fire_skip_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .m1_Fl_(m1_Fl_), .m1_rD_(m1_rD_), .mc(mc), .ps_Fl_(ps_Fl_),
- .do_ins_(do_ins_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .s({s[3]}));
- predicateM__ohPredPred ohPredPr_1(.fire_both_(fire_both_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .mc(mc),
- .any(net_92), .do(net_46), .resetLO(net_19), .s(s[1:2]));
- scanM__scanEx3h scanEx3h_0(.dIn(s[1:3]), .sin(sin), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- orangeTSMC090nm__wire90 wire90_0(.a(net_11));
- orangeTSMC090nm__wire90 wire90_1(.a(net_41));
- orangeTSMC090nm__wire90 wire90_2(.a(net_46));
- orangeTSMC090nm__wire90 wire90_3(.a(net_19));
- orangeTSMC090nm__wire90 wire90_4(.a(net_82));
- orangeTSMC090nm__wire90 wire90_5(.a(net_63));
- orangeTSMC090nm__wire90 wire90_6(.a(net_92));
- orangeTSMC090nm__wire90 wire90_7(.a(fire_skip_));
- orangeTSMC090nm__wire90 wire90_9(.a(fire_both_));
- orangeTSMC090nm__wire90 wire90_11(.a(fire_do_));
-endmodule /* predicateM__ohPredAll */
-
-module centersJ__ctrAND2in100(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_158, net_161;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_161, net_158);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (out, net_161);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_158));
- orangeTSMC090nm__wire90 wire90_6(.a(net_158));
- orangeTSMC090nm__wire90 wire90_7(.a(net_161));
-endmodule /* centersJ__ctrAND2in100 */
-
-module loopCountM__ilcLoad(do_ins_, sel_Ld_, sel_rD_, ilc_load_);
- input do_ins_;
- input sel_Ld_;
- input sel_rD_;
- output ilc_load_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_12;
-
- centersJ__ctrAND2in100 ctrAND2i_0(.inA(sel_rD_), .inB(net_12),
- .out(ilc_load_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_12, sel_Ld_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(ilc_load_), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_12));
-endmodule /* loopCountM__ilcLoad */
-
-module driversM__sucDri20or(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_94;
-
- /* user-specified Verilog declarations */
- wor succ;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_94, succ);
- // end Verilog_template
- redFive__nms3 nms3b_0(.g(net_94), .g2(inB), .g3(inA), .d(succ));
- redFive__pms1 pms1_0(.g(inA), .d(succ));
- redFive__pms1 pms1_1(.g(inB), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_94));
-endmodule /* driversM__sucDri20or */
-
-module loopCountM__olcControlD(fire_Co_, fire_zz_, olc_zero_, olc_zoo_,
- flag_D__clr_, flag_D__set_, s);
- input fire_Co_;
- input fire_zz_;
- input olc_zero_;
- input olc_zoo_;
- output flag_D__clr_;
- output flag_D__set_;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_180, net_184, net_279, net_281, net_284, net_286, net_544, net_549;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (net_180, olc_zoo_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_7 (net_184, olc_zero_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_18 (net_549, flag_D__set_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_19 (net_544, flag_D__clr_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[2], net_544);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[1], net_549);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_286, net_180, fire_Co_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_284, net_184, fire_zz_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_279, olc_zoo_, fire_Co_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_3 (net_281, olc_zero_, fire_zz_);
- // end Verilog_template
- driversM__sucDri20or sucDri20_3(.inA(net_286), .inB(net_284),
- .succ(flag_D__clr_));
- driversM__sucDri20or sucDri20_4(.inA(net_279), .inB(net_281),
- .succ(flag_D__set_));
- orangeTSMC090nm__wire90 wire90_9(.a(net_281));
- orangeTSMC090nm__wire90 wire90_10(.a(net_279));
- orangeTSMC090nm__wire90 wire90_11(.a(net_286));
- orangeTSMC090nm__wire90 wire90_12(.a(net_284));
- orangeTSMC090nm__wire90 wire90_13(.a(net_180));
- orangeTSMC090nm__wire90 wire90_14(.a(net_184));
- orangeTSMC090nm__wire90 wire90_21(.a(net_549));
- orangeTSMC090nm__wire90 wire90_22(.a(net_544));
-endmodule /* loopCountM__olcControlD */
-
-module loopCountM__olcCount(do_ins_, olc_zero_, sel_Co_, fire_Co_, olc_dec_);
- input do_ins_;
- input olc_zero_;
- input sel_Co_;
- output fire_Co_;
- output olc_dec_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_12;
-
- centersJ__ctrAND1in30 ctrAND1i_0(.in(net_12), .out(fire_Co_));
- centersJ__ctrAND2in100 ctrAND2i_0(.inA(olc_zero_), .inB(net_12),
- .out(olc_dec_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_12, sel_Co_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(fire_Co_), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_12));
-endmodule /* loopCountM__olcCount */
-
-module driversM__predDri10wMC(in, mc, pred);
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_145, pred);
- // end Verilog_template
- redFive__pms3 pms3_0(.g(in), .g2(net_145), .g3(mc), .d(pred));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
-endmodule /* driversM__predDri10wMC */
-
-module driversM__sucDri10(in, succ);
- input in;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_109, net_94;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_94, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_109, in);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_94), .g2(net_109), .d(succ));
- redFive__pms1 pms1_0(.g(net_109), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_94));
- orangeTSMC090nm__wire90 wire90_1(.a(net_109));
-endmodule /* driversM__sucDri10 */
-
-module loopCountM__olcLoad(do_ins_, doneLO_M_, mc, sel_Ld_, sel_rD_, fire_zz_,
- olc_load_);
- input do_ins_;
- input doneLO_M_;
- input mc;
- input sel_Ld_;
- input sel_rD_;
- output fire_zz_;
- output olc_load_;
-
- supply1 vdd;
- supply0 gnd;
- wire inv_34_out, net_1035, net_905, net_908, net_929, net_937, net_956;
- wire net_976;
- wire [2:2] do;
-
- centersJ__ctrAND3in100A ctrAND3i_2(.inA(do[2]), .inB(net_976), .inC(net_956),
- .out(olc_load_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_28 (net_908, net_905);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_30 (net_976, sel_rD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_32 (net_1035, net_937);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_34 (inv_34_out, net_905);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_7 (net_905, net_929);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_8 (net_937, net_908);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_5 (net_956, sel_Ld_, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_7 (net_929, net_1035, do[2]);
- // end Verilog_template
- redFive__nand2n_sy nand2n_s_1(.ina(doneLO_M_), .inb(net_908),
- .out(fire_zz_));
- driversM__predDri10wMC predDri1_0(.in(net_956), .mc(mc), .pred(do[2]));
- driversM__predDri40 predDri4_0(.in(net_937), .pred(do_ins_));
- driversM__sucDri10 sucDri10_1(.in(olc_load_), .succ(do[2]));
- orangeTSMC090nm__wire90 wire90_17(.a(net_929));
- orangeTSMC090nm__wire90 wire90_25(.a(net_956));
- orangeTSMC090nm__wire90 wire90_39(.a(net_937));
- orangeTSMC090nm__wire90 wire90_42(.a(net_905));
- orangeTSMC090nm__wire90 wire90_48(.a(net_976));
- orangeTSMC090nm__wire90 wire90_50(.a(do[2]));
- orangeTSMC090nm__wire90 wire90_51(.a(net_1035));
- orangeTSMC090nm__wire90 wire90_52(.a(net_908));
-endmodule /* loopCountM__olcLoad */
-
-module loopCountM__loadORcount(do_ins_, doneLO_M_, mc, olc_zero_, olc_zoo_,
- sel_Co_, sel_Ld_, sel_rD_, flag_D__clr_, flag_D__set_, ilc_load_,
- olc_dec_, olc_load_, s);
- input do_ins_;
- input doneLO_M_;
- input mc;
- input olc_zero_;
- input olc_zoo_;
- input sel_Co_;
- input sel_Ld_;
- input sel_rD_;
- output flag_D__clr_;
- output flag_D__set_;
- output ilc_load_;
- output olc_dec_;
- output olc_load_;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_880, net_883;
-
- loopCountM__ilcLoad ilcLoad_0(.do_ins_(do_ins_), .sel_Ld_(sel_Ld_),
- .sel_rD_(sel_rD_), .ilc_load_(ilc_load_));
- loopCountM__olcControlD olcContr_1(.fire_Co_(net_883), .fire_zz_(net_880),
- .olc_zero_(olc_zero_), .olc_zoo_(olc_zoo_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .s(s[1:2]));
- loopCountM__olcCount olcCount_0(.do_ins_(do_ins_), .olc_zero_(olc_zero_),
- .sel_Co_(sel_Co_), .fire_Co_(net_883), .olc_dec_(olc_dec_));
- loopCountM__olcLoad olcLoad_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
- .mc(mc), .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .fire_zz_(net_880),
- .olc_load_(olc_load_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_880));
- orangeTSMC090nm__wire90 wire90_1(.a(net_883));
-endmodule /* loopCountM__loadORcount */
-
-module loopCountM__olcEven(count_T_, do, do_1, do_2, \inLO[2] , \inLO[4] ,
- \inLO[6] , load_T_, \bitt[2] , \bitt[4] , \bitt[6] );
- input count_T_;
- input [2:2] do;
- input [4:4] do_1;
- input [6:6] do_2;
- input \inLO[2] , \inLO[4] , \inLO[6] ;
- input load_T_;
- output \bitt[2] , \bitt[4] , \bitt[6] ;
-
- supply1 vdd;
- supply0 gnd;
- wire count_F_, load_F_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_2 (count_F_, count_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_3 (load_F_, load_T_);
- // end Verilog_template
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_2[6:6]), .inLO({ \inLO[6] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[6] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[4:4]), .inLO({ \inLO[4] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[4] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[2:2]), .inLO({ \inLO[2] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[2] }));
- orangeTSMC090nm__wire90 wire90_3(.a(count_F_));
- orangeTSMC090nm__wire90 wire90_4(.a(load_F_));
-endmodule /* loopCountM__olcEven */
-
-module loopCountM__olcOdd(count_T_, do, do_1, \inLO[1] , \inLO[3] , \inLO[5] ,
- load_T_, \bitt[1] , \bitt[3] , \bitt[5] );
- input count_T_;
- input [3:3] do;
- input [5:5] do_1;
- input \inLO[1] , \inLO[3] , \inLO[5] ;
- input load_T_;
- output \bitt[1] , \bitt[3] , \bitt[5] ;
-
- supply1 vdd;
- supply0 gnd;
- wire count_F_, load_F_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_2 (load_F_, load_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_3 (count_F_, count_T_);
- // end Verilog_template
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[5:5]), .inLO({ \inLO[5] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[5] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[3:3]), .inLO({ \inLO[3] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[3] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do({vdd}), .inLO({ \inLO[1] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[1] }));
- orangeTSMC090nm__wire90 wire90_2(.a(load_F_));
- orangeTSMC090nm__wire90 wire90_3(.a(count_F_));
-endmodule /* loopCountM__olcOdd */
-
-module loopCountM__olc(inLO, olc_dec_, olc_load_, bitt, olc_zero_, olc_zoo_);
- input [1:6] inLO;
- input olc_dec_;
- input olc_load_;
- output [1:6] bitt;
- output olc_zero_;
- output olc_zoo_;
-
- supply1 vdd;
- supply0 gnd;
- wire [6:2] do;
-
- loopCountM__calculate countLog_0(.bit({bitt[1]}), .bit_1({bitt[2]}),
- .bit_2({bitt[3]}), .bit_3({bitt[4]}), .bit_4({bitt[5]}),
- .bit_5({bitt[6]}), .do(do[2:2]), .do_1(do[3:3]), .do_2(do[4:4]),
- .do_3(do[5:5]), .do_4(do[6:6]), .zero(olc_zero_), .zoo(olc_zoo_));
- loopCountM__olcEven olcEven_1(.count_T_(olc_dec_), .do(do[2:2]),
- .do_1(do[4:4]), .do_2(do[6:6]), .\inLO[2] (inLO[2]), .\inLO[4] (inLO[4]),
- .\inLO[6] (inLO[6]), .load_T_(olc_load_), .\bitt[2] (bitt[2]), .\bitt[4]
- (bitt[4]), .\bitt[6] (bitt[6]));
- loopCountM__olcOdd olcOdd_2(.count_T_(olc_dec_), .do(do[3:3]),
- .do_1(do[5:5]), .\inLO[1] (inLO[1]), .\inLO[3] (inLO[3]), .\inLO[5]
- (inLO[5]), .load_T_(olc_load_), .\bitt[1] (bitt[1]), .\bitt[3] (bitt[3]),
- .\bitt[5] (bitt[5]));
- orangeTSMC090nm__wire90 wire90_1(.a(do[2]));
- orangeTSMC090nm__wire90 wire90_2(.a(do[3]));
- orangeTSMC090nm__wire90 wire90_3(.a(do[4]));
- orangeTSMC090nm__wire90 wire90_4(.a(do[5]));
- orangeTSMC090nm__wire90 wire90_5(.a(do[6]));
-endmodule /* loopCountM__olc */
-
-module loopCountM__olcWcont(do_ins_, doneLO_M_, inLO, sel_Co_, sel_Ld_,
- sel_rD_, sin, flag_D__clr_, flag_D__set_, ilc_load_, sout, mc, p1p, p2p,
- rd);
- input do_ins_;
- input doneLO_M_;
- input [1:6] inLO;
- input sel_Co_;
- input sel_Ld_;
- input sel_rD_;
- input sin;
- output flag_D__clr_;
- output flag_D__set_;
- output ilc_load_;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_46, net_81, olc_dec_, olc_load_, olc_zero_, olc_zoo_;
- wire [1:6] bitt;
- wire [1:2] s;
-
- loopCountM__loadORcount loadORco_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
- .mc(mc), .olc_zero_(olc_zero_), .olc_zoo_(olc_zoo_), .sel_Co_(sel_Co_),
- .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .olc_dec_(olc_dec_),
- .olc_load_(olc_load_), .s(s[1:2]));
- loopCountM__olc olc_0(.inLO(inLO[1:6]), .olc_dec_(olc_dec_),
- .olc_load_(olc_load_), .bitt(bitt[1:6]), .olc_zero_(olc_zero_),
- .olc_zoo_(olc_zoo_));
- scanM__scanEx2h scanEx2h_0(.dIn(s[1:2]), .sin(net_81), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx3h scanEx3h_1(.dIn({bitt[1], bitt[3], bitt[5]}), .sin(sin),
- .mc(mc), .sout(net_46), .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx3h scanEx3h_2(.dIn({bitt[2], bitt[4], bitt[6]}), .sin(net_46),
- .mc(mc), .sout(net_81), .p1p(p1p), .p2p(p2p), .rd(rd));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- orangeTSMC090nm__wire90 wire90_1(.a(olc_zero_));
- orangeTSMC090nm__wire90 wire90_2(.a(olc_zoo_));
- orangeTSMC090nm__wire90 wire90_3(.a(olc_load_));
- orangeTSMC090nm__wire90 wire90_4(.a(olc_dec_));
- orangeTSMC090nm__wire90 wire90_5(.a(bitt[4]));
- orangeTSMC090nm__wire90 wire90_6(.a(bitt[5]));
- orangeTSMC090nm__wire90 wire90_7(.a(bitt[6]));
- orangeTSMC090nm__wire90 wire90_8(.a(bitt[1]));
- orangeTSMC090nm__wire90 wire90_9(.a(bitt[2]));
- orangeTSMC090nm__wire90 wire90_10(.a(bitt[3]));
-endmodule /* loopCountM__olcWcont */
-
-module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
- \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , \m1[1] , \m1[2] ,
- \m1[3] , \m1[4] , \m1[5] , \m1[6] , \m1[7] , \m1[8] , \m1[9] , \m1[10] ,
- \m1[11] , \m1[12] , \m1[21] , \m1[22] , m1cate_1__F_, m1cate_1__T_,
- m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_,
- m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_,
- pred_D_, pred_T_, ps, sir, succ_sf_, do_ins_, fire_M_, flag_A__clr_,
- flag_A__set_, flag_D__clr_, flag_D__set_, ps_do_, ps_skip_, sor);
- input epi_torp_;
- input flag_C__T_;
- input [1:6] in;
- input \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] ;
- input \m1[1] , \m1[2] , \m1[3] , \m1[4] , \m1[5] , \m1[6] , \m1[7] , \m1[8] ,
- \m1[9] , \m1[10] , \m1[11] , \m1[12] , \m1[21] , \m1[22] ;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input pred_D_;
- input pred_T_;
- input [18:26] ps;
- input [1:9] sir;
- input succ_sf_;
- output do_ins_;
- output fire_M_;
- output flag_A__clr_;
- output flag_A__set_;
- output flag_D__clr_;
- output flag_D__set_;
- output ps_do_;
- output ps_skip_;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire doneLO_M_, flag_B__clr_, flag_B__set_, ilc_load_, net_244, net_249;
- wire net_279;
-
- wiresL__bitAssignments bitAssig_0();
- oneHotM__flags flags_0(.flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_),
- .flag_B__set_(flag_B__set_), .flag_C__T_(flag_C__T_), .m1({ \m1[1] ,
- \m1[2] , \m1[3] , \m1[4] , \m1[5] , \m1[6] , \m1[7] , \m1[8] ,
- \m1[9] , \m1[10] , \m1[11] , \m1[12] }), .sin(sir[1]), .sout(net_279),
- .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- moveM__ilcMoveOut ilcMoveO_0(.do_ins_(do_ins_), .epi_torp_(epi_torp_),
- .ilc_load_(ilc_load_), .\inLO[1] ( \inLO[1] ), .\inLO[2] ( \inLO[2] ),
- .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] ( \inLO[5] ),
- .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .pred_D_(pred_D_),
- .pred_T_(pred_T_), .sel_Di_(ps[18]), .sel_Mv_(ps[25]), .sel_Ti_(ps[19]),
- .sel_Tp_(ps[26]), .sin(net_249), .succ_sf_(succ_sf_),
- .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
- .sout(sor[1]), .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- loopCountM__muxForD muxForD_0(.in(in[1:6]), .sel(ps[20]), .outLO({ \inLO[1] ,
- \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8]
- }));
- predicateM__ohPredAll ohPredAl_0(.flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_),
- .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .m1_Fl_( \m1[22] ), .m1_rD_( \m1[21] ),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_),
- .ps_Fl_(ps[22]), .sin(net_244), .do_ins_(do_ins_), .ps_do_(ps_do_),
- .ps_skip_(ps_skip_), .sout(net_249), .mc(sir[9]), .p1p(sir[3]),
- .p2p(sir[2]), .rd(sir[5]));
- loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
- .inLO({ \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] ,
- \inLO[6] }), .sel_Co_(ps[24]), .sel_Ld_(ps[23]), .sel_rD_(ps[21]),
- .sin(net_279), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .ilc_load_(ilc_load_), .sout(net_244), .mc(sir[9]), .p1p(sir[3]),
- .p2p(sir[2]), .rd(sir[5]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- orangeTSMC090nm__wire90 wire90_5(.a(flag_A__set_));
- orangeTSMC090nm__wire90 wire90_6(.a(flag_A__clr_));
- orangeTSMC090nm__wire90 wire90_7(.a(flag_B__set_));
- orangeTSMC090nm__wire90 wire90_8(.a(flag_B__clr_));
- orangeTSMC090nm__wire90 wire90_9(.a(flag_D__set_));
- orangeTSMC090nm__wire90 wire90_10(.a(flag_D__clr_));
- orangeTSMC090nm__wire90 wire90_24(.a(ilc_load_));
- orangeTSMC090nm__wire90 wire90_25(.a(doneLO_M_));
-endmodule /* stagesM__outDockCenter */
-
-module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, pred_D_, pred_T_, sir, succ_sf_, do_ins_, fire_M_,
- flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, \ps[1] , \ps[2] ,
- \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] , \ps[9] , \ps[10] ,
- \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] , \ps[16] , \ps[17] ,
- \ps[18] , \ps[19] , \ps[20] , \ps[27] , ps_do_, ps_skip_, sor);
- input epi_torp_;
- input flag_C__T_;
- input [1:6] in;
- input [1:27] m1;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input pred_D_;
- input pred_T_;
- input [1:9] sir;
- input succ_sf_;
- output do_ins_;
- output fire_M_;
- output flag_A__clr_;
- output flag_A__set_;
- output flag_D__clr_;
- output flag_D__set_;
- output \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8]
- , \ps[9] , \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] ,
- \ps[16] , \ps[17] , \ps[18] , \ps[19] , \ps[20] , \ps[27] ;
- output ps_do_;
- output ps_skip_;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire \inLO[1] ;
- wire \inLO[2] ;
- wire \inLO[3] ;
- wire \inLO[4] ;
- wire \inLO[5] ;
- wire \inLO[6] ;
- wire \inLO[8] ;
- wire [21:26] ps_1;
-
- registersM__dockPSreg dockPSre_0(.do_ins_(do_ins_), .m1(m1[1:27]), .outLO({
- \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] }), .ps({ \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] ,
- \ps[6] , \ps[7] , \ps[8] , \ps[9] , \ps[10] , \ps[11] , \ps[12] ,
- \ps[13] , \ps[14] , \ps[15] , \ps[16] , \ps[17] , \ps[18] , \ps[19]
- , \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24], ps_1[25], ps_1[26],
- \ps[27] }));
- stagesM__outDockCenter outDockC_0(.epi_torp_(epi_torp_),
- .flag_C__T_(flag_C__T_), .in(in[1:6]), .\inLO[1] ( \inLO[1] ), .\inLO[2]
- ( \inLO[2] ), .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] (
- \inLO[5] ), .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .\m1[1]
- (m1[1]), .\m1[2] (m1[2]), .\m1[3] (m1[3]), .\m1[4] (m1[4]), .\m1[5]
- (m1[5]), .\m1[6] (m1[6]), .\m1[7] (m1[7]), .\m1[8] (m1[8]), .\m1[9]
- (m1[9]), .\m1[10] (m1[10]), .\m1[11] (m1[11]), .\m1[12] (m1[12]),
- .\m1[21] (m1[21]), .\m1[22] (m1[22]), .m1cate_1__F_(m1cate_1__F_),
- .m1cate_1__T_(m1cate_1__T_), .m1cate_2__F_(m1cate_2__F_),
- .m1cate_2__T_(m1cate_2__T_), .m1cate_3__F_(m1cate_3__F_),
- .m1cate_3__T_(m1cate_3__T_), .m1cate_4__F_(m1cate_4__F_),
- .m1cate_4__T_(m1cate_4__T_), .m1cate_5__F_(m1cate_5__F_),
- .m1cate_5__T_(m1cate_5__T_), .m1cate_6__F_(m1cate_6__F_),
- .m1cate_6__T_(m1cate_6__T_), .pred_D_(pred_D_), .pred_T_(pred_T_), .ps({
- \ps[18] , \ps[19] , \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24],
- ps_1[25], ps_1[26]}), .sir(sir[1:9]), .succ_sf_(succ_sf_),
- .do_ins_(do_ins_), .fire_M_(fire_M_), .flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .ps_do_(ps_do_), .ps_skip_(ps_skip_),
- .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_1(.a( \inLO[1] ));
- orangeTSMC090nm__wire90 wire90_2(.a( \inLO[2] ));
- orangeTSMC090nm__wire90 wire90_3(.a( \inLO[3] ));
- orangeTSMC090nm__wire90 wire90_4(.a( \inLO[4] ));
- orangeTSMC090nm__wire90 wire90_5(.a( \inLO[5] ));
- orangeTSMC090nm__wire90 wire90_6(.a( \inLO[6] ));
- orangeTSMC090nm__wire90 wire90_7(.a( \inLO[8] ));
-endmodule /* stagesM__outDockPredStage */
-
-module stageGroupsM__outM1PredLit(dp, dp_B_, epi_torp_, pred_D_, pred_R_,
- pred_T_, ring, signalBitFromInboundSwitchFabric, sir, dsA, dsA_TT_, dsD,
- dsD_1, flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, m1,
- ps_do_, ps_skip_, sor, succ_D_, succ_T_, succ_m1_);
- input [1:37] dp;
- input dp_B_;
- input epi_torp_;
- input pred_D_;
- input pred_R_;
- input pred_T_;
- input [1:36] ring;
- input signalBitFromInboundSwitchFabric;
- input [1:9] sir;
- output [14:1] dsA;
- output dsA_TT_;
- output [1:6] dsD;
- output [37:7] dsD_1;
- output flag_A__clr_;
- output flag_A__set_;
- output flag_D__clr_;
- output flag_D__set_;
- output [1:36] m1;
- output ps_do_;
- output ps_skip_;
- output [1:1] sor;
- output succ_D_;
- output succ_T_;
- output succ_m1_;
-
- supply1 vdd;
- supply0 gnd;
- wire do_ins_, fire_M_, flag_C_, m1cate_1__F_, m1cate_1__T_, m1cate_2__F_;
- wire m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_, m1cate_4__T_;
- wire m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_, take_m1_;
- wire [8:8] net_47;
- wire \ps[1] ;
- wire \ps[2] ;
- wire \ps[3] ;
- wire \ps[4] ;
- wire \ps[5] ;
- wire \ps[6] ;
- wire \ps[7] ;
- wire \ps[8] ;
- wire \ps[9] ;
- wire \ps[10] ;
- wire \ps[11] ;
- wire \ps[12] ;
- wire \ps[13] ;
- wire \ps[14] ;
- wire \ps[15] ;
- wire \ps[16] ;
- wire \ps[17] ;
- wire \ps[18] ;
- wire \ps[19] ;
- wire \ps[20] ;
- wire \ps[27] ;
-
- stagesM__litDandP litDandP_0(.do_ins_(do_ins_), .dp(dp[1:37]), .dp_B_(dp_B_),
- .fire_M_(fire_M_), .\ps[1] ( \ps[1] ), .\ps[2] ( \ps[2] ), .\ps[3] (
- \ps[3] ), .\ps[4] ( \ps[4] ), .\ps[5] ( \ps[5] ), .\ps[6] ( \ps[6] ),
- .\ps[7] ( \ps[7] ), .\ps[8] ( \ps[8] ), .\ps[9] ( \ps[9] ), .\ps[10] (
- \ps[10] ), .\ps[11] ( \ps[11] ), .\ps[12] ( \ps[12] ), .\ps[13] ( \ps[13]
- ), .\ps[14] ( \ps[14] ), .\ps[15] ( \ps[15] ), .\ps[16] ( \ps[16] ),
- .\ps[17] ( \ps[17] ), .\ps[18] ( \ps[18] ), .\ps[19] ( \ps[19] ),
- .\ps[20] ( \ps[20] ), .\ps[27] ( \ps[27] ),
- .signalBitFromInboundSwitchFabric(signalBitFromInboundSwitchFabric),
- .dsA(dsA[14:1]), .dsA_TT_(dsA_TT_), .dsD({dsD[1], dsD[2], dsD[3], dsD[4],
- dsD[5], dsD[6], dsD_1[7], dsD_1[8], dsD_1[9], dsD_1[10], dsD_1[11],
- dsD_1[12], dsD_1[13], dsD_1[14], dsD_1[15], dsD_1[16], dsD_1[17],
- dsD_1[18], dsD_1[19], dsD_1[20], dsD_1[21], dsD_1[22], dsD_1[23],
- dsD_1[24], dsD_1[25], dsD_1[26], dsD_1[27], dsD_1[28], dsD_1[29],
- dsD_1[30], dsD_1[31], dsD_1[32], dsD_1[33], dsD_1[34], dsD_1[35],
- dsD_1[36], dsD_1[37]}), .flag_C_(flag_C_), .succ_D_(succ_D_),
- .succ_T_(succ_T_));
- stagesM__mOneDockStage mOneDock_0(.pred_R_(pred_R_), .ring(ring[1:36]),
- .sir(sir[1:9]), .m1(m1[1:36]), .m1cate_1__F_(m1cate_1__F_),
- .m1cate_1__T_(m1cate_1__T_), .m1cate_2__F_(m1cate_2__F_),
- .m1cate_2__T_(m1cate_2__T_), .m1cate_3__F_(m1cate_3__F_),
- .m1cate_3__T_(m1cate_3__T_), .m1cate_4__F_(m1cate_4__F_),
- .m1cate_4__T_(m1cate_4__T_), .m1cate_5__F_(m1cate_5__F_),
- .m1cate_5__T_(m1cate_5__T_), .m1cate_6__F_(m1cate_6__F_),
- .m1cate_6__T_(m1cate_6__T_), .sor({net_47[8]}), .succ_m1_(succ_m1_),
- .take_m1_(take_m1_));
- stagesM__outDockPredStage outDockP_0(.epi_torp_(epi_torp_),
- .flag_C__T_(flag_C_), .in(dsD[1:6]), .m1(m1[1:27]),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_),
- .pred_D_(pred_D_), .pred_T_(pred_T_), .sir({net_47[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .succ_sf_(succ_D_),
- .do_ins_(do_ins_), .fire_M_(fire_M_), .flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .\ps[1] ( \ps[1] ), .\ps[2] ( \ps[2] ),
- .\ps[3] ( \ps[3] ), .\ps[4] ( \ps[4] ), .\ps[5] ( \ps[5] ), .\ps[6] (
- \ps[6] ), .\ps[7] ( \ps[7] ), .\ps[8] ( \ps[8] ), .\ps[9] ( \ps[9] ),
- .\ps[10] ( \ps[10] ), .\ps[11] ( \ps[11] ), .\ps[12] ( \ps[12] ),
- .\ps[13] ( \ps[13] ), .\ps[14] ( \ps[14] ), .\ps[15] ( \ps[15] ),
- .\ps[16] ( \ps[16] ), .\ps[17] ( \ps[17] ), .\ps[18] ( \ps[18] ),
- .\ps[19] ( \ps[19] ), .\ps[20] ( \ps[20] ), .\ps[27] ( \ps[27] ),
- .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(flag_C_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_M_));
- orangeTSMC090nm__wire90 wire90_2(.a(do_ins_));
- orangeTSMC090nm__wire90 wire90_3(.a(m1cate_1__T_));
- orangeTSMC090nm__wire90 wire90_4(.a(m1cate_1__F_));
- orangeTSMC090nm__wire90 wire90_5(.a(m1cate_2__T_));
- orangeTSMC090nm__wire90 wire90_6(.a(m1cate_2__F_));
- orangeTSMC090nm__wire90 wire90_7(.a(m1cate_3__T_));
- orangeTSMC090nm__wire90 wire90_8(.a(m1cate_3__F_));
- orangeTSMC090nm__wire90 wire90_9(.a(m1cate_4__T_));
- orangeTSMC090nm__wire90 wire90_10(.a(m1cate_4__F_));
- orangeTSMC090nm__wire90 wire90_11(.a(m1cate_5__T_));
- orangeTSMC090nm__wire90 wire90_12(.a(m1cate_5__F_));
- orangeTSMC090nm__wire90 wire90_13(.a(m1cate_6__T_));
- orangeTSMC090nm__wire90 wire90_14(.a(m1cate_6__F_));
-endmodule /* stageGroupsM__outM1PredLit */
-
-module dockM__outputDock(do_epi_, dp, dp_B_, in, in_T_, pred_D_, pred_T_,
- signalBitFromInboundSwitchFabric, sir, dsA, dsA_TT_, dsD, fout, sor,
- succ_D_, succ_T_);
- input do_epi_;
- input [1:37] dp;
- input dp_B_;
- input [1:36] in;
- input in_T_;
- input pred_D_;
- input pred_T_;
- input signalBitFromInboundSwitchFabric;
- input [1:9] sir;
- output [14:1] dsA;
- output dsA_TT_;
- output [37:1] dsD;
- output fout;
- output [1:1] sor;
- output succ_D_;
- output succ_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, net_15, net_84;
- wire net_88, ps_do_, ps_skip_, torp;
- wire [35:0] net_26;
- wire [35:0] net_57;
- wire [35:0] net_68;
- wire [8:8] net_75;
- wire [8:8] net_76;
-
- stageGroupsM__dockWagNine dockWagN_0(.in({net_26[35], net_26[34], net_26[33],
- net_26[32], net_26[31], net_26[30], net_26[29], net_26[28], net_26[27],
- net_26[26], net_26[25], net_26[24], net_26[23], net_26[22], net_26[21],
- net_26[20], net_26[19], net_26[18], net_26[17], net_26[16], net_26[15],
- net_26[14], net_26[13], net_26[12], net_26[11], net_26[10], net_26[9],
- net_26[8], net_26[7], net_26[6], net_26[5], net_26[4], net_26[3],
- net_26[2], net_26[1], net_26[0]}), .pred(net_15), .sir({net_75[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .out({net_57[35], net_57[34], net_57[33], net_57[32], net_57[31],
- net_57[30], net_57[29], net_57[28], net_57[27], net_57[26], net_57[25],
- net_57[24], net_57[23], net_57[22], net_57[21], net_57[20], net_57[19],
- net_57[18], net_57[17], net_57[16], net_57[15], net_57[14], net_57[13],
- net_57[12], net_57[11], net_57[10], net_57[9], net_57[8], net_57[7],
- net_57[6], net_57[5], net_57[4], net_57[3], net_57[2], net_57[1],
- net_57[0]}), .sor({net_76[8]}), .succ(net_84), .take({fout}));
- stageGroupsM__epiRQod epiRQod_1(.do_epi_(do_epi_), .do_od_(net_88),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .in(in[1:36]),
- .in_T_(in_T_), .m1({net_68[35], net_68[34], net_68[33], net_68[32],
- net_68[31], net_68[30], net_68[29], net_68[28], net_68[27], net_68[26],
- net_68[25], net_68[24], net_68[23], net_68[22], net_68[21], net_68[20],
- net_68[19], net_68[18], net_68[17], net_68[16], net_68[15], net_68[14],
- net_68[13], net_68[12], net_68[11], net_68[10], net_68[9], net_68[8],
- net_68[7], net_68[6], net_68[5], net_68[4], net_68[3], net_68[2],
- net_68[1], net_68[0]}), .ps_do_(ps_do_), .ps_skip_(ps_skip_),
- .sir(sir[1:9]), .epi_TORP_(torp), .rq({net_26[35], net_26[34],
- net_26[33], net_26[32], net_26[31], net_26[30], net_26[29], net_26[28],
- net_26[27], net_26[26], net_26[25], net_26[24], net_26[23], net_26[22],
- net_26[21], net_26[20], net_26[19], net_26[18], net_26[17], net_26[16],
- net_26[15], net_26[14], net_26[13], net_26[12], net_26[11], net_26[10],
- net_26[9], net_26[8], net_26[7], net_26[6], net_26[5], net_26[4],
- net_26[3], net_26[2], net_26[1], net_26[0]}), .rq_succ_(net_15),
- .sor({net_75[8]}));
- stageGroupsM__outM1PredLit outM1Pre_0(.dp(dp[1:37]), .dp_B_(dp_B_),
- .epi_torp_(torp), .pred_D_(pred_D_), .pred_R_(net_84), .pred_T_(pred_T_),
- .ring({net_57[35], net_57[34], net_57[33], net_57[32], net_57[31],
- net_57[30], net_57[29], net_57[28], net_57[27], net_57[26], net_57[25],
- net_57[24], net_57[23], net_57[22], net_57[21], net_57[20], net_57[19],
- net_57[18], net_57[17], net_57[16], net_57[15], net_57[14], net_57[13],
- net_57[12], net_57[11], net_57[10], net_57[9], net_57[8], net_57[7],
- net_57[6], net_57[5], net_57[4], net_57[3], net_57[2], net_57[1],
- net_57[0]}),
- .signalBitFromInboundSwitchFabric(signalBitFromInboundSwitchFabric),
- .sir({net_76[8], sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8],
- sir[9]}), .dsA(dsA[14:1]), .dsA_TT_(dsA_TT_), .dsD({dsD[1], dsD[2],
- dsD[3], dsD[4], dsD[5], dsD[6]}), .dsD_1(dsD[37:7]),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .m1({net_68[35], net_68[34], net_68[33], net_68[32], net_68[31],
- net_68[30], net_68[29], net_68[28], net_68[27], net_68[26], net_68[25],
- net_68[24], net_68[23], net_68[22], net_68[21], net_68[20], net_68[19],
- net_68[18], net_68[17], net_68[16], net_68[15], net_68[14], net_68[13],
- net_68[12], net_68[11], net_68[10], net_68[9], net_68[8], net_68[7],
- net_68[6], net_68[5], net_68[4], net_68[3], net_68[2], net_68[1],
- net_68[0]}), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sor(sor[1:1]),
- .succ_D_(succ_D_), .succ_T_(succ_T_), .succ_m1_(net_88));
- orangeTSMC090nm__wire90 wire90_1(.a(net_84));
- orangeTSMC090nm__wire90 wire90_2(.a(torp));
- orangeTSMC090nm__wire90 wire90_3(.a(net_88));
- orangeTSMC090nm__wire90 wire90_4(.a(net_15));
-endmodule /* dockM__outputDock */
-
-module centersJ__ctrAND3in100LT(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_104, net_130, net_138;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (out, net_104);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_138, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
- nand (strong0, strong1) #(100) nand2LT__0 (net_104, net_138, net_130);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_130));
- orangeTSMC090nm__wire90 wire90_0(.a(net_130));
- orangeTSMC090nm__wire90 wire90_4(.a(net_104));
- orangeTSMC090nm__wire90 wire90_5(.a(net_138));
-endmodule /* centersJ__ctrAND3in100LT */
-
-module gaspM__gaspTap(mc, pred, to_A_, to_B_, tok, fire, s, succ_A_, succ_B_,
- take);
- input mc;
- input pred;
- input to_A_;
- input to_B_;
- input tok;
- output fire;
- output [1:1] s;
- output succ_A_;
- output succ_B_;
- output take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_163;
-
- centersJ__ctrAND3in100LT ctrAND3i_0(.inA(succ_A_), .inB(succ_B_),
- .inC(net_163), .out(fire));
- driversM__dataDriver60 dataDriv_0(.inA(tok), .inB(fire), .out(take));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_163, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_163);
- // end Verilog_template
- driversM__predDri60wMC predDri6_1(.in(fire), .mc(mc), .pred(pred));
- driversM__sucANDdri60 sucANDdr_2(.inA(to_A_), .inB(fire), .succ(succ_A_));
- driversM__sucANDdri60 sucANDdr_3(.inA(to_B_), .inB(fire), .succ(succ_B_));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- orangeTSMC090nm__wire90 wire90_0(.a(net_163));
-endmodule /* gaspM__gaspTap */
-
-module scanM__scanFx2(dout, dout_1, sic, soc);
- output [1:1] dout;
- output [2:2] dout_1;
- inout [1:9] sic;
- inout [1:1] soc;
-
- supply1 vdd;
- supply0 gnd;
- wire net_30;
-
- scanM__scanCellF scanCell_3(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]),
- .sout(net_30));
- scanM__scanCellF scanCell_4(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]),
- .sout(soc[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_30));
-endmodule /* scanM__scanFx2 */
-
-module stagesM__tapStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ_A_,
- succ_B_, sic, sir, soc, sor);
- input [14:1] ain;
- input ain_TT_;
- input [1:37] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output [1:37] out;
- output succ_A_;
- output succ_B_;
- inout [1:9] sic;
- inout [1:9] sir;
- inout [1:1] soc;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_0, net_3, net_54, to_A_, to_B_;
-
- registersM__addr1in60Cx15 addr1in6_0(.ain({ain[1], ain[2], ain[3], ain[4],
- ain[5], ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12],
- ain[13], ain[14]}), .ain_TT_(ain_TT_), .fire(net_0), .aout({aout[1],
- aout[2], aout[3], aout[4], aout[5], aout[6], aout[7], aout[8], aout[9],
- aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- registersM__data1in60Cx37 data1in6_0(.in(in[1:37]), .take(net_3),
- .out(out[1:37]));
- gaspM__gaspTap gaspTap_0(.mc(sir[9]), .pred(pred), .to_A_(to_A_),
- .to_B_(to_B_), .tok(ain_TT_), .fire(net_0), .s({net_54}),
- .succ_A_(succ_A_), .succ_B_(succ_B_), .take(net_3));
- scanM__scanEx1 scanEx1_0(.dIn({net_54}), .sir(sir[1:9]), .sor(sor[1:1]));
- scanM__scanFx2 scanFx2_0(.dout({to_A_}), .dout_1({to_B_}), .sic(sic[1:9]),
- .soc(soc[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
-endmodule /* stagesM__tapStage */
-
-module stageGroupsM__tapPropStop(ain, ain_TT_, cin, fin, in, pred, aout,
- aout_TT_, fout, out, succ_A_, succ_B_, sic, sid, sir, soc, sod, sor);
- input [14:1] ain;
- input ain_TT_;
- input cin;
- input fin;
- input [37:1] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output fout;
- output [37:1] out;
- output succ_A_;
- output succ_B_;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_85, net_91, properSt_1_fire;
- wire [8:8] net_100;
- wire [8:8] net_101;
- wire [8:8] net_105;
- wire [51:0] net_107;
-
- countersL__instructionCount instruct_0(.cin(cin), .count(net_91), .fin(fin),
- .fout(fout), .sid({net_105[8], sod[2], sod[3], sod[4], sod[5], sid[6],
- sid[7], sid[8], sid[9]}), .sod(sod[1:1]));
- stageGroupsM__properStopper properSt_1(.ain(ain[14:1]), .ain_TT_(ain_TT_),
- .in(in[37:1]), .pred(pred), .aout({net_107[37], net_107[38], net_107[39],
- net_107[40], net_107[41], net_107[42], net_107[43], net_107[44],
- net_107[45], net_107[46], net_107[47], net_107[48], net_107[49],
- net_107[50]}), .aout_TT_(net_107[51]), .extra(net_91),
- .fire(properSt_1_fire), .out({net_107[0], net_107[1], net_107[2],
- net_107[3], net_107[4], net_107[5], net_107[6], net_107[7], net_107[8],
- net_107[9], net_107[10], net_107[11], net_107[12], net_107[13],
- net_107[14], net_107[15], net_107[16], net_107[17], net_107[18],
- net_107[19], net_107[20], net_107[21], net_107[22], net_107[23],
- net_107[24], net_107[25], net_107[26], net_107[27], net_107[28],
- net_107[29], net_107[30], net_107[31], net_107[32], net_107[33],
- net_107[34], net_107[35], net_107[36]}), .succ(net_85), .sic(sic[1:9]),
- .sid(sid[1:9]), .sir(sir[1:9]), .soc({net_100[8], soc[2], soc[3], soc[4],
- soc[5]}), .sod({net_105[8], sod[2], sod[3], sod[4], sod[5]}),
- .sor({net_101[8], sor[2], sor[3], sor[4], sor[5]}));
- stagesM__tapStage tapStage_2(.ain({net_107[37], net_107[38], net_107[39],
- net_107[40], net_107[41], net_107[42], net_107[43], net_107[44],
- net_107[45], net_107[46], net_107[47], net_107[48], net_107[49],
- net_107[50]}), .ain_TT_(net_107[51]), .in({net_107[36], net_107[35],
- net_107[34], net_107[33], net_107[32], net_107[31], net_107[30],
- net_107[29], net_107[28], net_107[27], net_107[26], net_107[25],
- net_107[24], net_107[23], net_107[22], net_107[21], net_107[20],
- net_107[19], net_107[18], net_107[17], net_107[16], net_107[15],
- net_107[14], net_107[13], net_107[12], net_107[11], net_107[10],
- net_107[9], net_107[8], net_107[7], net_107[6], net_107[5], net_107[4],
- net_107[3], net_107[2], net_107[1], net_107[0]}), .pred(net_85),
- .aout(aout[14:1]), .aout_TT_(aout_TT_), .out({out[1], out[2], out[3],
- out[4], out[5], out[6], out[7], out[8], out[9], out[10], out[11],
- out[12], out[13], out[14], out[15], out[16], out[17], out[18], out[19],
- out[20], out[21], out[22], out[23], out[24], out[25], out[26], out[27],
- out[28], out[29], out[30], out[31], out[32], out[33], out[34], out[35],
- out[36], out[37]}), .succ_A_(succ_A_), .succ_B_(succ_B_),
- .sic({net_100[8], soc[2], soc[3], soc[4], soc[5], sic[6], sic[7], sic[8],
- sic[9]}), .sir({net_101[8], sor[2], sor[3], sor[4], sor[5], sir[6],
- sir[7], sir[8], sir[9]}), .soc(soc[1:1]), .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_2(.a(net_85));
-endmodule /* stageGroupsM__tapPropStop */
-
-module stageGroupsM__southFifo(cin, fin, aout, aout_TT_, fout, out, succ_tap_,
- sic, sid, sir, soc, sod, sor);
- input cin;
- input fin;
- output [14:1] aout;
- output aout_TT_;
- output fout;
- output [37:1] out;
- output succ_tap_;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_53, net_58, net_61;
- wire [8:8] net_64;
- wire [51:0] net_77;
- wire [51:0] net_79;
-
- stageGroupsM__tapPropStop tapPropS_1(.ain({net_79[37], net_79[38],
- net_79[39], net_79[40], net_79[41], net_79[42], net_79[43], net_79[44],
- net_79[45], net_79[46], net_79[47], net_79[48], net_79[49], net_79[50]}),
- .ain_TT_(net_79[51]), .cin(cin), .fin(fin), .in({net_79[0], net_79[1],
- net_79[2], net_79[3], net_79[4], net_79[5], net_79[6], net_79[7],
- net_79[8], net_79[9], net_79[10], net_79[11], net_79[12], net_79[13],
- net_79[14], net_79[15], net_79[16], net_79[17], net_79[18], net_79[19],
- net_79[20], net_79[21], net_79[22], net_79[23], net_79[24], net_79[25],
- net_79[26], net_79[27], net_79[28], net_79[29], net_79[30], net_79[31],
- net_79[32], net_79[33], net_79[34], net_79[35], net_79[36]}),
- .pred(net_61), .aout(aout[14:1]), .aout_TT_(aout_TT_), .fout(fout),
- .out(out[37:1]), .succ_A_(net_53), .succ_B_(succ_tap_), .sic(sic[1:9]),
- .sid(sid[1:9]), .sir({net_64[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .soc(soc[1:5]), .sod(sod[1:5]),
- .sor(sor[1:5]));
- stageGroupsM__upDown8weak upDown8w_1(.ainD(aout[14:1]), .ainD_TT_(aout_TT_),
- .ainU({net_77[37], net_77[38], net_77[39], net_77[40], net_77[41],
- net_77[42], net_77[43], net_77[44], net_77[45], net_77[46], net_77[47],
- net_77[48], net_77[49], net_77[50]}), .ainU_TT_(net_77[51]),
- .inD(out[37:1]), .inU({net_77[0], net_77[1], net_77[2], net_77[3],
- net_77[4], net_77[5], net_77[6], net_77[7], net_77[8], net_77[9],
- net_77[10], net_77[11], net_77[12], net_77[13], net_77[14], net_77[15],
- net_77[16], net_77[17], net_77[18], net_77[19], net_77[20], net_77[21],
- net_77[22], net_77[23], net_77[24], net_77[25], net_77[26], net_77[27],
- net_77[28], net_77[29], net_77[30], net_77[31], net_77[32], net_77[33],
- net_77[34], net_77[35], net_77[36]}), .predD(net_53), .predU(net_58),
- .aoutD({net_77[37], net_77[38], net_77[39], net_77[40], net_77[41],
- net_77[42], net_77[43], net_77[44], net_77[45], net_77[46], net_77[47],
- net_77[48], net_77[49], net_77[50]}), .aoutD_TT_(net_77[51]),
- .aoutU({net_79[37], net_79[38], net_79[39], net_79[40], net_79[41],
- net_79[42], net_79[43], net_79[44], net_79[45], net_79[46], net_79[47],
- net_79[48], net_79[49], net_79[50]}), .aoutU_TT_(net_79[51]),
- .outD({net_77[0], net_77[1], net_77[2], net_77[3], net_77[4], net_77[5],
- net_77[6], net_77[7], net_77[8], net_77[9], net_77[10], net_77[11],
- net_77[12], net_77[13], net_77[14], net_77[15], net_77[16], net_77[17],
- net_77[18], net_77[19], net_77[20], net_77[21], net_77[22], net_77[23],
- net_77[24], net_77[25], net_77[26], net_77[27], net_77[28], net_77[29],
- net_77[30], net_77[31], net_77[32], net_77[33], net_77[34], net_77[35],
- net_77[36]}), .outU({net_79[0], net_79[1], net_79[2], net_79[3],
- net_79[4], net_79[5], net_79[6], net_79[7], net_79[8], net_79[9],
- net_79[10], net_79[11], net_79[12], net_79[13], net_79[14], net_79[15],
- net_79[16], net_79[17], net_79[18], net_79[19], net_79[20], net_79[21],
- net_79[22], net_79[23], net_79[24], net_79[25], net_79[26], net_79[27],
- net_79[28], net_79[29], net_79[30], net_79[31], net_79[32], net_79[33],
- net_79[34], net_79[35], net_79[36]}), .succD(net_58), .succU(net_61),
- .sir(sir[1:9]), .sor({net_64[8]}));
-endmodule /* stageGroupsM__southFifo */
-
-module stageGroupsM__tokenFIFO(pred, succ, sir, sor);
- input pred;
- output succ;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire aStage_3_fire, aStage_4_fire, aStage_5_fire, net_0, net_2;
- wire [1:3] s;
-
- gaspM__aStage aStage_3(.mc(sir[9]), .pred(pred), .fire(aStage_3_fire),
- .s({s[1]}), .succ(net_0));
- gaspM__aStage aStage_4(.mc(sir[9]), .pred(net_0), .fire(aStage_4_fire),
- .s({s[2]}), .succ(net_2));
- gaspM__aStage aStage_5(.mc(sir[9]), .pred(net_2), .fire(aStage_5_fire),
- .s({s[3]}), .succ(succ));
- scanM__scanEx3h scanEx3h_1(.dIn(s[1:3]), .sin(sir[1]), .mc(sir[9]),
- .sout(sor[1]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
- orangeTSMC090nm__wire90 wire90_1(.a(net_2));
-endmodule /* stageGroupsM__tokenFIFO */
-
-module marinaOutDock(fin, fout, sic, sid, sir);
- input fin;
- output fout;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
-
- supply1 vdd;
- supply0 gnd;
- wire ain_T_, aout_T_, dockPred_D_, dockPred_T_, dockSucc_D_, dockSucc_T_;
- wire dsA_TT_, net_14, net_38, net_44;
- wire [14:1] ain;
- wire [14:1] aout;
- wire [37:1] din;
- wire [14:1] dsA;
- wire [37:1] dsD;
- wire \iout[1] ;
- wire \iout[2] ;
- wire \iout[3] ;
- wire \iout[4] ;
- wire \iout[5] ;
- wire \iout[6] ;
- wire \iout[7] ;
- wire \iout[8] ;
- wire \iout[9] ;
- wire \iout[10] ;
- wire \iout[11] ;
- wire \iout[12] ;
- wire \iout[13] ;
- wire \iout[14] ;
- wire \iout[15] ;
- wire \iout[16] ;
- wire \iout[17] ;
- wire \iout[18] ;
- wire \iout[20] ;
- wire \iout[21] ;
- wire \iout[22] ;
- wire \iout[23] ;
- wire \iout[24] ;
- wire \iout[25] ;
- wire \iout[26] ;
- wire \iout[27] ;
- wire \iout[28] ;
- wire \iout[29] ;
- wire \iout[30] ;
- wire \iout[31] ;
- wire \iout[32] ;
- wire \iout[33] ;
- wire \iout[34] ;
- wire \iout[35] ;
- wire \iout[36] ;
- wire \iout[37] ;
- wire [19:19] iout_1;
- wire [8:4] net_109;
- wire [8:4] net_116;
- wire [8:4] net_117;
- wire [8:8] net_119;
- wire [8:8] net_120;
-
- stageGroupsM__northFifo northFif_1(.ainU(dsA[14:1]), .ainU_TT_(dsA_TT_),
- .fin(net_38), .inU(dsD[37:1]), .predU(dockSucc_D_), .aoutD(ain[14:1]),
- .aoutD_TT_(ain_T_), .fout(fout), .outD(din[37:1]), .succD(dockPred_D_),
- .sic({net_116[8], net_116[7], net_116[6], net_116[5], net_116[4], sic[6],
- sic[7], sic[8], sic[9]}), .sid({net_117[8], net_117[7], net_117[6],
- net_117[5], net_117[4], sid[6], sid[7], sid[8], sid[9]}),
- .sir({net_109[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6],
- sir[7], sir[8], sir[9]}));
- dockM__outputDock outputDo_0(.do_epi_(net_14), .dp({din[1], din[2], din[3],
- din[4], din[5], din[6], din[7], din[8], din[9], din[10], din[11],
- din[12], din[13], din[14], din[15], din[16], din[17], din[18], din[19],
- din[20], din[21], din[22], din[23], din[24], din[25], din[26], din[27],
- din[28], din[29], din[30], din[31], din[32], din[33], din[34], din[35],
- din[36], din[37]}), .dp_B_(ain[6]), .in({ \iout[1] , \iout[2] ,
- \iout[3] , \iout[4] , \iout[5] , \iout[6] , \iout[7] , \iout[8] ,
- \iout[9] , \iout[10] , \iout[11] , \iout[12] , \iout[13] , \iout[14]
- , \iout[15] , \iout[16] , \iout[17] , \iout[18] , \iout[20] ,
- \iout[21] , \iout[22] , \iout[23] , \iout[24] , \iout[25] ,
- \iout[26] , \iout[27] , \iout[28] , \iout[29] , \iout[30] ,
- \iout[31] , \iout[32] , \iout[33] , \iout[34] , \iout[35] ,
- \iout[36] , \iout[37] }), .in_T_(aout_T_), .pred_D_(dockPred_D_),
- .pred_T_(dockPred_T_), .signalBitFromInboundSwitchFabric(ain[14]),
- .sir({net_119[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6],
- sir[7], sir[8], sir[9]}), .dsA(dsA[14:1]), .dsA_TT_(dsA_TT_),
- .dsD(dsD[37:1]), .fout(net_44), .sor({net_120[8]}),
- .succ_D_(dockSucc_D_), .succ_T_(dockSucc_T_));
- stageGroupsM__southFifo southFif_1(.cin(net_44), .fin(fin),
- .aout(aout[14:1]), .aout_TT_(aout_T_), .fout(net_38), .out({ \iout[37] ,
- \iout[36] , \iout[35] , \iout[34] , \iout[33] , \iout[32] ,
- \iout[31] , \iout[30] , \iout[29] , \iout[28] , \iout[27] ,
- \iout[26] , \iout[25] , \iout[24] , \iout[23] , \iout[22] ,
- \iout[21] , \iout[20] , iout_1[19], \iout[18] , \iout[17] , \iout[16]
- , \iout[15] , \iout[14] , \iout[13] , \iout[12] , \iout[11] ,
- \iout[10] , \iout[9] , \iout[8] , \iout[7] , \iout[6] , \iout[5] ,
- \iout[4] , \iout[3] , \iout[2] , \iout[1] }), .succ_tap_(net_14),
- .sic(sic[1:9]), .sid(sid[1:9]), .sir(sir[1:9]), .soc({net_116[8],
- net_116[7], net_116[6], net_116[5], net_116[4]}), .sod({net_117[8],
- net_117[7], net_117[6], net_117[5], net_117[4]}), .sor({net_119[8],
- net_109[7], net_109[6], net_109[5], net_109[4]}));
- stageGroupsM__tokenFIFO tokenFIF_1(.pred(dockSucc_T_), .succ(dockPred_T_),
- .sir({net_120[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6],
- sir[7], sir[8], sir[9]}), .sor({net_109[8]}));
-endmodule /* marinaOutDock */
projects / fleet.git / commitdiff