improve master-clear logic

diff --git a/src/com/sun/vlsi/chips/marina/test/Marina.java b/src/com/sun/vlsi/chips/marina/test/Marina.java
index 8c9cced..f878f47 100644 (file)
--- a/src/com/sun/vlsi/chips/marina/test/Marina.java
+++ b/src/com/sun/vlsi/chips/marina/test/Marina.java
@@ -18,11 +18,24 @@ public class Marina {
     public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE  = 5;
     public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO = MarinaPath.SIGNAL_BIT_INDEX;
 
-    public static final String DATA_CHAIN =    "marina.marina_data";      
-    public static final String CONTROL_CHAIN = "marina.marina_control";
-    public static final String REPORT_CHAIN =  "marina.marina_report";
-        
-    private static String prefix = "marinaGu@0.outDockW@3.marinaOu@1.";
+       
+    public static int TOKEN_FIFO_CAPACITY = 3;
+    
+    public static boolean kesselsCounter = true;
+    //public static boolean kesselsCounter = false;
+
+    public static final String DATA_CHAIN =    kesselsCounter ? "marina.marina_data" : "marina.ivan_data";      
+    public static final String CONTROL_CHAIN = kesselsCounter ? "marina.marina_control" : "marina.ivan_control";
+    public static final String REPORT_CHAIN =  kesselsCounter ? "marina.marina_report" : "marina.ivan_report";
+
+    public static String prefix = "marinaGu@0.outDockW@"+(kesselsCounter?"3":"0")+".marinaOu@"+(kesselsCounter?"1":"0")+".";
+    public static String MASTER_CLEAR = "mc";
+
+
+    /*
+    private static String prefix = "outDockW@"+(kesselsCounter?"3":"0")+".marinaOu@1.";
+    private static String MASTER_CLEAR = "EXTmasterClear";
+    */
 
     private static final String OLC_PATH_EVEN = 
         prefix+"outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.scanEx3h@1"; // bits 2,4,6
@@ -181,13 +194,9 @@ public class Marina {
             vm.setNodeState(prefix+"northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire", 0);
             model.waitNS(1000);
 
-            vm.setNodeState("sid[9]", 1);
-            vm.setNodeState("sic[9]", 1);
-            vm.setNodeState("sir[9]", 1);
+            vm.setNodeState(MASTER_CLEAR, 1);
             model.waitNS(1000);
-            vm.setNodeState("sid[9]", 0);
-            vm.setNodeState("sic[9]", 0);
-            vm.setNodeState("sir[9]", 0);
+            vm.setNodeState(MASTER_CLEAR, 0);
             model.waitNS(1000);
 
             // pulse ilc[load] and olc[load]
@@ -253,9 +262,9 @@ public class Marina {
             nModel.setNodeVoltage(prefix+"sir[9]",0.0);
             nModel.waitNS(1);
             */
-            nModel.setNodeVoltage("mc",1.0);
+            nModel.setNodeVoltage(MASTER_CLEAR,1.0);
             nModel.waitNS(WIDTH);
-            nModel.setNodeVoltage("mc",0.0);
+            nModel.setNodeVoltage(MASTER_CLEAR,0.0);
             nModel.waitNS(1);
         }
         resetAfterMasterClear();
@@ -280,7 +289,7 @@ public class Marina {
         //tokOut.resetAfterMasterClear();
         instrIn.resetAfterMasterClear();
     }
-    public static boolean kesselsCounter = true;
+
 
     /** Get the 6 bit outer loop counter. */
     public int getOLC() {

diff --git a/src/com/sun/vlsi/chips/marina/test/MarinaTest.java b/src/com/sun/vlsi/chips/marina/test/MarinaTest.java
index 4d6f5e2..91a3944 100644 (file)
--- a/src/com/sun/vlsi/chips/marina/test/MarinaTest.java
+++ b/src/com/sun/vlsi/chips/marina/test/MarinaTest.java
@@ -14,6 +14,7 @@ import com.sun.async.test.JtagSubchainTesterModel;
 import com.sun.async.test.JtagTester;
 import com.sun.async.test.ManualPowerChannel;
 import com.sun.async.test.NanosimModel;
+import com.sun.async.test.NanosimLogicSettable;
 import com.sun.async.test.HsimModel;
 import com.sun.async.test.VerilogModel;
 import com.sun.async.test.Netscan4;
@@ -262,20 +263,30 @@ public class MarinaTest {
 
         marina = new Marina(ccs, model, !cmdArgs.jtagShift, indenter);
 
+        if (model instanceof NanosimModel) {
+            NanosimLogicSettable mc = (NanosimLogicSettable)
+                ((SimulationModel)model).createLogicSettable(Marina.MASTER_CLEAR);
+            mc.setInitState(true);
+        }
+
+        prln("starting model");
         if (model instanceof VerilogModel)
             ((SimulationModel)model).start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift);
         else if (model instanceof HsimModel)
             ((SimulationModel)model).start("hsim64", netListName, 0, !cmdArgs.jtagShift);
         else
             ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift);
+        prln("model started");
 
-        /*
-        ccC.resetInBits();
-        ccC.shift(Marina.CONTROL_CHAIN, false, true);
-        */
+        model.waitNS(1000);
+        prln("deasserting master clear");
+        ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0);
+        model.waitNS(1000);
 
-        cc.resetInBits();
-        cc.shift(Marina.CONTROL_CHAIN, false, true);
+        if (cmdArgs.testNum!=0 && cmdArgs.testNum!=1) {
+            cc.resetInBits();
+            cc.shift(Marina.CONTROL_CHAIN, false, true);
+        }
         
         doOneTest(cmdArgs.testNum);