#include "contrib/demo.ships"
-
-0: sendto alu2.op;
-10: sendto alu2.a;
-2: sendto alu2.b;
-
-alu2.a: take, deliver;
-alu2.b: take, deliver;
-alu2.op: take, deliver;
-alu2.out: take, sendto debug.data;
-
-
+10: sendto alu2.a;
+2: sendto alu2.b;
+0: sendto alu2.op;
+0: sendto alu2.op;
+0: sendto alu2.op;
+0: sendto alu2.op;
+alu2.out:
+ take;
+ [2] sendto alu2.a;
+ [2] sendto alu2.b;
+ take, sendto alu2.a;
+ take, sendto alu2.b;
+ take, ack debug.data;
// want: memory, fetch, halt
//#ship alu1 : Alu1
+
#ship alu2 : Alu2
#ship debug : Debug
-#ship command : Command
+#ship execute : Execute
//#ship alu1 : Alu1
-//#ship command : CommandShip
//#ship dup1 : Dup
//#ship dup2 : Dup
//#ship dup3 : Dup
this.noInbox = noInbox;
this.noChannelDef = noChannelDef;
}
+ public DataInbox(InterpreterShip ship, String name, boolean noInbox, boolean noChannelDef, boolean special) {
+ super(ship, name);
+ this.noInbox = noInbox;
+ this.noChannelDef = noChannelDef;
+ this.special = special;
+ }
void addDataFromFabric(int data) {
addItemFromFabric(data);
}
public void writeInstruction(DataOutputStream os, Instruction d) throws IOException {
+ long instr = 0;
+
+ // Kill is encoded as Execute with the illegal combination (Latch & ~DataIn)
+ if (d instanceof Instruction.Kill) {
+ Instruction.Kill k = (Instruction.Kill)d;
+ d = new Instruction.Executable(k.benkoBox, null, k.count, false, false, true, false, false, false);
+ }
+
if (d instanceof Instruction.Executable) {
Instruction.Executable inst = (Instruction.Executable)d;
-
InterpreterBenkoBox dest = resolve(inst.dest);
- long instr = dest==null ? 0 : (dest.addr << 1);
-
+ instr = dest==null ? 0 : (dest.addr << 1);
instr |= (((long)inst.count) << (11+1));
if (inst.tokenIn) instr |= (1L << (11+1+7+0));
- if (inst.dataOut) instr |= (1L << (11+1+7+1));
+ if (inst.dataIn) instr |= (1L << (11+1+7+1));
if (inst.latch) instr |= (1L << (11+1+7+2));
- if (inst.dataIn) instr |= (1L << (11+1+7+3));
+ if (inst.dataOut) instr |= (1L << (11+1+7+3));
if (inst.tokenOut) instr |= (1L << (11+1+7+4));
instr |= ((long)resolve(inst.benkoBox).instr_addr) << (11+5+7+1);
- long out = 0;
- out |= ((InterpreterBenkoBox)ships.get("command").getBenkoBox("data")).addr;
- out |= instr << 11;
- dump(os, (out >> (5*8)) & 0xff);
- dump(os, (out >> (4*8)) & 0xff);
- dump(os, (out >> (3*8)) & 0xff);
- dump(os, (out >> (2*8)) & 0xff);
- dump(os, (out >> (1*8)) & 0xff);
- dump(os, (out >> (0*8)) & 0xff);
+
} else if (d instanceof Instruction.Literal.Absolute) {
Instruction.Literal.Absolute ld = (Instruction.Literal.Absolute)d;
- long out = 0;
- out |= resolve(ld.dest).addr;
- out |= ((long)ld.value) << 11;
- dump(os, (out >> (5*8)) & 0xff);
- dump(os, (out >> (4*8)) & 0xff);
- dump(os, (out >> (3*8)) & 0xff);
- dump(os, (out >> (2*8)) & 0xff);
- dump(os, (out >> (1*8)) & 0xff);
- dump(os, (out >> (0*8)) & 0xff);
+ instr = (2L << (11+24));
+ instr |= (resolve(ld.dest).addr) << 24;
+ instr |= ((long)ld.value);
}
+
+ dump(os, (instr >> (5*8)) & 0xff);
+ dump(os, (instr >> (4*8)) & 0xff);
+ dump(os, (instr >> (3*8)) & 0xff);
+ dump(os, (instr >> (2*8)) & 0xff);
+ dump(os, (instr >> (1*8)) & 0xff);
+ dump(os, (instr >> (0*8)) & 0xff);
}
public void dump(OutputStream os, long data_) throws IOException {
int data = (int)data_;
System.out.println("import ["+ship.getBalsaName()+"]");
}
*/
- System.out.println("module fabric(clk, top_r, top_a, top,");
+ System.out.println("module fabric(clk, data_Execute0_in_r, data_Execute0_in_a, data_Execute0_in,");
System.out.println(" data_Debug0_out_r, data_Debug0_out_a, data_Debug0_out);");
System.out.println(" input clk;");
- System.out.println(" input top_r;");
- System.out.println(" output top_a;");
- System.out.println(" input [(`PACKET_WIDTH-1):0] top;");
+ System.out.println(" input data_Execute0_in_r;");
+ System.out.println(" output data_Execute0_in_a;");
+ System.out.println(" input [(`PACKET_WIDTH-1):0] data_Execute0_in;");
System.out.println(" output data_Debug0_out_r;");
System.out.println(" input data_Debug0_out_a;");
System.out.println(" output [(`PACKET_WIDTH-1):0] data_Debug0_out;");
- System.out.println(" wire [(`INSTRUCTION_WIDTH-1):0] data_Command0_out;");
+ System.out.println(" wire [(`INSTRUCTION_WIDTH-1):0] data_Execute0_ihorn;");
+ System.out.println(" wire [(`PACKET_WIDTH-1):0] data_Execute0_dhorn;");
System.out.println();
System.out.println();
inputs.dumpChannels(true);
for(InterpreterShip ship : shiplist)
for(BenkoBox port : ship.getBenkoBoxes()) {
- if (ship instanceof Command && port instanceof Outbox) continue;
+ if (ship instanceof Execute && port instanceof Outbox) continue;
System.out.println(" wire [(`PACKET_WIDTH-1):0] data_"+getUniqueName(ship)+"_"+port.getName()+";");
}
}
}
- System.out.println("funnel topfun(clk, dest_r, dest_a, dest, source_r, source_a, source, top_r, top_a, top);");
- System.out.println("");
- System.out.println(" assign instruction_r = data_Command0_out_r;");
- System.out.println(" assign data_Command0_out_a = instruction_a;");
- System.out.println(" assign instruction = data_Command0_out;");
+ System.out.println("funnel topfun(clk,"+
+ " dest_r, dest_a, dest,"+
+ " source_r, source_a, source,"+
+ " data_Execute0_dhorn_r, data_Execute0_dhorn_a, data_Execute0_dhorn);");
+ System.out.println("assign instruction_r = data_Execute0_ihorn_r;");
+ System.out.println("assign data_Execute0_ihorn_a = instruction_a;");
+ System.out.println("assign instruction = data_Execute0_ihorn;");
System.out.println("endmodule");
}
+++ /dev/null
-package edu.berkeley.fleet.ships;
-import edu.berkeley.fleet.interpreter.*;
-import edu.berkeley.fleet.*;
-
-import java.util.*;
-import java.io.*;
-
-public class Command extends InterpreterShip {
-
- DataInbox data = new DataInbox(this, "data", true, false);
- DataOutbox out = new DataOutbox(this, "out", true);
-
- public String getBalsaName() { return "command"; }
-
- public Command(Interpreter fleet, String name) {
- super(fleet, name);
- }
-
- public void service() {
- /*
- if (token.tokenReadyForShip()) {
- Log.println(Log.invert(" COMMAND: got a token"+Log.clreol()));
- token.removeTokenForShip();
- }
- */
- if (data.dataReadyForShip())
- Log.println(Log.invert(" COMMAND: got a datum: " + data.removeDataForShip()+Log.clreol()));
- }
-
-}
--- /dev/null
+package edu.berkeley.fleet.ships;
+import edu.berkeley.fleet.interpreter.*;
+import edu.berkeley.fleet.*;
+
+import java.util.*;
+import java.io.*;
+
+public class Execute extends InterpreterShip {
+
+ DataInbox in = new DataInbox(this, "in", true, false, true);
+ DataOutbox ihorn = new DataOutbox(this, "ihorn", true);
+ DataOutbox dhorn = new DataOutbox(this, "dhorn", true);
+
+ public String getBalsaName() { return "execute"; }
+
+ public Execute(Interpreter fleet, String name) {
+ super(fleet, name);
+ }
+
+ public void service() {
+ throw new Error("the Execute ship is only for FPGA simulations");
+ }
+
+}
+++ /dev/null
-`include "macros.v"
-
-module command (clk, data_r, data_a, data_d,
- command_r, command_a, command_d);
- input clk;
-
- input data_r;
- output data_a;
- input [(`DATAWIDTH-1):0] data_d;
-
- output command_r;
- input command_a;
- output [(`INSTRUCTION_WIDTH-1):0] command_d;
-
- assign command_r = data_r;
- assign data_a = command_a;
- assign command_d = data_d;
-
-endmodule
--- /dev/null
+`include "macros.v"
+
+ //RAMB16_S9_S9
+module execute (clk, in_r, in_a_, in_d,
+ ihorn_r_, ihorn_a, ihorn_d_,
+ dhorn_r_, dhorn_a, dhorn_d_
+ );
+ input clk;
+
+ `input(in_r, in_a, in_a_, [(`DATAWIDTH-1):0], in_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+ `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
+
+ reg ihorn_full;
+ reg dhorn_full;
+
+ always @(posedge clk) begin
+ if (ihorn_full) begin
+ `onwrite(ihorn_r, ihorn_a)
+ ihorn_full = 0;
+ end
+ end else if (dhorn_full) begin
+ `onwrite(dhorn_r, dhorn_a)
+ dhorn_full = 0;
+ end
+ end else begin
+ `onread(in_r, in_a)
+ case (in_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+ 0: begin
+ ihorn_full = 1;
+ ihorn_d = in_d;
+ end
+ //01:
+ 2: begin
+ dhorn_full = 1;
+ `packet_data(dhorn_d) = in_d[23:0];
+ `packet_dest(dhorn_d) = in_d[34:24];
+ end
+ //11:
+ endcase
+ end
+ end
+ end
+
+endmodule
+
input out_a;
output in_a;
output out_r;
- input [(`DATAWIDTH-1):0] in_d;
- output [(`DATAWIDTH-1):0] out_d;
+ input [(`PACKET_WIDTH-1):0] in_d;
+ output [(`PACKET_WIDTH-1):0] out_d;
- wire [(`DATAWIDTH-1):0] d12;
- wire [(`DATAWIDTH-1):0] d23;
- wire [(`DATAWIDTH-1):0] d34;
+ wire [(`PACKET_WIDTH-1):0] d12;
+ wire [(`PACKET_WIDTH-1):0] d23;
+ wire [(`PACKET_WIDTH-1):0] d34;
fifostage s1(clk, in_r, in_a, in_d, r12, a12, d12);
fifostage s2(clk, r12, a12, d12, r23, a23, d23);
out_r_, out_a, out_d_);
input clk;
- `input( in_r, in_a, in_a_, [(`DATAWIDTH-1):0], in_d)
- `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
- `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+ `input( in_r, in_a, in_a_, [(`PACKET_WIDTH-1):0], in_d)
+ `output(out_r, out_r_, out_a, [(`PACKET_WIDTH-1):0], out_d_)
+ `defreg(out_d_, [(`PACKET_WIDTH-1):0], out_d)
reg full;
assign fabric_in_data = `packet_data(fabric_in_d);
- fifo4 dfifo(clk, fabric_in_r, fabric_in_a, fabric_in_data,
+ fifo4 dfifo(clk, fabric_in_r, fabric_in_a_, fabric_in_data,
ship_r_, ship_a, ship_d_);
endmodule
`define BENKOBOX_ADDRESS_BITS 11
`define DESTINATION_ADDRESS_BITS 11
`define COUNT_BITS 7
+`define COUNT_WIDTH 7
`define PACKET_WIDTH (`DATAWIDTH + `DESTINATION_ADDRESS_BITS)
`define INSTRUCTION_WIDTH 37
`define instruction_dest_steer(i) i[24]
`define opcode_base (1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS)
-`define instruction_bit_tokenin(instruction) instruction[`opcode_base+4]
-`define instruction_bit_datain(instruction) instruction[`opcode_base+3]
+`define instruction_bit_tokenout(instruction) instruction[`opcode_base+4]
+`define instruction_bit_dataout(instruction) instruction[`opcode_base+3]
`define instruction_bit_latch(instruction) instruction[`opcode_base+2]
-`define instruction_bit_dataout(instruction) instruction[`opcode_base+1]
-`define instruction_bit_tokenout(instruction) instruction[`opcode_base+0]
+`define instruction_bit_datain(instruction) instruction[`opcode_base+1]
+`define instruction_bit_tokenin(instruction) instruction[`opcode_base+0]
`define instruction_bit_dest(instruction) instruction[(`DESTINATION_ADDRESS_BITS):1]
+`define instruction_bit_recycle(instruction) instruction[0]
+`define instruction_is_kill(i) (`instruction_bit_latch(i) && (!(`instruction_bit_datain(i))))
+`define instruction_count(instruction) instruction[(1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS-1):(1+`DESTINATION_ADDRESS_BITS)]
`define defreg(signame,width,regname) reg width regname; wire width signame; assign signame = regname; initial regname = 0;
-`define onread(req, ack) if (!req && ack) ack=0; else if (req && !ack) begin ack=1;
-`define onwrite(out_r, out_a) if (out_r && out_a) out_r = 0; else if (!out_r && !out_a) begin out_r = 1;
`define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d;
`define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d;
+
+`define onread(req, ack) if (!req && ack) ack=0; else if (req && !ack) begin ack=1;
+`define onwrite(req, ack) if (!req && !ack) req = 1; else if (req && ack) begin req = 0;
assign write_enable = write_enable_reg;
assign root_in_d = root_in_d_reg;
+ // fpga -> host
always @(posedge User_Clk)
begin
write_enable_reg = 0;
gpleds_reg[6] = root_out_a_reg;
end
+ // host -> fpga
always @(posedge User_Clk)
begin
read_enable_reg = 0;
`include "macros.v"
module outbox(clk,
- instr_r, instr_a, instr_d,
+ instr_r, instr_a_, instr_d,
fabric_in_r, fabric_in_a, fabric_in_d,
fabric_out_r, fabric_out_a, fabric_out_d,
ship_r, ship_a, ship_d);
input clk;
input instr_r;
- output instr_a;
+ output instr_a_;
+ reg instr_a;
+ assign instr_a_ = instr_a;
input [(`INSTRUCTION_WIDTH-1):0] instr_d;
wire [(`INSTRUCTION_WIDTH-1):0] instr_d2;
+ wire [(`INSTRUCTION_WIDTH-1):0] instr_d0;
+ wire [(`INSTRUCTION_WIDTH-1):0] recycle_d;
+
input ship_r;
output ship_a;
input [(`DATAWIDTH-1):0] ship_d;
input fabric_out_a;
output [(`PACKET_WIDTH-1):0] fabric_out_d;
+ reg kill_r;
+ wire kill_a;
+ reg [(`COUNT_WIDTH-1):0] kill_d;
+
+ reg [(`INSTRUCTION_WIDTH-1):0] instruction;
+ reg instr_rx;
+ wire instr_ax;
+ reg ifull;
+
+ always @(posedge clk) begin
+ if (!ifull) begin
+ `onread(instr_r, instr_a)
+ ifull = 1;
+ instruction = instr_d;
+ end
+ end else begin
+ if (`instruction_is_kill(instruction)) begin
+ kill_d = `instruction_count(instruction);
+ `onwrite(kill_r, kill_a)
+ ifull = 0;
+ end
+ end else begin
+ `onwrite(instr_rx, instr_ax)
+ ifull = 0;
+ end
+ end
+ end
+ end
+
fifo4 dfifo(clk, fabric_in_r, fabric_in_a, fabric_in_data,
fabric_in_r2, fabric_in_a2, fabric_in_data2);
- fifo4 ififo(clk, instr_r, instr_a, instr_d,
- instr_r2, instr_a2, instr_d2);
-
- outbox_core ob(clk, instr_r2, instr_a2, instr_d2,
- fabric_in_r2, fabric_in_a2, fabric_in_d2,
- fabric_out_r, fabric_out_a, fabric_out_d,
- ship_r, ship_a, ship_d);
+ funnel ifunnel(clk, instr_r0, instr_a0, instr_d0,
+ instr_rx, instr_ax, instruction,
+ recycle_r, recycle_a, recycle_d);
+ fifo4 ififo(clk, instr_r0, instr_a0, instr_d0,
+ instr_r2, instr_a2, instr_d2);
+ outboxcore ob(clk, instr_r2, instr_a2, instr_d2,
+ fabric_in_r2, fabric_in_a2, fabric_in_d2,
+ fabric_out_r, fabric_out_a, fabric_out_d,
+ ship_r, ship_a, ship_d,
+ kill_r, kill_a, kill_d,
+ recycle_r, recycle_a, recycle_d);
endmodule
`include "macros.v"
-module outbox_core(clk,
- instr_r, instr_a_, instr_d,
- fabric_in_r, fabric_in_a_, fabric_in_d,
- fabric_out_r_, fabric_out_a, fabric_out_d_,
- ship_r, ship_a_, ship_d);
+module outboxcore(clk,
+ instr_r, instr_a_, instr_d,
+ fabric_in_r, fabric_in_a_, fabric_in_d,
+ fabric_out_r_, fabric_out_a, fabric_out_d_,
+ ship_r, ship_a_, ship_d,
+ kill_r, kill_a_, kill_d,
+ recycle_r_, recycle_a, recycle_d_
+ );
input clk;
reg have_instruction;
reg have_token;
reg have_data;
reg send_token;
reg send_data;
+ reg parse_instruction;
+ reg do_recycle;
+ reg [(`COUNT_BITS-1):0] kill_count;
reg [(`INSTRUCTION_WIDTH-1):0] instruction;
- `input(ship_r, ship_a, ship_a_, [(`DATAWIDTH-1):0], ship_d)
`input(instr_r, instr_a, instr_a_, [(`INSTRUCTION_WIDTH-1):0], instr_d)
`input(fabric_in_r, fabric_in_a, fabric_in_a_, [(`PACKET_WIDTH-1):0], fabric_in_d)
`output(fabric_out_r, fabric_out_r_, fabric_out_a, [(`PACKET_WIDTH-1):0], fabric_out_d_)
- `defreg(fabric_out_d_, [(`PACKET_WIDTH-1):0], fabric_out_d)
+ `defreg(fabric_out_d_, [(`PACKET_WIDTH-1):0], fabric_out_d)
+ `input(ship_r, ship_a, ship_a_, [(`DATAWIDTH-1):0], ship_d)
+ `input(kill_r, kill_a, kill_a_, [(`COUNT_WIDTH-1):0], kill_d)
+ `output(recycle_r, recycle_r_, recycle_a, [(`INSTRUCTION_WIDTH-1):0], recycle_d_)
+ assign recycle_d_ = instruction;
always @(posedge clk) begin
- if (!have_instruction) begin
- `onread(instr_r, instr_a)
- instruction = instr_d;
- have_instruction = 1;
+
+ if (do_recycle) begin
+ `onwrite(recycle_r, recycle_a)
+ do_recycle = 0;
+ end
+
+ end else begin
+
+ if (!have_instruction && !parse_instruction) begin
+ `onread(instr_r, instr_a)
+ instruction = instr_d;
+ parse_instruction = 1;
+ end
+ end
+
+ /*
+ // FIXME: actually don't want to kill partway through an instruction
+ `onread(kill_r, kill_a)
+ kill_count = kill_d;
+ end
+
+ if (have_instruction && (kill_count > 0)) begin
+ kill_count = kill_count - 1;
+ have_instruction = 0;
+ end
+ */
+
+ if (parse_instruction) begin
have_token = !`instruction_bit_tokenin(instruction);
have_data = !`instruction_bit_datain(instruction);
- `packet_dest(fabric_out_d) = `instruction_bit_dest(instruction);
+ `packet_dest(fabric_out_d) = `instruction_bit_dest(instruction);
send_data = !`instruction_bit_dataout(instruction);
send_token = !`instruction_bit_tokenout(instruction);
+ have_instruction = 1;
+ parse_instruction = 0;
end
- end
- if (have_instruction && !have_token) begin
- `onread(fabric_in_r, fabric_in_a)
- have_token = 1;
+ if (have_instruction && !have_token) begin
+ `onread(fabric_in_r, fabric_in_a)
+ have_token = 1;
+ end
end
- end
-
- if (have_instruction && !have_data) begin
- `onread(ship_r, ship_a)
- if (`instruction_bit_latch(instruction)) begin
- `packet_data(fabric_out_d) = ship_d;
+
+ if (have_instruction && !have_data) begin
+ `onread(ship_r, ship_a)
+ if (`instruction_bit_latch(instruction)) begin
+ `packet_data(fabric_out_d) = ship_d;
+ end
+ have_data = 1;
end
- have_data = 1;
end
- end
- if (have_instruction && have_data && have_token) begin
- if (!send_data || !send_token) begin
- `onwrite(fabric_out_r, fabric_out_a)
- send_data = 1;
- send_token = 1;
+ if (have_instruction && have_data && have_token) begin
+ if (!send_data || !send_token) begin
+ `onwrite(fabric_out_r, fabric_out_a)
+ send_data = 1;
+ send_token = 1;
+ end
end
end
- end
- if (have_instruction && have_data && have_token && send_data && send_token) begin
- have_instruction = 0;
+ if (have_instruction && have_data && have_token && send_data && send_token) begin
+ if (`instruction_count(instruction)==1) begin
+ have_instruction = 0;
+ end else begin
+ have_instruction = 0;
+ if (`instruction_count(instruction)>0) begin
+ `instruction_count(instruction) = `instruction_count(instruction) - 1;
+ end
+ if (`instruction_bit_recycle(instruction)) begin
+ have_instruction = 0;
+ do_recycle = 1;
+ end else begin
+ parse_instruction = 1;
+ end
+ end
+ end
end
-
- end
-
+ end
endmodule
+
initial count_out = 0;
wire [(`DATAWIDTH-1):0] funnel_out_d;
- fabric fabric(clk, horn_in_r, horn_in_a, horn_in_d_,
- funnel_out_r, funnel_out_a, funnel_out_d);
+ fabric fabric(clk, horn_in_r_, horn_in_a, horn_in_d_,
+ funnel_out_r, funnel_out_a_, funnel_out_d);
+ // host -> fpga
always @(posedge clk) begin
if (!full_in) begin
`onread(in_r, in_a)
end
end
+ // fpga -> host
always @(posedge clk) begin
if (!full_out) begin
`onread(funnel_out_r, funnel_out_a)
end
end else begin
`onwrite(out_r, out_a)
- if (count_out<6) out_d = out_d >> 8;
+ out_d = out_d >> 8;
count_out = count_out - 1;
if (count_out==0) full_out = 0;
end
sendc(0x06);
*/
- //for( j=0; j<2; j++) {
+ // for( j=0; j<16; j++) {
i = recvc();
printf("result: %d / %x \n", i, i);
i = recvc();
printf("result: %d / %x \n", i, i);
i = recvc();
printf("result: %d / %x \n", i, i);
- //}
+ // }
return 0;
}
projects / fleet.git / commitdiff