re-enable building of .ace file

diff --git a/Makefile b/Makefile
index 62b7983..cd0e3d0 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -101,6 +101,7 @@ build/fpga/main.bit: $(java_files) $(ship_files)
        rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
        time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk}'
        scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
+       scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/
 
 pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
 intstyle = -intstyle xflow
@@ -217,8 +218,8 @@ synth:
        $(xilinx_ise)par      ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
        $(xilinx_ise)trce     ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
        $(xilinx_ise)bitgen   ${intstyle} -f main.ut main.ncd
-#      $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
-#      mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
+       $(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
+       mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
 
 
 runserver: fleet.jar