1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Size(..), intSize, floatSize, isFloatSize,
29 wordSize, cmmTypeSize, sizeToWidth,
32 Imm(..), strImmLit, litToImm,
40 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
41 RegClass(..), regClass,
47 get_GlobalReg_reg_or_addr,
49 -- * Machine-dependent register-related stuff
50 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
51 allocatableRegsInClass,
58 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
61 EABase(..), EAIndex(..),
62 eax, ebx, ecx, edx, esi, edi, ebp, esp,
63 fake0, fake1, fake2, fake3, fake4, fake5,
66 #if x86_64_TARGET_ARCH
67 EABase(..), EAIndex(..), ripRel,
68 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
69 eax, ebx, ecx, edx, esi, edi, ebp, esp,
70 r8, r9, r10, r11, r12, r13, r14, r15,
71 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
72 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
74 addrModeRegs, allFPArgRegs,
78 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
79 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
81 #if powerpc_TARGET_ARCH
90 #include "HsVersions.h"
93 # define STOLEN_X86_REGS 4
94 -- HACK: go for the max
97 #include "../includes/MachRegs.h"
101 import CgUtils ( get_GlobalReg_addr )
102 import CLabel ( CLabel, mkMainCapabilityLabel )
104 import Outputable ( Outputable(..), pprPanic, panic )
105 import qualified Outputable
113 #if powerpc_TARGET_ARCH
114 import Data.Word ( Word8, Word16, Word32 )
115 import Data.Int ( Int8, Int16, Int32 )
118 -- -----------------------------------------------------------------------------
119 -- Sizes on this architecture
121 -- A Size is usually a combination of width and class
123 -- It looks very like the old MachRep, but it's now of purely local
124 -- significance, here in the native code generator. You can change it
125 -- without global consequences.
127 -- A major use is as an opcode qualifier; thus the opcode
131 -- where the Size field encodes the ".l" part.
133 -- ToDo: it's not clear to me that we need separate signed-vs-unsigned sizes
134 -- here. I've removed them from the x86 version, we'll see what happens --SDM
136 -- ToDo: quite a few occurrences of Size could usefully be replaced by Width
138 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
139 data Size -- For these three, the "size" also gives the int/float
140 -- distinction, because the instructions for int/float
141 -- differ only in their suffices
142 = II8 | II16 | II32 | II64 | FF32 | FF64 | FF80
145 intSize, floatSize :: Width -> Size
150 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
154 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
157 wordSize = intSize wordWidth
159 sizeToWidth :: Size -> Width
161 sizeToWidth II16 = W16
162 sizeToWidth II32 = W32
163 sizeToWidth II64 = W64
164 sizeToWidth FF32 = W32
165 sizeToWidth FF64 = W64
166 sizeToWidth _ = panic "MachInstrs.sizeToWidth"
168 cmmTypeSize :: CmmType -> Size
169 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
170 | otherwise = intSize (typeWidth ty)
172 isFloatSize :: Size -> Bool
173 isFloatSize FF32 = True
174 isFloatSize FF64 = True
175 isFloatSize FF80 = True
176 isFloatSize other = False
179 #if alpha_TARGET_ARCH
183 -- | W -- word (2 bytes): UNUSED
185 | L -- longword (4 bytes)
186 | Q -- quadword (8 bytes)
187 -- | FF -- VAX F-style floating pt: UNUSED
188 -- | GF -- VAX G-style floating pt: UNUSED
189 -- | DF -- VAX D-style floating pt: UNUSED
190 -- | SF -- IEEE single-precision floating pt: UNUSED
191 | TF -- IEEE double-precision floating pt
195 #if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
197 = II8 -- byte (signed)
198 | II8u -- byte (unsigned)
199 | II16 -- halfword (signed, 2 bytes)
200 | II16u -- halfword (unsigned, 2 bytes)
201 | II32 -- word (4 bytes)
202 | II64 -- word (8 bytes)
203 | FF32 -- IEEE single-precision floating pt
204 | FF64 -- IEEE single-precision floating pt
208 intSize, floatSize :: Width -> Size
213 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
217 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
220 wordSize = intSize wordWidth
222 isFloatSize :: Size -> Bool
223 isFloatSize FF32 = True
224 isFloatSize FF64 = True
225 isFloatSize _ = False
227 cmmTypeSize :: CmmType -> Size
228 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
229 | otherwise = intSize (typeWidth ty)
231 sizeToWidth :: Size -> Width
246 -- -----------------------------------------------------------------------------
251 | ImmInteger Integer -- Sigh.
252 | ImmCLbl CLabel -- AbstractC Label (with baggage)
253 | ImmLit Doc -- Simple string
254 | ImmIndex CLabel Int
257 | ImmConstantSum Imm Imm
258 | ImmConstantDiff Imm Imm
259 #if sparc_TARGET_ARCH
260 | LO Imm {- Possible restrictions... -}
263 #if powerpc_TARGET_ARCH
266 | HA Imm {- high halfword adjusted -}
268 strImmLit s = ImmLit (text s)
270 litToImm :: CmmLit -> Imm
271 litToImm (CmmInt i w) = ImmInteger (narrowS w i)
272 -- narrow to the width: a CmmInt might be out of
273 -- range, but we assume that ImmInteger only contains
274 -- in-range values. A signed value should be fine here.
275 litToImm (CmmFloat f W32) = ImmFloat f
276 litToImm (CmmFloat f W64) = ImmDouble f
277 litToImm (CmmLabel l) = ImmCLbl l
278 litToImm (CmmLabelOff l off) = ImmIndex l off
279 litToImm (CmmLabelDiffOff l1 l2 off)
281 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
283 litToImm (CmmBlock id) = ImmCLbl (infoTblLbl id)
285 -- -----------------------------------------------------------------------------
289 #if alpha_TARGET_ARCH
295 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
296 = AddrBaseIndex EABase EAIndex Displacement
299 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
300 data EAIndex = EAIndexNone | EAIndex Reg Int
301 type Displacement = Imm
304 #if sparc_TARGET_ARCH
309 #if powerpc_TARGET_ARCH
314 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
315 addrModeRegs :: AddrMode -> [Reg]
316 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
318 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
319 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
324 addrOffset :: AddrMode -> Int -> Maybe AddrMode
328 #if alpha_TARGET_ARCH
329 _ -> panic "MachMisc.addrOffset not defined for Alpha"
331 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
332 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
334 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
335 AddrBaseIndex r i (ImmInteger n)
336 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
338 AddrBaseIndex r i (ImmCLbl lbl)
339 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
341 AddrBaseIndex r i (ImmIndex lbl ix)
342 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
344 _ -> Nothing -- in theory, shouldn't happen
346 #if sparc_TARGET_ARCH
347 AddrRegImm r (ImmInt n)
348 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
349 | otherwise -> Nothing
352 AddrRegImm r (ImmInteger n)
353 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
354 | otherwise -> Nothing
355 where n2 = n + toInteger off
357 AddrRegReg r (RealReg 0)
358 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
359 | otherwise -> Nothing
363 #if powerpc_TARGET_ARCH
364 AddrRegImm r (ImmInt n)
365 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
366 | otherwise -> Nothing
369 AddrRegImm r (ImmInteger n)
370 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
371 | otherwise -> Nothing
372 where n2 = n + toInteger off
378 #if alpha_TARGET_ARCH
380 fits8Bits :: Integer -> Bool
381 fits8Bits i = i >= -256 && i < 256
385 #if sparc_TARGET_ARCH
387 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
388 fits13Bits :: Integral a => a -> Bool
389 fits13Bits x = x >= -4096 && x < 4096
393 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
394 ++show i++");\nprobably because of large constant data structures;" ++
395 "\nworkaround: use -fvia-C on this module.\n")
399 #if powerpc_TARGET_ARCH
400 fits16Bits :: Integral a => a -> Bool
401 fits16Bits x = x >= -32768 && x < 32768
403 makeImmediate :: Integral a => Width -> Bool -> a -> Maybe Imm
404 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
406 narrow W32 False = fromIntegral (fromIntegral x :: Word32)
407 narrow W16 False = fromIntegral (fromIntegral x :: Word16)
408 narrow W8 False = fromIntegral (fromIntegral x :: Word8)
409 narrow W32 True = fromIntegral (fromIntegral x :: Int32)
410 narrow W16 True = fromIntegral (fromIntegral x :: Int16)
411 narrow W8 True = fromIntegral (fromIntegral x :: Int8)
413 narrowed = narrow rep signed
416 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
417 | otherwise = Nothing
419 | narrowed >= 0 && narrowed < 65536 = Just narrowed
420 | otherwise = Nothing
421 toI16 _ _ = Just narrowed
425 -- @spRel@ gives us a stack relative addressing mode for volatile
426 -- temporaries and for excess call arguments. @fpRel@, where
427 -- applicable, is the same but for the frame pointer.
429 spRel :: Int -- desired stack offset in words, positive or negative
433 #if defined(i386_TARGET_ARCH)
434 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
435 #elif defined(x86_64_TARGET_ARCH)
436 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
438 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
441 #if sparc_TARGET_ARCH
442 fpRel :: Int -> AddrMode
443 -- Duznae work for offsets greater than 13 bits; we just hope for
446 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
449 #if x86_64_TARGET_ARCH
450 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
453 -- -----------------------------------------------------------------------------
456 -- We map STG registers onto appropriate CmmExprs. Either they map
457 -- to real machine registers or stored as offsets from BaseReg. Given
458 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
459 -- register it is in, on this platform, or a CmmExpr denoting the
460 -- address in the register table holding it.
461 -- (See also get_GlobalReg_addr in CgUtils.)
463 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
464 get_GlobalReg_reg_or_addr mid
465 = case globalRegMaybe mid of
467 Nothing -> Right (get_GlobalReg_addr mid)
469 -- ---------------------------------------------------------------------------
472 -- RealRegs are machine regs which are available for allocation, in
473 -- the usual way. We know what class they are, because that's part of
474 -- the processor's architecture.
476 -- VirtualRegs are virtual registers. The register allocator will
477 -- eventually have to map them into RealRegs, or into spill slots.
478 -- VirtualRegs are allocated on the fly, usually to represent a single
479 -- value in the abstract assembly code (i.e. dynamic registers are
480 -- usually single assignment). With the new register allocator, the
481 -- single assignment restriction isn't necessary to get correct code,
482 -- although a better register allocation will result if single
483 -- assignment is used -- because the allocator maps a VirtualReg into
484 -- a single RealReg, even if the VirtualReg has multiple live ranges.
486 -- Virtual regs can be of either class, so that info is attached.
488 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
489 -- when supplied with the vreg for the lower-half of the quantity.
490 -- (NB. Not reversible).
491 getHiVRegFromLo (VirtualRegI u)
492 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
493 getHiVRegFromLo other
494 = pprPanic "getHiVRegFromLo" (ppr other)
502 instance Uniquable RegClass where
503 getUnique RcInteger = mkUnique 'L' 0
504 getUnique RcFloat = mkUnique 'L' 1
505 getUnique RcDouble = mkUnique 'L' 2
510 = RealReg {-# UNPACK #-} !RegNo
511 | VirtualRegI {-# UNPACK #-} !Unique
512 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
513 | VirtualRegF {-# UNPACK #-} !Unique
514 | VirtualRegD {-# UNPACK #-} !Unique
517 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
518 -- in the register allocator.
519 instance Uniquable Reg where
520 getUnique (RealReg i) = mkUnique 'C' i
521 getUnique (VirtualRegI u) = u
522 getUnique (VirtualRegHi u) = u
523 getUnique (VirtualRegF u) = u
524 getUnique (VirtualRegD u) = u
526 unRealReg (RealReg i) = i
527 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
529 mkVReg :: Unique -> Size -> Reg
531 | not (isFloatSize size) = VirtualRegI u
534 #if sparc_TARGET_ARCH
535 FF32 -> VirtualRegF u
536 FF64 -> VirtualRegD u
538 FF32 -> VirtualRegD u
539 FF64 -> VirtualRegD u
541 _other -> panic "mkVReg"
543 isVirtualReg :: Reg -> Bool
544 isVirtualReg (RealReg _) = False
545 isVirtualReg (VirtualRegI _) = True
546 isVirtualReg (VirtualRegHi _) = True
547 isVirtualReg (VirtualRegF _) = True
548 isVirtualReg (VirtualRegD _) = True
550 isRealReg :: Reg -> Bool
551 isRealReg = not . isVirtualReg
553 renameVirtualReg :: Unique -> Reg -> Reg
556 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
557 VirtualRegI _ -> VirtualRegI u
558 VirtualRegHi _ -> VirtualRegHi u
559 VirtualRegF _ -> VirtualRegF u
560 VirtualRegD _ -> VirtualRegD u
562 instance Show Reg where
563 show (RealReg i) = showReg i
564 show (VirtualRegI u) = "%vI_" ++ show u
565 show (VirtualRegHi u) = "%vHi_" ++ show u
566 show (VirtualRegF u) = "%vF_" ++ show u
567 show (VirtualRegD u) = "%vD_" ++ show u
569 instance Outputable RegClass where
570 ppr RcInteger = Outputable.text "I"
571 ppr RcFloat = Outputable.text "F"
572 ppr RcDouble = Outputable.text "D"
574 instance Outputable Reg where
575 ppr r = Outputable.text (show r)
580 -- trivColorable function for the graph coloring allocator
581 -- This gets hammered by scanGraph during register allocation,
582 -- so needs to be fairly efficient.
584 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
585 -- (which are disjoint) ie. x86, x86_64 and ppc
589 -- Doing a nice fold over the UniqSet makes trivColorable use
590 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
592 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
593 trivColorable classN conflicts exclusions
596 acc :: Reg -> (Int, Int) -> (Int, Int)
599 RcInteger -> (cd+1, cf)
600 RcDouble -> (cd, cf+1)
601 _ -> panic "MachRegs.trivColorable: reg class not handled"
603 tmp = foldUniqSet acc (0, 0) conflicts
604 (countInt, countFloat) = foldUniqSet acc tmp exclusions
606 squeese = worst countInt classN RcInteger
607 + worst countFloat classN RcDouble
609 in squeese < allocatableRegsInClass classN
611 -- | Worst case displacement
612 -- node N of classN has n neighbors of class C.
614 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
615 -- This is a bit boring compared to what's in RegArchX86.
617 worst :: Int -> RegClass -> RegClass -> Int
618 worst n classN classC
622 RcInteger -> min n (allocatableRegsInClass RcInteger)
627 RcDouble -> min n (allocatableRegsInClass RcDouble)
632 -- The number of allocatable regs is hard coded here so we can do a fast comparision
633 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
634 -- free regs, but they can't be more or the register conflict graph won't color.
636 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
637 -- is too slow for us here.
639 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
642 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
643 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
645 #elif x86_64_TARGET_ARCH
646 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
647 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
649 #elif powerpc_TARGET_ARCH
650 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
651 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
653 #elif sparc_TARGET_ARCH
654 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
655 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
658 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
661 {-# INLINE regClass #-}
662 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
663 trivColorable classN conflicts exclusions
664 = {-# SCC "trivColorable" #-}
668 NodeUFM _ _ left right
669 -> case isSqueesed cI cF right of
672 False -> isSqueesed cI' cF' left
673 True -> (# True, cI', cF' #)
676 -> case regClass reg of
678 -> case cI +# _ILIT(1) of
679 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
682 -> case cF +# _ILIT(1) of
683 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
686 -> (# False, cI, cF #)
688 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
689 (# False, cI', cF' #)
690 -> case isSqueesed cI' cF' exclusions of
691 (# s, _, _ #) -> not s
698 -- -----------------------------------------------------------------------------
699 -- Machine-specific register stuff
701 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
702 -- point registers. The mapping of STG registers to alpha machine registers
703 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
705 #if alpha_TARGET_ARCH
709 v0, f0, ra, pv, gp, sp, zeroh :: Reg
711 f0 = realReg (fReg 0)
712 ra = FixedReg ILIT(26)
714 gp = FixedReg ILIT(29)
715 sp = FixedReg ILIT(30)
716 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
718 t9, t10, t11, t12 :: Reg
726 Intel x86 architecture:
727 - All registers except 7 (esp) are available for use.
728 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
729 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
730 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
731 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
732 fp registers, and 3-operand insns for them, and we translate this into
733 real stack-based x86 fp code after register allocation.
735 The fp registers are all Double registers; we don't have any RcFloat class
736 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
742 fake0, fake1, fake2, fake3, fake4, fake5,
743 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
760 -- On x86, we might want to have an 8-bit RegClass, which would
761 -- contain just regs 1-4 (the others don't have 8-bit versions).
762 -- However, we can get away without this at the moment because the
763 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
764 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
765 regClass (VirtualRegI u) = RcInteger
766 regClass (VirtualRegHi u) = RcInteger
767 regClass (VirtualRegD u) = RcDouble
768 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
769 (ppr (VirtualRegF u))
772 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
773 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
775 showReg :: RegNo -> String
777 = if n >= 0 && n < 14
779 else "%unknown_x86_real_reg_" ++ show n
785 AMD x86_64 architecture:
786 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
787 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
788 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
792 #if x86_64_TARGET_ARCH
794 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
795 r8, r9, r10, r11, r12, r13, r14, r15,
796 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
797 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
832 -- so we can re-use some x86 code:
842 xmm n = RealReg (16+n)
844 -- On x86, we might want to have an 8-bit RegClass, which would
845 -- contain just regs 1-4 (the others don't have 8-bit versions).
846 -- However, we can get away without this at the moment because the
847 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
848 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
849 regClass (VirtualRegI u) = RcInteger
850 regClass (VirtualRegHi u) = RcInteger
851 regClass (VirtualRegD u) = RcDouble
852 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
853 (ppr (VirtualRegF u))
856 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
858 showReg :: RegNo -> String
860 | n >= 16 = "%xmm" ++ show (n-16)
861 | n >= 8 = "%r" ++ show n
862 | otherwise = regNames !! n
867 The SPARC has 64 registers of interest; 32 integer registers and 32
868 floating point registers. The mapping of STG registers to SPARC
869 machine registers is defined in StgRegs.h. We are, of course,
870 prepared for any eventuality.
872 The whole fp-register pairing thing on sparcs is a huge nuisance. See
873 fptools/ghc/includes/MachRegs.h for a description of what's going on
877 #if sparc_TARGET_ARCH
879 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
886 nCG_FirstFloatReg :: RegNo
887 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
889 regClass (VirtualRegI u) = RcInteger
890 regClass (VirtualRegF u) = RcFloat
891 regClass (VirtualRegD u) = RcDouble
892 regClass (RealReg i) | i < 32 = RcInteger
893 | i < nCG_FirstFloatReg = RcDouble
894 | otherwise = RcFloat
896 showReg :: RegNo -> String
898 | n >= 0 && n < 8 = "%g" ++ show n
899 | n >= 8 && n < 16 = "%o" ++ show (n-8)
900 | n >= 16 && n < 24 = "%l" ++ show (n-16)
901 | n >= 24 && n < 32 = "%i" ++ show (n-24)
902 | n >= 32 && n < 64 = "%f" ++ show (n-32)
903 | otherwise = "%unknown_sparc_real_reg_" ++ show n
905 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
907 f6 = RealReg (fReg 6)
908 f8 = RealReg (fReg 8)
909 f22 = RealReg (fReg 22)
910 f26 = RealReg (fReg 26)
911 f27 = RealReg (fReg 27)
914 -- g0 is useful for codegen; is always zero, and writes to it vanish.
915 g0 = RealReg (gReg 0)
916 g1 = RealReg (gReg 1)
917 g2 = RealReg (gReg 2)
919 -- FP, SP, int and float return (from C) regs.
920 fp = RealReg (iReg 6)
921 sp = RealReg (oReg 6)
922 o0 = RealReg (oReg 0)
923 o1 = RealReg (oReg 1)
924 f0 = RealReg (fReg 0)
925 f1 = RealReg (fReg 1)
930 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
934 #if powerpc_TARGET_ARCH
938 regClass (VirtualRegI u) = RcInteger
939 regClass (VirtualRegHi u) = RcInteger
940 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
941 (ppr (VirtualRegF u))
942 regClass (VirtualRegD u) = RcDouble
943 regClass (RealReg i) | i < 32 = RcInteger
944 | otherwise = RcDouble
946 showReg :: RegNo -> String
948 | n >= 0 && n <= 31 = "%r" ++ show n
949 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
950 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
957 f1 = RealReg $ fReg 1
958 f20 = RealReg $ fReg 20
959 f21 = RealReg $ fReg 21
963 Redefine the literals used for machine-registers with non-numeric
964 names in the header files. Gag me with a spoon, eh?
967 #if alpha_TARGET_ARCH
1001 #if i386_TARGET_ARCH
1018 #if x86_64_TARGET_ARCH
1053 #if sparc_TARGET_ARCH
1121 #if powerpc_TARGET_ARCH
1155 #ifdef darwin_TARGET_OS
1225 -- allMachRegs is the complete set of machine regs.
1226 allMachRegNos :: [RegNo]
1228 = IF_ARCH_alpha( [0..63],
1229 IF_ARCH_i386( [0..13],
1230 IF_ARCH_x86_64( [0..31],
1231 IF_ARCH_sparc( ([0..31]
1232 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1233 ++ [nCG_FirstFloatReg .. f31]),
1234 IF_ARCH_powerpc([0..63],
1237 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1238 -- i.e., these are the regs for which we are prepared to allow the
1239 -- register allocator to attempt to map VRegs to.
1240 allocatableRegs :: [RegNo]
1242 = let isFree i = isFastTrue (freeReg i)
1243 in filter isFree allMachRegNos
1246 -- | The number of regs in each class.
1247 -- We go via top level CAFs to ensure that we're not recomputing
1248 -- the length of these lists each time the fn is called.
1249 allocatableRegsInClass :: RegClass -> Int
1250 allocatableRegsInClass cls
1252 RcInteger -> allocatableRegsInteger
1253 RcDouble -> allocatableRegsDouble
1255 allocatableRegsInteger
1256 = length $ filter (\r -> regClass r == RcInteger)
1257 $ map RealReg allocatableRegs
1259 allocatableRegsDouble
1260 = length $ filter (\r -> regClass r == RcDouble)
1261 $ map RealReg allocatableRegs
1264 -- these are the regs which we cannot assume stay alive over a
1266 callClobberedRegs :: [Reg]
1269 #if alpha_TARGET_ARCH
1270 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1271 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1272 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1273 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1274 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1275 #endif /* alpha_TARGET_ARCH */
1276 #if i386_TARGET_ARCH
1277 -- caller-saves registers
1278 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1279 #endif /* i386_TARGET_ARCH */
1280 #if x86_64_TARGET_ARCH
1281 -- caller-saves registers
1282 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1283 -- all xmm regs are caller-saves
1284 #endif /* x86_64_TARGET_ARCH */
1285 #if sparc_TARGET_ARCH
1288 [oReg i | i <- [0..5]] ++
1289 [gReg i | i <- [1..7]] ++
1290 [fReg i | i <- [0..31]] )
1291 #endif /* sparc_TARGET_ARCH */
1292 #if powerpc_TARGET_ARCH
1293 #if darwin_TARGET_OS
1294 map RealReg (0:[2..12] ++ map fReg [0..13])
1295 #elif linux_TARGET_OS
1296 map RealReg (0:[2..13] ++ map fReg [0..13])
1298 #endif /* powerpc_TARGET_ARCH */
1301 -- argRegs is the set of regs which are read for an n-argument call to C.
1302 -- For archs which pass all args on the stack (x86), is empty.
1303 -- Sparc passes up to the first 6 args in regs.
1304 -- Dunno about Alpha.
1305 argRegs :: RegNo -> [Reg]
1307 #if i386_TARGET_ARCH
1308 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1311 #if x86_64_TARGET_ARCH
1312 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1315 #if alpha_TARGET_ARCH
1317 argRegs 1 = freeMappedRegs [16, fReg 16]
1318 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1319 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1320 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1321 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1322 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1323 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1324 #endif /* alpha_TARGET_ARCH */
1326 #if sparc_TARGET_ARCH
1328 argRegs 1 = map (RealReg . oReg) [0]
1329 argRegs 2 = map (RealReg . oReg) [0,1]
1330 argRegs 3 = map (RealReg . oReg) [0,1,2]
1331 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1332 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1333 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1334 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1335 #endif /* sparc_TARGET_ARCH */
1337 #if powerpc_TARGET_ARCH
1339 argRegs 1 = map RealReg [3]
1340 argRegs 2 = map RealReg [3,4]
1341 argRegs 3 = map RealReg [3..5]
1342 argRegs 4 = map RealReg [3..6]
1343 argRegs 5 = map RealReg [3..7]
1344 argRegs 6 = map RealReg [3..8]
1345 argRegs 7 = map RealReg [3..9]
1346 argRegs 8 = map RealReg [3..10]
1347 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1348 #endif /* powerpc_TARGET_ARCH */
1351 -- all of the arg regs ??
1352 #if alpha_TARGET_ARCH
1353 allArgRegs :: [(Reg, Reg)]
1354 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1355 #endif /* alpha_TARGET_ARCH */
1357 #if sparc_TARGET_ARCH
1359 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1360 #endif /* sparc_TARGET_ARCH */
1362 #if i386_TARGET_ARCH
1364 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1367 #if x86_64_TARGET_ARCH
1369 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1370 allFPArgRegs :: [Reg]
1371 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1374 #if powerpc_TARGET_ARCH
1376 allArgRegs = map RealReg [3..10]
1377 allFPArgRegs :: [Reg]
1378 #if darwin_TARGET_OS
1379 allFPArgRegs = map (RealReg . fReg) [1..13]
1380 #elif linux_TARGET_OS
1381 allFPArgRegs = map (RealReg . fReg) [1..8]
1383 #endif /* powerpc_TARGET_ARCH */
1387 freeReg :: RegNo -> FastBool
1389 #if alpha_TARGET_ARCH
1390 freeReg 26 = fastBool False -- return address (ra)
1391 freeReg 28 = fastBool False -- reserved for the assembler (at)
1392 freeReg 29 = fastBool False -- global pointer (gp)
1393 freeReg 30 = fastBool False -- stack pointer (sp)
1394 freeReg 31 = fastBool False -- always zero (zeroh)
1395 freeReg 63 = fastBool False -- always zero (f31)
1398 #if i386_TARGET_ARCH
1399 freeReg esp = fastBool False -- %esp is the C stack pointer
1402 #if x86_64_TARGET_ARCH
1403 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1406 #if sparc_TARGET_ARCH
1407 freeReg g0 = fastBool False -- %g0 is always 0.
1408 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1409 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1410 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1411 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1412 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1413 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1414 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1415 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1416 freeReg f1 = fastBool False
1419 #if powerpc_TARGET_ARCH
1420 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1421 freeReg 1 = fastBool False -- The Stack Pointer
1422 #if !darwin_TARGET_OS
1423 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1424 freeReg 2 = fastBool False
1429 freeReg REG_Base = fastBool False
1432 freeReg REG_R1 = fastBool False
1435 freeReg REG_R2 = fastBool False
1438 freeReg REG_R3 = fastBool False
1441 freeReg REG_R4 = fastBool False
1444 freeReg REG_R5 = fastBool False
1447 freeReg REG_R6 = fastBool False
1450 freeReg REG_R7 = fastBool False
1453 freeReg REG_R8 = fastBool False
1456 freeReg REG_F1 = fastBool False
1459 freeReg REG_F2 = fastBool False
1462 freeReg REG_F3 = fastBool False
1465 freeReg REG_F4 = fastBool False
1468 freeReg REG_D1 = fastBool False
1471 freeReg REG_D2 = fastBool False
1474 freeReg REG_Sp = fastBool False
1477 freeReg REG_Su = fastBool False
1480 freeReg REG_SpLim = fastBool False
1483 freeReg REG_Hp = fastBool False
1486 freeReg REG_HpLim = fastBool False
1488 freeReg n = fastBool True
1491 -- | Returns 'Nothing' if this global register is not stored
1492 -- in a real machine register, otherwise returns @'Just' reg@, where
1493 -- reg is the machine register it is stored in.
1495 globalRegMaybe :: GlobalReg -> Maybe Reg
1498 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1501 globalRegMaybe (VanillaReg 1 _) = Just (RealReg REG_R1)
1504 globalRegMaybe (VanillaReg 2 _) = Just (RealReg REG_R2)
1507 globalRegMaybe (VanillaReg 3 _) = Just (RealReg REG_R3)
1510 globalRegMaybe (VanillaReg 4 _) = Just (RealReg REG_R4)
1513 globalRegMaybe (VanillaReg 5 _) = Just (RealReg REG_R5)
1516 globalRegMaybe (VanillaReg 6 _) = Just (RealReg REG_R6)
1519 globalRegMaybe (VanillaReg 7 _) = Just (RealReg REG_R7)
1522 globalRegMaybe (VanillaReg 8 _) = Just (RealReg REG_R8)
1525 globalRegMaybe (VanillaReg 9 _) = Just (RealReg REG_R9)
1528 globalRegMaybe (VanillaReg 10 _) = Just (RealReg REG_R10)
1531 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1534 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1537 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1540 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1543 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1546 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1549 globalRegMaybe Sp = Just (RealReg REG_Sp)
1552 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1555 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1558 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1561 globalRegMaybe Hp = Just (RealReg REG_Hp)
1564 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1566 #ifdef REG_CurrentTSO
1567 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1569 #ifdef REG_CurrentNursery
1570 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1572 globalRegMaybe _ = Nothing