1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Imm(..), strImmLit, litToImm,
36 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
37 RegClass(..), regClass,
43 get_GlobalReg_reg_or_addr,
45 -- * Machine-dependent register-related stuff
46 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
53 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
56 EABase(..), EAIndex(..),
57 eax, ebx, ecx, edx, esi, edi, ebp, esp,
58 fake0, fake1, fake2, fake3, fake4, fake5,
61 #if x86_64_TARGET_ARCH
62 EABase(..), EAIndex(..), ripRel,
63 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
64 eax, ebx, ecx, edx, esi, edi, ebp, esp,
65 r8, r9, r10, r11, r12, r13, r14, r15,
66 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
67 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
69 addrModeRegs, allFPArgRegs,
73 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
74 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
76 #if powerpc_TARGET_ARCH
85 #include "HsVersions.h"
88 # define STOLEN_X86_REGS 4
89 -- HACK: go for the max
95 import MachOp ( MachRep(..) )
96 import CgUtils ( get_GlobalReg_addr )
98 import CLabel ( CLabel, mkMainCapabilityLabel )
100 import Outputable ( Outputable(..), pprPanic, panic )
101 import qualified Outputable
107 #if powerpc_TARGET_ARCH
108 import Data.Word ( Word8, Word16, Word32 )
109 import Data.Int ( Int8, Int16, Int32 )
112 -- -----------------------------------------------------------------------------
117 | ImmInteger Integer -- Sigh.
118 | ImmCLbl CLabel -- AbstractC Label (with baggage)
119 | ImmLit Doc -- Simple string
120 | ImmIndex CLabel Int
123 | ImmConstantSum Imm Imm
124 | ImmConstantDiff Imm Imm
125 #if sparc_TARGET_ARCH
126 | LO Imm {- Possible restrictions... -}
129 #if powerpc_TARGET_ARCH
132 | HA Imm {- high halfword adjusted -}
134 strImmLit s = ImmLit (text s)
136 litToImm :: CmmLit -> Imm
137 litToImm (CmmInt i _) = ImmInteger i
138 litToImm (CmmFloat f F32) = ImmFloat f
139 litToImm (CmmFloat f F64) = ImmDouble f
140 litToImm (CmmLabel l) = ImmCLbl l
141 litToImm (CmmLabelOff l off) = ImmIndex l off
142 litToImm (CmmLabelDiffOff l1 l2 off)
144 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
147 -- -----------------------------------------------------------------------------
151 #if alpha_TARGET_ARCH
157 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
158 = AddrBaseIndex EABase EAIndex Displacement
161 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
162 data EAIndex = EAIndexNone | EAIndex Reg Int
163 type Displacement = Imm
166 #if sparc_TARGET_ARCH
171 #if powerpc_TARGET_ARCH
176 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
177 addrModeRegs :: AddrMode -> [Reg]
178 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
180 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
181 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
186 addrOffset :: AddrMode -> Int -> Maybe AddrMode
190 #if alpha_TARGET_ARCH
191 _ -> panic "MachMisc.addrOffset not defined for Alpha"
193 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
194 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
196 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
197 AddrBaseIndex r i (ImmInteger n)
198 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
200 AddrBaseIndex r i (ImmCLbl lbl)
201 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
203 AddrBaseIndex r i (ImmIndex lbl ix)
204 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
206 _ -> Nothing -- in theory, shouldn't happen
208 #if sparc_TARGET_ARCH
209 AddrRegImm r (ImmInt n)
210 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
211 | otherwise -> Nothing
214 AddrRegImm r (ImmInteger n)
215 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
216 | otherwise -> Nothing
217 where n2 = n + toInteger off
219 AddrRegReg r (RealReg 0)
220 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
221 | otherwise -> Nothing
225 #if powerpc_TARGET_ARCH
226 AddrRegImm r (ImmInt n)
227 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
228 | otherwise -> Nothing
231 AddrRegImm r (ImmInteger n)
232 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
233 | otherwise -> Nothing
234 where n2 = n + toInteger off
240 #if alpha_TARGET_ARCH
242 fits8Bits :: Integer -> Bool
243 fits8Bits i = i >= -256 && i < 256
247 #if sparc_TARGET_ARCH
249 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
250 fits13Bits :: Integral a => a -> Bool
251 fits13Bits x = x >= -4096 && x < 4096
255 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
256 ++show i++");\nprobably because of large constant data structures;" ++
257 "\nworkaround: use -fvia-C on this module.\n")
261 #if powerpc_TARGET_ARCH
262 fits16Bits :: Integral a => a -> Bool
263 fits16Bits x = x >= -32768 && x < 32768
265 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
267 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
269 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
270 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
271 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
272 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
273 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
274 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
276 narrowed = narrow rep signed
279 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
280 | otherwise = Nothing
282 | narrowed >= 0 && narrowed < 65536 = Just narrowed
283 | otherwise = Nothing
284 toI16 _ _ = Just narrowed
288 -- @spRel@ gives us a stack relative addressing mode for volatile
289 -- temporaries and for excess call arguments. @fpRel@, where
290 -- applicable, is the same but for the frame pointer.
292 spRel :: Int -- desired stack offset in words, positive or negative
296 #if defined(i386_TARGET_ARCH)
297 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
298 #elif defined(x86_64_TARGET_ARCH)
299 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
301 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
304 #if sparc_TARGET_ARCH
305 fpRel :: Int -> AddrMode
306 -- Duznae work for offsets greater than 13 bits; we just hope for
309 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
312 #if x86_64_TARGET_ARCH
313 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
316 -- -----------------------------------------------------------------------------
319 -- We map STG registers onto appropriate CmmExprs. Either they map
320 -- to real machine registers or stored as offsets from BaseReg. Given
321 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
322 -- register it is in, on this platform, or a CmmExpr denoting the
323 -- address in the register table holding it.
324 -- (See also get_GlobalReg_addr in CgUtils.)
326 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
327 get_GlobalReg_reg_or_addr mid
328 = case globalRegMaybe mid of
330 Nothing -> Right (get_GlobalReg_addr mid)
332 -- ---------------------------------------------------------------------------
335 -- RealRegs are machine regs which are available for allocation, in
336 -- the usual way. We know what class they are, because that's part of
337 -- the processor's architecture.
339 -- VirtualRegs are virtual registers. The register allocator will
340 -- eventually have to map them into RealRegs, or into spill slots.
341 -- VirtualRegs are allocated on the fly, usually to represent a single
342 -- value in the abstract assembly code (i.e. dynamic registers are
343 -- usually single assignment). With the new register allocator, the
344 -- single assignment restriction isn't necessary to get correct code,
345 -- although a better register allocation will result if single
346 -- assignment is used -- because the allocator maps a VirtualReg into
347 -- a single RealReg, even if the VirtualReg has multiple live ranges.
349 -- Virtual regs can be of either class, so that info is attached.
351 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
352 -- when supplied with the vreg for the lower-half of the quantity.
353 -- (NB. Not reversible).
354 getHiVRegFromLo (VirtualRegI u)
355 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
356 getHiVRegFromLo other
357 = pprPanic "getHiVRegFromLo" (ppr other)
365 instance Uniquable RegClass where
366 getUnique RcInteger = mkUnique 'L' 0
367 getUnique RcFloat = mkUnique 'L' 1
368 getUnique RcDouble = mkUnique 'L' 2
373 = RealReg {-# UNPACK #-} !RegNo
374 | VirtualRegI {-# UNPACK #-} !Unique
375 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
376 | VirtualRegF {-# UNPACK #-} !Unique
377 | VirtualRegD {-# UNPACK #-} !Unique
380 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
381 -- in the register allocator.
382 instance Uniquable Reg where
383 getUnique (RealReg i) = mkUnique 'C' i
384 getUnique (VirtualRegI u) = u
385 getUnique (VirtualRegHi u) = u
386 getUnique (VirtualRegF u) = u
387 getUnique (VirtualRegD u) = u
389 unRealReg (RealReg i) = i
390 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
392 mkVReg :: Unique -> MachRep -> Reg
395 #if sparc_TARGET_ARCH
401 other -> VirtualRegI u
403 isVirtualReg :: Reg -> Bool
404 isVirtualReg (RealReg _) = False
405 isVirtualReg (VirtualRegI _) = True
406 isVirtualReg (VirtualRegHi _) = True
407 isVirtualReg (VirtualRegF _) = True
408 isVirtualReg (VirtualRegD _) = True
410 isRealReg :: Reg -> Bool
411 isRealReg = not . isVirtualReg
413 renameVirtualReg :: Unique -> Reg -> Reg
416 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
417 VirtualRegI _ -> VirtualRegI u
418 VirtualRegHi _ -> VirtualRegHi u
419 VirtualRegF _ -> VirtualRegF u
420 VirtualRegD _ -> VirtualRegD u
422 instance Show Reg where
423 show (RealReg i) = showReg i
424 show (VirtualRegI u) = "%vI_" ++ show u
425 show (VirtualRegHi u) = "%vHi_" ++ show u
426 show (VirtualRegF u) = "%vF_" ++ show u
427 show (VirtualRegD u) = "%vD_" ++ show u
429 instance Outputable RegClass where
430 ppr RcInteger = Outputable.text "I"
431 ppr RcFloat = Outputable.text "F"
432 ppr RcDouble = Outputable.text "D"
434 instance Outputable Reg where
435 ppr r = Outputable.text (show r)
440 -- trivColorable function for the graph coloring allocator
441 -- This gets hammered by scanGraph during register allocation,
442 -- so needs to be fairly efficient.
444 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
445 -- (which are disjoint) ie. x86, x86_64 and ppc
447 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
448 trivColorable classN conflicts exclusions
452 RcInteger -> (cd+1, cf)
453 RcDouble -> (cd, cf+1)
454 _ -> panic "MachRegs.trivColorable: reg class not handled"
456 tmp = foldUniqSet acc (0, 0) conflicts
457 (rsD, rsFP) = foldUniqSet acc tmp exclusions
459 squeese = worst rsD classN RcInteger
460 + worst rsFP classN RcDouble
462 in squeese < allocatableRegsInClass classN
465 -- | Worst case displacement
466 -- node N of classN has n neighbors of class C.
468 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
469 -- This is a bit boring compared to what's in RegArchX86.
471 worst :: Int -> RegClass -> RegClass -> Int
472 worst n classN classC
476 RcInteger -> min n (allocatableRegsInClass RcInteger)
481 RcDouble -> min n (allocatableRegsInClass RcDouble)
485 -- -----------------------------------------------------------------------------
486 -- Machine-specific register stuff
488 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
489 -- point registers. The mapping of STG registers to alpha machine registers
490 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
492 #if alpha_TARGET_ARCH
496 v0, f0, ra, pv, gp, sp, zeroh :: Reg
498 f0 = realReg (fReg 0)
499 ra = FixedReg ILIT(26)
501 gp = FixedReg ILIT(29)
502 sp = FixedReg ILIT(30)
503 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
505 t9, t10, t11, t12 :: Reg
513 Intel x86 architecture:
514 - All registers except 7 (esp) are available for use.
515 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
516 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
517 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
518 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
519 fp registers, and 3-operand insns for them, and we translate this into
520 real stack-based x86 fp code after register allocation.
522 The fp registers are all Double registers; we don't have any RcFloat class
523 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
529 fake0, fake1, fake2, fake3, fake4, fake5,
530 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
547 -- On x86, we might want to have an 8-bit RegClass, which would
548 -- contain just regs 1-4 (the others don't have 8-bit versions).
549 -- However, we can get away without this at the moment because the
550 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
551 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
552 regClass (VirtualRegI u) = RcInteger
553 regClass (VirtualRegHi u) = RcInteger
554 regClass (VirtualRegD u) = RcDouble
555 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
556 (ppr (VirtualRegF u))
559 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
560 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
562 showReg :: RegNo -> String
564 = if n >= 0 && n < 14
566 else "%unknown_x86_real_reg_" ++ show n
572 AMD x86_64 architecture:
573 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
574 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
575 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
579 #if x86_64_TARGET_ARCH
581 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
582 r8, r9, r10, r11, r12, r13, r14, r15,
583 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
584 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
619 -- so we can re-use some x86 code:
629 xmm n = RealReg (16+n)
631 -- On x86, we might want to have an 8-bit RegClass, which would
632 -- contain just regs 1-4 (the others don't have 8-bit versions).
633 -- However, we can get away without this at the moment because the
634 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
635 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
636 regClass (VirtualRegI u) = RcInteger
637 regClass (VirtualRegHi u) = RcInteger
638 regClass (VirtualRegD u) = RcDouble
639 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
640 (ppr (VirtualRegF u))
643 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
645 showReg :: RegNo -> String
647 | n >= 16 = "%xmm" ++ show (n-16)
648 | n >= 8 = "%r" ++ show n
649 | otherwise = regNames !! n
654 The SPARC has 64 registers of interest; 32 integer registers and 32
655 floating point registers. The mapping of STG registers to SPARC
656 machine registers is defined in StgRegs.h. We are, of course,
657 prepared for any eventuality.
659 The whole fp-register pairing thing on sparcs is a huge nuisance. See
660 fptools/ghc/includes/MachRegs.h for a description of what's going on
664 #if sparc_TARGET_ARCH
666 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
673 nCG_FirstFloatReg :: RegNo
674 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
676 regClass (VirtualRegI u) = RcInteger
677 regClass (VirtualRegF u) = RcFloat
678 regClass (VirtualRegD u) = RcDouble
679 regClass (RealReg i) | i < 32 = RcInteger
680 | i < nCG_FirstFloatReg = RcDouble
681 | otherwise = RcFloat
683 showReg :: RegNo -> String
685 | n >= 0 && n < 8 = "%g" ++ show n
686 | n >= 8 && n < 16 = "%o" ++ show (n-8)
687 | n >= 16 && n < 24 = "%l" ++ show (n-16)
688 | n >= 24 && n < 32 = "%i" ++ show (n-24)
689 | n >= 32 && n < 64 = "%f" ++ show (n-32)
690 | otherwise = "%unknown_sparc_real_reg_" ++ show n
692 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
694 f6 = RealReg (fReg 6)
695 f8 = RealReg (fReg 8)
696 f22 = RealReg (fReg 22)
697 f26 = RealReg (fReg 26)
698 f27 = RealReg (fReg 27)
701 -- g0 is useful for codegen; is always zero, and writes to it vanish.
702 g0 = RealReg (gReg 0)
703 g1 = RealReg (gReg 1)
704 g2 = RealReg (gReg 2)
706 -- FP, SP, int and float return (from C) regs.
707 fp = RealReg (iReg 6)
708 sp = RealReg (oReg 6)
709 o0 = RealReg (oReg 0)
710 o1 = RealReg (oReg 1)
711 f0 = RealReg (fReg 0)
712 f1 = RealReg (fReg 1)
717 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
721 #if powerpc_TARGET_ARCH
725 regClass (VirtualRegI u) = RcInteger
726 regClass (VirtualRegHi u) = RcInteger
727 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
728 (ppr (VirtualRegF u))
729 regClass (VirtualRegD u) = RcDouble
730 regClass (RealReg i) | i < 32 = RcInteger
731 | otherwise = RcDouble
733 showReg :: RegNo -> String
735 | n >= 0 && n <= 31 = "%r" ++ show n
736 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
737 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
744 f1 = RealReg $ fReg 1
745 f20 = RealReg $ fReg 20
746 f21 = RealReg $ fReg 21
750 Redefine the literals used for machine-registers with non-numeric
751 names in the header files. Gag me with a spoon, eh?
754 #if alpha_TARGET_ARCH
805 #if x86_64_TARGET_ARCH
840 #if sparc_TARGET_ARCH
908 #if powerpc_TARGET_ARCH
942 #ifdef darwin_TARGET_OS
1012 -- allMachRegs is the complete set of machine regs.
1013 allMachRegNos :: [RegNo]
1015 = IF_ARCH_alpha( [0..63],
1016 IF_ARCH_i386( [0..13],
1017 IF_ARCH_x86_64( [0..31],
1018 IF_ARCH_sparc( ([0..31]
1019 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1020 ++ [nCG_FirstFloatReg .. f31]),
1021 IF_ARCH_powerpc([0..63],
1024 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1025 -- i.e., these are the regs for which we are prepared to allow the
1026 -- register allocator to attempt to map VRegs to.
1027 allocatableRegs :: [RegNo]
1029 = let isFree i = isFastTrue (freeReg i)
1030 in filter isFree allMachRegNos
1033 -- | The number of regs in each class.
1034 -- We go via top level CAFs to ensure that we're not recomputing
1035 -- the length of these lists each time the fn is called.
1036 allocatableRegsInClass :: RegClass -> Int
1037 allocatableRegsInClass cls
1039 RcInteger -> allocatableRegsInteger
1040 RcDouble -> allocatableRegsDouble
1042 allocatableRegsInteger
1043 = length $ filter (\r -> regClass r == RcInteger)
1044 $ map RealReg allocatableRegs
1046 allocatableRegsDouble
1047 = length $ filter (\r -> regClass r == RcDouble)
1048 $ map RealReg allocatableRegs
1051 -- these are the regs which we cannot assume stay alive over a
1053 callClobberedRegs :: [Reg]
1056 #if alpha_TARGET_ARCH
1057 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1058 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1059 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1060 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1061 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1062 #endif /* alpha_TARGET_ARCH */
1063 #if i386_TARGET_ARCH
1064 -- caller-saves registers
1065 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1066 #endif /* i386_TARGET_ARCH */
1067 #if x86_64_TARGET_ARCH
1068 -- caller-saves registers
1069 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1070 -- all xmm regs are caller-saves
1071 #endif /* x86_64_TARGET_ARCH */
1072 #if sparc_TARGET_ARCH
1075 [oReg i | i <- [0..5]] ++
1076 [gReg i | i <- [1..7]] ++
1077 [fReg i | i <- [0..31]] )
1078 #endif /* sparc_TARGET_ARCH */
1079 #if powerpc_TARGET_ARCH
1080 #if darwin_TARGET_OS
1081 map RealReg (0:[2..12] ++ map fReg [0..13])
1082 #elif linux_TARGET_OS
1083 map RealReg (0:[2..13] ++ map fReg [0..13])
1085 #endif /* powerpc_TARGET_ARCH */
1088 -- argRegs is the set of regs which are read for an n-argument call to C.
1089 -- For archs which pass all args on the stack (x86), is empty.
1090 -- Sparc passes up to the first 6 args in regs.
1091 -- Dunno about Alpha.
1092 argRegs :: RegNo -> [Reg]
1094 #if i386_TARGET_ARCH
1095 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1098 #if x86_64_TARGET_ARCH
1099 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1102 #if alpha_TARGET_ARCH
1104 argRegs 1 = freeMappedRegs [16, fReg 16]
1105 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1106 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1107 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1108 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1109 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1110 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1111 #endif /* alpha_TARGET_ARCH */
1113 #if sparc_TARGET_ARCH
1115 argRegs 1 = map (RealReg . oReg) [0]
1116 argRegs 2 = map (RealReg . oReg) [0,1]
1117 argRegs 3 = map (RealReg . oReg) [0,1,2]
1118 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1119 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1120 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1121 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1122 #endif /* sparc_TARGET_ARCH */
1124 #if powerpc_TARGET_ARCH
1126 argRegs 1 = map RealReg [3]
1127 argRegs 2 = map RealReg [3,4]
1128 argRegs 3 = map RealReg [3..5]
1129 argRegs 4 = map RealReg [3..6]
1130 argRegs 5 = map RealReg [3..7]
1131 argRegs 6 = map RealReg [3..8]
1132 argRegs 7 = map RealReg [3..9]
1133 argRegs 8 = map RealReg [3..10]
1134 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1135 #endif /* powerpc_TARGET_ARCH */
1138 -- all of the arg regs ??
1139 #if alpha_TARGET_ARCH
1140 allArgRegs :: [(Reg, Reg)]
1141 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1142 #endif /* alpha_TARGET_ARCH */
1144 #if sparc_TARGET_ARCH
1146 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1147 #endif /* sparc_TARGET_ARCH */
1149 #if i386_TARGET_ARCH
1151 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1154 #if x86_64_TARGET_ARCH
1156 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1157 allFPArgRegs :: [Reg]
1158 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1161 #if powerpc_TARGET_ARCH
1163 allArgRegs = map RealReg [3..10]
1164 allFPArgRegs :: [Reg]
1165 #if darwin_TARGET_OS
1166 allFPArgRegs = map (RealReg . fReg) [1..13]
1167 #elif linux_TARGET_OS
1168 allFPArgRegs = map (RealReg . fReg) [1..8]
1170 #endif /* powerpc_TARGET_ARCH */
1174 freeReg :: RegNo -> FastBool
1176 #if alpha_TARGET_ARCH
1177 freeReg 26 = fastBool False -- return address (ra)
1178 freeReg 28 = fastBool False -- reserved for the assembler (at)
1179 freeReg 29 = fastBool False -- global pointer (gp)
1180 freeReg 30 = fastBool False -- stack pointer (sp)
1181 freeReg 31 = fastBool False -- always zero (zeroh)
1182 freeReg 63 = fastBool False -- always zero (f31)
1185 #if i386_TARGET_ARCH
1186 freeReg esp = fastBool False -- %esp is the C stack pointer
1189 #if x86_64_TARGET_ARCH
1190 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1193 #if sparc_TARGET_ARCH
1194 freeReg g0 = fastBool False -- %g0 is always 0.
1195 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1196 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1197 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1198 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1199 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1200 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1201 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1202 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1203 freeReg f1 = fastBool False
1206 #if powerpc_TARGET_ARCH
1207 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1208 freeReg 1 = fastBool False -- The Stack Pointer
1209 #if !darwin_TARGET_OS
1210 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1211 freeReg 2 = fastBool False
1216 freeReg REG_Base = fastBool False
1219 freeReg REG_R1 = fastBool False
1222 freeReg REG_R2 = fastBool False
1225 freeReg REG_R3 = fastBool False
1228 freeReg REG_R4 = fastBool False
1231 freeReg REG_R5 = fastBool False
1234 freeReg REG_R6 = fastBool False
1237 freeReg REG_R7 = fastBool False
1240 freeReg REG_R8 = fastBool False
1243 freeReg REG_F1 = fastBool False
1246 freeReg REG_F2 = fastBool False
1249 freeReg REG_F3 = fastBool False
1252 freeReg REG_F4 = fastBool False
1255 freeReg REG_D1 = fastBool False
1258 freeReg REG_D2 = fastBool False
1261 freeReg REG_Sp = fastBool False
1264 freeReg REG_Su = fastBool False
1267 freeReg REG_SpLim = fastBool False
1270 freeReg REG_Hp = fastBool False
1273 freeReg REG_HpLim = fastBool False
1275 freeReg n = fastBool True
1278 -- | Returns 'Nothing' if this global register is not stored
1279 -- in a real machine register, otherwise returns @'Just' reg@, where
1280 -- reg is the machine register it is stored in.
1282 globalRegMaybe :: GlobalReg -> Maybe Reg
1285 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1288 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1291 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1294 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1297 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1300 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1303 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1306 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1309 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1312 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1315 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1318 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1321 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1324 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1327 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1330 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1333 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1336 globalRegMaybe Sp = Just (RealReg REG_Sp)
1339 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1342 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1345 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1348 globalRegMaybe Hp = Just (RealReg REG_Hp)
1351 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1353 #ifdef REG_CurrentTSO
1354 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1356 #ifdef REG_CurrentNursery
1357 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1359 globalRegMaybe _ = Nothing