1 {-# OPTIONS -fno-warn-missing-signatures #-}
2 -- | Graph coloring register allocator.
4 -- TODO: The colors in graphviz graphs for x86_64 and ppc could be nicer.
7 module RegAlloc.Graph.Main (
13 import qualified GraphColor as Color
14 import qualified GraphBase as Color
15 import RegAlloc.Liveness
16 import RegAlloc.Graph.Spill
17 import RegAlloc.Graph.SpillClean
18 import RegAlloc.Graph.SpillCost
19 import RegAlloc.Graph.Stats
20 import RegAlloc.Graph.TrivColorable
38 -- | The maximum number of build\/spill cycles we'll allow.
39 -- We should only need 3 or 4 cycles tops.
40 -- If we run for any longer than this we're probably in an infinite loop,
41 -- It's probably better just to bail out and report a bug at this stage.
46 -- | The top level of the graph coloring register allocator.
49 :: (Outputable instr, Instruction instr)
51 -> UniqFM (UniqSet RealReg) -- ^ the registers we can use for allocation
52 -> UniqSet Int -- ^ the set of available spill slots.
53 -> [LiveCmmTop instr] -- ^ code annotated with liveness information.
54 -> UniqSM ( [NatCmmTop instr], [RegAllocStats instr] )
55 -- ^ code with registers allocated and stats for each stage of
58 regAlloc dflags regsFree slotsFree code
60 -- TODO: the regClass function is currently hard coded to the default target
61 -- architecture. Would prefer to determine this from dflags.
62 -- There are other uses of targetRegClass later in this module.
63 let triv = trivColorable
64 targetVirtualRegSqueeze
67 (code_final, debug_codeGraphs, _)
68 <- regAlloc_spin dflags 0
70 regsFree slotsFree [] code
73 , reverse debug_codeGraphs )
78 (triv :: Color.Triv VirtualReg RegClass RealReg)
79 (regsFree :: UniqFM (UniqSet RealReg))
84 -- if any of these dump flags are turned on we want to hang on to
85 -- intermediate structures in the allocator - otherwise tell the
86 -- allocator to ditch them early so we don't end up creating space leaks.
88 [ dopt Opt_D_dump_asm_regalloc_stages dflags
89 , dopt Opt_D_dump_asm_stats dflags
90 , dopt Opt_D_dump_asm_conflicts dflags ]
92 -- check that we're not running off down the garden path.
93 when (spinCount > maxSpinCount)
94 $ pprPanic "regAlloc_spin: max build/spill cycle count exceeded."
95 ( text "It looks like the register allocator is stuck in an infinite loop."
96 $$ text "max cycles = " <> int maxSpinCount
97 $$ text "regsFree = " <> (hcat $ punctuate space $ map ppr
98 $ uniqSetToList $ unionManyUniqSets $ eltsUFM regsFree)
99 $$ text "slotsFree = " <> ppr (sizeUniqSet slotsFree))
101 -- build a conflict graph from the code.
102 (graph :: Color.Graph VirtualReg RegClass RealReg)
103 <- {-# SCC "BuildGraph" #-} buildGraph code
106 -- We really do want the graph to be fully evaluated _before_ we start coloring.
107 -- If we don't do this now then when the call to Color.colorGraph forces bits of it,
108 -- the heap will be filled with half evaluated pieces of graph and zillions of apply thunks.
110 seqGraph graph `seq` return ()
113 -- build a map of the cost of spilling each instruction
114 -- this will only actually be computed if we have to spill something.
115 let spillCosts = foldl' plusSpillCostInfo zeroSpillCostInfo
116 $ map slurpSpillCostInfo code
118 -- the function to choose regs to leave uncolored
119 let spill = chooseSpill spillCosts
121 -- record startup state
124 then Just $ RegAllocStatsStart
127 , raSpillCosts = spillCosts }
130 -- try and color the graph
131 let (graph_colored, rsSpill, rmCoalesce)
132 = {-# SCC "ColorGraph" #-}
134 (dopt Opt_RegsIterative dflags)
136 regsFree triv spill graph
138 -- rewrite regs in the code that have been coalesced
140 | RegVirtual vr <- reg
141 = case lookupUFM rmCoalesce vr of
142 Just vr' -> patchF (RegVirtual vr')
149 = map (patchEraseLive patchF) code
152 -- see if we've found a coloring
153 if isEmptyUniqSet rsSpill
155 -- if -fasm-lint is turned on then validate the graph
156 let graph_colored_lint =
157 if dopt Opt_DoAsmLinting dflags
158 then Color.validateGraph (text "")
159 True -- require all nodes to be colored
163 -- patch the registers using the info in the graph
164 let code_patched = map (patchRegsFromGraph graph_colored_lint) code_coalesced
166 -- clean out unneeded SPILL/RELOADs
167 let code_spillclean = map cleanSpills code_patched
169 -- strip off liveness information,
170 -- and rewrite SPILL/RELOAD pseudos into real instructions along the way
171 let code_final = map stripLive code_spillclean
173 -- let spillNatTop = mapGenBlockTop spillNatBlock
174 -- let code_final = map spillNatTop code_nat
176 -- record what happened in this stage for debugging
180 , raGraphColored = graph_colored_lint
181 , raCoalesced = rmCoalesce
182 , raPatched = code_patched
183 , raSpillClean = code_spillclean
184 , raFinal = code_final
185 , raSRMs = foldl' addSRM (0, 0, 0) $ map countSRMs code_spillclean }
189 if dump then [stat] ++ maybeToList stat1 ++ debug_codeGraphs
192 -- space leak avoidance
193 seqList statList `seq` return ()
197 , graph_colored_lint)
199 -- we couldn't find a coloring, time to spill something
201 -- if -fasm-lint is turned on then validate the graph
202 let graph_colored_lint =
203 if dopt Opt_DoAsmLinting dflags
204 then Color.validateGraph (text "")
205 False -- don't require nodes to be colored
209 -- spill the uncolored regs
210 (code_spilled, slotsFree', spillStats)
211 <- regSpill code_coalesced slotsFree rsSpill
213 -- recalculate liveness
214 let code_nat = map stripLive code_spilled
215 code_relive <- mapM regLiveness code_nat
217 -- record what happened in this stage for debugging
220 { raGraph = graph_colored_lint
221 , raCoalesced = rmCoalesce
222 , raSpillStats = spillStats
223 , raSpillCosts = spillCosts
224 , raSpilled = code_spilled }
228 then [stat] ++ maybeToList stat1 ++ debug_codeGraphs
231 -- space leak avoidance
232 seqList statList `seq` return ()
234 regAlloc_spin dflags (spinCount + 1) triv regsFree slotsFree'
240 -- | Build a graph from the liveness and coalesce information in this code.
244 => [LiveCmmTop instr]
245 -> UniqSM (Color.Graph VirtualReg RegClass RealReg)
249 -- Slurp out the conflicts and reg->reg moves from this code
250 let (conflictList, moveList) =
251 unzip $ map slurpConflicts code
253 -- Slurp out the spill/reload coalesces
254 let moveList2 = map slurpReloadCoalesce code
256 -- Add the reg-reg conflicts to the graph
257 let conflictBag = unionManyBags conflictList
258 let graph_conflict = foldrBag graphAddConflictSet Color.initGraph conflictBag
260 -- Add the coalescences edges to the graph.
261 let moveBag = unionBags (unionManyBags moveList2) (unionManyBags moveList)
262 let graph_coalesce = foldrBag graphAddCoalesce graph_conflict moveBag
264 return graph_coalesce
267 -- | Add some conflict edges to the graph.
268 -- Conflicts between virtual and real regs are recorded as exclusions.
272 -> Color.Graph VirtualReg RegClass RealReg
273 -> Color.Graph VirtualReg RegClass RealReg
275 graphAddConflictSet set graph
276 = let virtuals = mkUniqSet
277 [ vr | RegVirtual vr <- uniqSetToList set ]
279 graph1 = Color.addConflicts virtuals classOfVirtualReg graph
281 graph2 = foldr (\(r1, r2) -> Color.addExclusion r1 classOfVirtualReg r2)
284 | RegVirtual vr <- uniqSetToList set
285 , RegReal rr <- uniqSetToList set]
290 -- | Add some coalesence edges to the graph
291 -- Coalesences between virtual and real regs are recorded as preferences.
295 -> Color.Graph VirtualReg RegClass RealReg
296 -> Color.Graph VirtualReg RegClass RealReg
298 graphAddCoalesce (r1, r2) graph
300 , RegVirtual vr <- r2
301 = Color.addPreference (vr, classOfVirtualReg vr) rr graph
304 , RegVirtual vr <- r1
305 = Color.addPreference (vr, classOfVirtualReg vr) rr graph
307 | RegVirtual vr1 <- r1
308 , RegVirtual vr2 <- r2
310 (vr1, classOfVirtualReg vr1)
311 (vr2, classOfVirtualReg vr2)
314 -- We can't coalesce two real regs, but there could well be existing
315 -- hreg,hreg moves in the input code. We'll just ignore these
316 -- for coalescing purposes.
322 -- | Patch registers in code using the reg -> reg mapping in this graph.
324 :: (Outputable instr, Instruction instr)
325 => Color.Graph VirtualReg RegClass RealReg
326 -> LiveCmmTop instr -> LiveCmmTop instr
328 patchRegsFromGraph graph code
330 -- a function to lookup the hardreg for a virtual reg from the graph.
332 -- leave real regs alone.
336 -- this virtual has a regular node in the graph.
337 | RegVirtual vr <- reg
338 , Just node <- Color.lookupNode graph vr
339 = case Color.nodeColor node of
340 Just color -> RegReal color
341 Nothing -> RegVirtual vr
343 -- no node in the graph for this virtual, bad news.
345 = pprPanic "patchRegsFromGraph: register mapping failed."
346 ( text "There is no node in the graph for register " <> ppr reg
351 targetVirtualRegSqueeze
352 targetRealRegSqueeze)
355 in patchEraseLive patchF code
359 -- for when laziness just isn't what you wanted...
361 seqGraph :: Color.Graph VirtualReg RegClass RealReg -> ()
362 seqGraph graph = seqNodes (eltsUFM (Color.graphMap graph))
364 seqNodes :: [Color.Node VirtualReg RegClass RealReg] -> ()
368 (n : ns) -> seqNode n `seq` seqNodes ns
370 seqNode :: Color.Node VirtualReg RegClass RealReg -> ()
372 = seqVirtualReg (Color.nodeId node)
373 `seq` seqRegClass (Color.nodeClass node)
374 `seq` seqMaybeRealReg (Color.nodeColor node)
375 `seq` (seqVirtualRegList (uniqSetToList (Color.nodeConflicts node)))
376 `seq` (seqRealRegList (uniqSetToList (Color.nodeExclusions node)))
377 `seq` (seqRealRegList (Color.nodePreference node))
378 `seq` (seqVirtualRegList (uniqSetToList (Color.nodeCoalesce node)))
380 seqVirtualReg :: VirtualReg -> ()
388 seqRealReg :: RealReg -> ()
391 RealRegSingle _ -> ()
392 RealRegPair _ _ -> ()
394 seqRegClass :: RegClass -> ()
401 seqMaybeRealReg :: Maybe RealReg -> ()
405 Just r -> seqRealReg r
407 seqVirtualRegList :: [VirtualReg] -> ()
411 (r : rs) -> seqVirtualReg r `seq` seqVirtualRegList rs
413 seqRealRegList :: [RealReg] -> ()
417 (r : rs) -> seqRealReg r `seq` seqRealRegList rs
423 (r : rs) -> r `seq` seqList rs