2 % (c) The AQUA Project, Glasgow University, 1993-1996
4 \section[MachMisc]{Description of various machine-specific things}
7 #include "HsVersions.h"
8 #include "nativeGen/NCG.h"
12 fixedHdrSizeInWords, varHdrSizeInWords,
13 charLikeSize, intLikeSize, mutHS, dataHS,
14 sizeOf, primRepToSize,
18 volatileSaves, volatileRestores,
20 storageMgrInfo, smCAFlist, smOldLim, smOldMutables,
23 targetMaxDouble, targetMaxInt, targetMinDouble, targetMinInt,
30 Instr(..), IF_ARCH_i386(Operand(..) COMMA,)
45 IMPORT_DELOOPER(AbsCLoop) ( fixedHdrSizeInWords, varHdrSizeInWords ) -- paranoia
46 IMPORT_DELOOPER(NcgLoop) ( underscorePrefix, fmtAsmLbl ) -- paranoia
47 IMPORT_1_3(Char(isDigit))
49 import AbsCSyn ( MagicId(..) )
50 import AbsCUtils ( magicIdPrimRep )
51 import CmdLineOpts ( opt_SccProfilingOn )
52 import Literal ( mkMachInt, Literal(..) )
53 import MachRegs ( stgReg, callerSaves, RegLoc(..),
54 Imm(..), Reg(..), Addr
56 import OrdList ( OrdList )
57 import PrimRep ( PrimRep(..) )
58 import SMRep ( SMRep(..), SMSpecRepKind(..), SMUpdateKind(..) )
59 import Stix ( StixTree(..), StixReg(..), sStLitLbl,
66 underscorePrefix :: Bool -- leading underscore on labels?
70 ,{-else-} IF_ARCH_i386(
74 , {-otherwise-} False)))
75 ,{-else-}IF_ARCH_sparc(
76 IF_OS_sunos4(True, {-otherwise-} False)
79 ---------------------------
80 fmtAsmLbl :: String -> String -- for formatting labels
84 {- The alpha assembler likes temporary labels to look like $L123
85 instead of L123. (Don't toss the L, because then Lf28
93 ---------------------------
94 cvtLitLit :: String -> String
96 -- ToDo: some kind of *careful* attention needed...
98 cvtLitLit "stdin" = IF_ARCH_alpha("_iob+0" {-probably OK...-}
99 ,IF_ARCH_i386("_IO_stdin_"
100 ,IF_ARCH_sparc("__iob+0x0"{-probably OK...-}
102 cvtLitLit "stdout" = IF_ARCH_alpha("_iob+56"{-dodgy *at best*...-}
103 ,IF_ARCH_i386("_IO_stdout_"
104 ,IF_ARCH_sparc("__iob+0x14"{-dodgy *at best*...-}
106 cvtLitLit "stderr" = IF_ARCH_alpha("_iob+112"{-dodgy *at best*...-}
107 ,IF_ARCH_i386("_IO_stderr_"
108 ,IF_ARCH_sparc("__iob+0x28"{-dodgy *at best*...-}
112 | otherwise = error ("Native code generator can't handle ``" ++ s ++ "''")
114 isHex ('0':'x':xs) = all isHexDigit xs
116 -- Now, where have I seen this before?
117 isHexDigit c = isDigit c || c >= 'A' && c <= 'F' || c >= 'a' && c <= 'f'
120 % ----------------------------------------------------------------
122 We (allegedly) put the first six C-call arguments in registers;
123 where do we start putting the rest of them?
125 eXTRA_STK_ARGS_HERE :: Int
127 = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,???)))
130 % ----------------------------------------------------------------
132 @fixedHdrSizeInWords@ and @varHdrSizeInWords@: these are not dependent
133 on target architecture.
135 fixedHdrSizeInWords :: Int
138 = 1{-info ptr-} + profFHS + parFHS + tickyFHS
139 -- obviously, we aren't taking non-sequential too seriously yet
141 profFHS = if opt_SccProfilingOn then 1 else 0
142 parFHS = {-if PAR or GRAN then 1 else-} 0
143 tickyFHS = {-if ticky ... then 1 else-} 0
145 varHdrSizeInWords :: SMRep -> Int{-in words-}
150 SpecialisedRep _ _ _ _ -> 0
151 GenericRep _ _ _ -> 0
153 MuTupleRep _ -> 2 {- (1 + GC_MUT_RESERVED_WORDS) -}
157 PhantomRep -> panic "MachMisc.varHdrSizeInWords:phantom"
160 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
162 Static closure sizes:
164 charLikeSize, intLikeSize :: Int
166 charLikeSize = blahLikeSize CharLikeRep
167 intLikeSize = blahLikeSize IntLikeRep
170 = fromInteger (sizeOf PtrRep)
171 * (fixedHdrSizeInWords + varHdrSizeInWords blahLikeRep + 1)
173 blahLikeRep = SpecialisedRep blah 0 1 SMNormalForm
176 mutHS, dataHS :: StixTree
178 mutHS = blah_hs (MuTupleRep 0)
179 dataHS = blah_hs (DataRep 0)
182 = StInt (toInteger words)
184 words = fixedHdrSizeInWords + varHdrSizeInWords blah
187 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
189 Size of a @PrimRep@, in bytes.
192 sizeOf :: PrimRep -> Integer{-in bytes-}
193 -- the result is an Integer only because it's more convenient
195 sizeOf pr = case (primRepToSize pr) of
196 IF_ARCH_alpha({B -> 1; BU -> 1; {-W -> 2; WU -> 2; L -> 4; SF -> 4;-} _ -> 8},)
197 IF_ARCH_sparc({B -> 1; BU -> 1; {-HW -> 2; HWU -> 2;-} W -> 4; {-D -> 8;-} F -> 4; DF -> 8},)
198 IF_ARCH_i386( {B -> 1; {-S -> 2;-} L -> 4; F -> 4; DF -> 8 },)
201 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
203 Now the volatile saves and restores. We add the basic guys to the
204 list of ``user'' registers provided. Note that there are more basic
205 registers on the restore list, because some are reloaded from
208 (@volatileRestores@ used only for wrapper-hungry PrimOps.)
211 volatileSaves, volatileRestores :: [MagicId] -> [StixTree]
213 save_cands = [BaseReg,SpA,SuA,SpB,SuB,Hp,HpLim,RetReg]
214 restore_cands = save_cands ++ [StkStubReg,StdUpdRetVecReg]
217 = map save ((filter callerSaves) (save_cands ++ vols))
219 save x = StAssign (magicIdPrimRep x) loc reg
221 reg = StReg (StixMagicId x)
222 loc = case stgReg x of
224 Always _ -> panic "volatileSaves"
226 volatileRestores vols
227 = map restore ((filter callerSaves) (restore_cands ++ vols))
229 restore x = StAssign (magicIdPrimRep x) reg loc
231 reg = StReg (StixMagicId x)
232 loc = case stgReg x of
234 Always _ -> panic "volatileRestores"
237 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
239 Obviously slightly weedy
240 (Note that the floating point values aren't terribly important.)
243 targetMinDouble = MachDouble (-1.7976931348623157e+308)
244 targetMaxDouble = MachDouble (1.7976931348623157e+308)
245 targetMinInt = mkMachInt (-2147483647)
246 targetMaxInt = mkMachInt 2147483647
249 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
251 Storage manager nonsense. Note that the indices are dependent on
252 the definition of the smInfo structure in SMinterface.lh
255 storageMgrInfo, smCAFlist, smOldMutables, smOldLim :: StixTree
257 storageMgrInfo = sStLitLbl SLIT("StorageMgrInfo")
258 smCAFlist = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_CAFLIST))
259 smOldMutables = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_OLDMUTABLES))
260 smOldLim = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_OLDLIM))
261 smStablePtrTable = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_STABLEPOINTERTABLE))
264 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
266 This algorithm for determining the $\log_2$ of exact powers of 2 comes
267 from GCC. It requires bit manipulation primitives, and we use GHC
275 exactLog2 :: Integer -> Maybe Integer
277 = if (x <= 0 || x >= 2147483648) then
280 case (fromInteger x) of { I# x# ->
281 if (w2i ((i2w x#) `and#` (i2w (0# -# x#))) /=# x#) then
284 Just (toInteger (I# (pow2 x#)))
287 shiftr x y = shiftRA# x y
289 pow2 x# | x# ==# 1# = 0#
290 | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` i2w_s 1#))
293 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
297 #if alpha_TARGET_ARCH
298 = ALWAYS -- For BI (same as BR)
299 | EQQ -- For CMP and BI (NB: "EQ" is a 1.3 Prelude name)
301 | GTT -- For BI only (NB: "GT" is a 1.3 Prelude name)
302 | LE -- For CMP and BI
303 | LTT -- For CMP and BI (NB: "LT" is a 1.3 Prelude name)
305 | NEVER -- For BI (null instruction)
306 | ULE -- For CMP only
307 | ULT -- For CMP only
310 = ALWAYS -- What's really used? ToDo
324 #if sparc_TARGET_ARCH
325 = ALWAYS -- What's really used? ToDo
346 #if alpha_TARGET_ARCH
349 -- | W -- word (2 bytes): UNUSED
351 -- | L -- longword (4 bytes): UNUSED
352 | Q -- quadword (8 bytes)
353 -- | FF -- VAX F-style floating pt: UNUSED
354 -- | GF -- VAX G-style floating pt: UNUSED
355 -- | DF -- VAX D-style floating pt: UNUSED
356 -- | SF -- IEEE single-precision floating pt: UNUSED
357 | TF -- IEEE double-precision floating pt
361 -- | HB -- higher byte **UNUSED**
364 | F -- IEEE single-precision floating pt
365 | DF -- IEEE single-precision floating pt
367 #if sparc_TARGET_ARCH
369 | BU -- byte (unsigned)
370 -- | HW -- halfword, 2 bytes (signed): UNUSED
371 -- | HWU -- halfword, 2 bytes (unsigned): UNUSED
373 -- | D -- doubleword, 8 bytes: UNUSED
374 | F -- IEEE single-precision floating pt
375 | DF -- IEEE single-precision floating pt
378 primRepToSize :: PrimRep -> Size
380 primRepToSize PtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
381 primRepToSize CodePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
382 primRepToSize DataPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
383 primRepToSize RetRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
384 primRepToSize CostCentreRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
385 primRepToSize CharRep = IF_ARCH_alpha( BU, IF_ARCH_i386( L, IF_ARCH_sparc( BU,)))
386 primRepToSize IntRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
387 primRepToSize WordRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
388 primRepToSize AddrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
389 primRepToSize FloatRep = IF_ARCH_alpha( TF, IF_ARCH_i386( F, IF_ARCH_sparc( F ,)))
390 primRepToSize DoubleRep = IF_ARCH_alpha( TF, IF_ARCH_i386( DF,IF_ARCH_sparc( DF,)))
391 primRepToSize ArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
392 primRepToSize ByteArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
393 primRepToSize StablePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
394 primRepToSize ForeignObjRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
397 %************************************************************************
399 \subsection{Machine's assembly language}
401 %************************************************************************
403 We have a few common ``instructions'' (nearly all the pseudo-ops) but
404 mostly all of @Instr@ is machine-specific.
408 = COMMENT FAST_STRING -- comment pseudo-op
409 | SEGMENT CodeSegment -- {data,text} segment pseudo-op
410 | LABEL CLabel -- global label pseudo-op
411 | ASCII Bool -- True <=> needs backslash conversion
412 String -- the literal string
418 #if alpha_TARGET_ARCH
420 -- data Instr continues...
424 | LD Size Reg Addr -- size, dst, src
425 | LDA Reg Addr -- dst, src
426 | LDAH Reg Addr -- dst, src
427 | LDGP Reg Addr -- dst, src
428 | LDI Size Reg Imm -- size, dst, src
429 | ST Size Reg Addr -- size, src, dst
434 | ABS Size RI Reg -- size, src, dst
435 | NEG Size Bool RI Reg -- size, overflow, src, dst
436 | ADD Size Bool Reg RI Reg -- size, overflow, src, src, dst
437 | SADD Size Size Reg RI Reg -- size, scale, src, src, dst
438 | SUB Size Bool Reg RI Reg -- size, overflow, src, src, dst
439 | SSUB Size Size Reg RI Reg -- size, scale, src, src, dst
440 | MUL Size Bool Reg RI Reg -- size, overflow, src, src, dst
441 | DIV Size Bool Reg RI Reg -- size, unsigned, src, src, dst
442 | REM Size Bool Reg RI Reg -- size, unsigned, src, src, dst
444 -- Simple bit-twiddling.
464 | CMP Cond Reg RI Reg
471 | FADD Size Reg Reg Reg
472 | FDIV Size Reg Reg Reg
473 | FMUL Size Reg Reg Reg
474 | FSUB Size Reg Reg Reg
475 | CVTxy Size Size Reg Reg
476 | FCMP Size Cond Reg Reg Reg
488 -- Alpha-specific pseudo-ops.
497 #endif {- alpha_TARGET_ARCH -}
503 -- data Instr continues...
507 | MOV Size Operand Operand
508 | MOVZX Size Operand Operand -- size is the size of operand 2
509 | MOVSX Size Operand Operand -- size is the size of operand 2
511 -- Load effective address (also a very useful three-operand add instruction :-)
513 | LEA Size Operand Operand
517 | ADD Size Operand Operand
518 | SUB Size Operand Operand
520 -- Multiplication (signed and unsigned), Division (signed and unsigned),
521 -- result in %eax, %edx.
523 | IMUL Size Operand Operand
526 -- Simple bit-twiddling.
528 | AND Size Operand Operand
529 | OR Size Operand Operand
530 | XOR Size Operand Operand
532 | NEGI Size Operand -- NEG instruction (name clash with Cond)
533 | SHL Size Operand Operand -- 1st operand must be an Imm
534 | SAR Size Operand Operand -- 1st operand must be an Imm
535 | SHR Size Operand Operand -- 1st operand must be an Imm
538 -- Float Arithmetic. -- ToDo for 386
540 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
541 -- right up until we spit them out.
543 | SAHF -- stores ah into flags
545 | FADD Size Operand -- src
547 | FIADD Size Addr -- src
549 | FCOM Size Operand -- src
551 | FDIV Size Operand -- src
553 | FIDIV Size Addr -- src
554 | FDIVR Size Operand -- src
556 | FIDIVR Size Addr -- src
557 | FICOM Size Addr -- src
558 | FILD Size Addr Reg -- src, dst
559 | FIST Size Addr -- dst
560 | FLD Size Operand -- src
563 | FMUL Size Operand -- src
565 | FIMUL Size Addr -- src
569 | FST Size Operand -- dst
570 | FSTP Size Operand -- dst
571 | FSUB Size Operand -- src
573 | FISUB Size Addr -- src
574 | FSUBR Size Operand -- src
576 | FISUBR Size Addr -- src
578 | FCOMP Size Operand -- src
586 | TEST Size Operand Operand
587 | CMP Size Operand Operand
597 | JMP Operand -- target
598 | JXX Cond CLabel -- target
603 | CLTD -- sign extend %eax into %edx:%eax
606 = OpReg Reg -- register
607 | OpImm Imm -- immediate value
608 | OpAddr Addr -- memory reference
610 #endif {- i386_TARGET_ARCH -}
614 #if sparc_TARGET_ARCH
616 -- data Instr continues...
620 | LD Size Addr Reg -- size, src, dst
621 | ST Size Reg Addr -- size, src, dst
625 | ADD Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
626 | SUB Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
628 -- Simple bit-twiddling.
630 | AND Bool Reg RI Reg -- cc?, src1, src2, dst
631 | ANDN Bool Reg RI Reg -- cc?, src1, src2, dst
632 | OR Bool Reg RI Reg -- cc?, src1, src2, dst
633 | ORN Bool Reg RI Reg -- cc?, src1, src2, dst
634 | XOR Bool Reg RI Reg -- cc?, src1, src2, dst
635 | XNOR Bool Reg RI Reg -- cc?, src1, src2, dst
636 | SLL Reg RI Reg -- src1, src2, dst
637 | SRL Reg RI Reg -- src1, src2, dst
638 | SRA Reg RI Reg -- src1, src2, dst
639 | SETHI Imm Reg -- src, dst
640 | NOP -- Really SETHI 0, %g0, but worth an alias
644 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
645 -- right up until we spit them out.
647 | FABS Size Reg Reg -- src dst
648 | FADD Size Reg Reg Reg -- src1, src2, dst
649 | FCMP Bool Size Reg Reg -- exception?, src1, src2, dst
650 | FDIV Size Reg Reg Reg -- src1, src2, dst
651 | FMOV Size Reg Reg -- src, dst
652 | FMUL Size Reg Reg Reg -- src1, src2, dst
653 | FNEG Size Reg Reg -- src, dst
654 | FSQRT Size Reg Reg -- src, dst
655 | FSUB Size Reg Reg Reg -- src1, src2, dst
656 | FxTOy Size Size Reg Reg -- src, dst
660 | BI Cond Bool Imm -- cond, annul?, target
661 | BF Cond Bool Imm -- cond, annul?, target
664 | CALL Imm Int Bool -- target, args, terminal
671 riZero (RIImm (ImmInt 0)) = True
672 riZero (RIImm (ImmInteger 0)) = True
673 riZero (RIReg (FixedReg ILIT(0))) = True
676 #endif {- sparc_TARGET_ARCH -}