2 % (c) The AQUA Project, Glasgow University, 1993-1996
4 \section[MachMisc]{Description of various machine-specific things}
7 #include "HsVersions.h"
8 #include "nativeGen/NCG.h"
12 fixedHdrSizeInWords, varHdrSizeInWords,
13 charLikeSize, intLikeSize, mutHS, dataHS,
14 sizeOf, primRepToSize,
18 volatileSaves, volatileRestores,
20 storageMgrInfo, smCAFlist, smOldLim, smOldMutables,
23 targetMaxDouble, targetMaxInt, targetMinDouble, targetMinInt,
30 Instr(..), IF_ARCH_i386(Operand(..) COMMA,)
45 IMPORT_DELOOPER(AbsCLoop) ( fixedHdrSizeInWords, varHdrSizeInWords ) -- paranoia
46 IMPORT_DELOOPER(NcgLoop) ( underscorePrefix, fmtAsmLbl ) -- paranoia
47 IMPORT_1_3(Char(isDigit))
49 import AbsCSyn ( MagicId(..) )
50 import AbsCUtils ( magicIdPrimRep )
51 import CmdLineOpts ( opt_SccProfilingOn )
52 import Literal ( mkMachInt, Literal(..) )
53 import MachRegs ( stgReg, callerSaves, RegLoc(..),
54 Imm(..), Reg(..), Addr
56 import OrdList ( OrdList )
57 import PrimRep ( PrimRep(..) )
58 import SMRep ( SMRep(..), SMSpecRepKind(..), SMUpdateKind(..) )
59 import Stix ( StixTree(..), StixReg(..), sStLitLbl,
66 underscorePrefix :: Bool -- leading underscore on labels?
70 ,{-else-} IF_ARCH_i386(
75 , {-otherwise-} False)))
77 ,{-else-}IF_ARCH_sparc(
78 IF_OS_sunos4(True, {-otherwise-} False)
81 ---------------------------
82 fmtAsmLbl :: String -> String -- for formatting labels
86 {- The alpha assembler likes temporary labels to look like $L123
87 instead of L123. (Don't toss the L, because then Lf28
95 ---------------------------
96 cvtLitLit :: String -> String
99 -- Rather than relying on guessing, use FILE_SIZE to compute the
102 cvtLitLit "stdin" = IF_ARCH_alpha("_iob+0" {-probably OK...-}
103 ,IF_ARCH_i386("_IO_stdin_"
104 ,IF_ARCH_sparc("__iob+0x0"{-probably OK...-}
107 cvtLitLit "stdout" = IF_ARCH_alpha("_iob+"++show (``FILE_SIZE''::Int)
108 ,IF_ARCH_i386("_IO_stdout_"
109 ,IF_ARCH_sparc("__iob+"++show (``FILE_SIZE''::Int)
111 cvtLitLit "stderr" = IF_ARCH_alpha("_iob+"++show (2*(``FILE_SIZE''::Int))
112 ,IF_ARCH_i386("_IO_stderr_"
113 ,IF_ARCH_sparc("__iob+"++show (2*(``FILE_SIZE''::Int))
116 cvtLitLit "stdout" = IF_ARCH_alpha("_iob+56"{-dodgy *at best*...-}
117 ,IF_ARCH_i386("_IO_stdout_"
118 ,IF_ARCH_sparc("__iob+0x10"{-dodgy *at best*...-}
120 cvtLitLit "stderr" = IF_ARCH_alpha("_iob+112"{-dodgy *at best*...-}
121 ,IF_ARCH_i386("_IO_stderr_"
122 ,IF_ARCH_sparc("__iob+0x20"{-dodgy *at best*...-}
127 | otherwise = error ("Native code generator can't handle ``" ++ s ++ "''")
129 isHex ('0':'x':xs) = all isHexDigit xs
131 -- Now, where have I seen this before?
132 isHexDigit c = isDigit c || c >= 'A' && c <= 'F' || c >= 'a' && c <= 'f'
135 % ----------------------------------------------------------------
137 We (allegedly) put the first six C-call arguments in registers;
138 where do we start putting the rest of them?
140 eXTRA_STK_ARGS_HERE :: Int
142 = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,???)))
145 % ----------------------------------------------------------------
147 @fixedHdrSizeInWords@ and @varHdrSizeInWords@: these are not dependent
148 on target architecture.
150 fixedHdrSizeInWords :: Int
153 = 1{-info ptr-} + profFHS + parFHS + tickyFHS
154 -- obviously, we aren't taking non-sequential too seriously yet
156 profFHS = if opt_SccProfilingOn then 1 else 0
157 parFHS = {-if PAR or GRAN then 1 else-} 0
158 tickyFHS = {-if ticky ... then 1 else-} 0
160 varHdrSizeInWords :: SMRep -> Int{-in words-}
165 SpecialisedRep _ _ _ _ -> 0
166 GenericRep _ _ _ -> 0
168 MuTupleRep _ -> 2 {- (1 + GC_MUT_RESERVED_WORDS) -}
172 PhantomRep -> panic "MachMisc.varHdrSizeInWords:phantom"
175 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
177 Static closure sizes:
179 charLikeSize, intLikeSize :: Int
181 charLikeSize = blahLikeSize CharLikeRep
182 intLikeSize = blahLikeSize IntLikeRep
185 = fromInteger (sizeOf PtrRep)
186 * (fixedHdrSizeInWords + varHdrSizeInWords blahLikeRep + 1)
188 blahLikeRep = SpecialisedRep blah 0 1 SMNormalForm
191 mutHS, dataHS :: StixTree
193 mutHS = blah_hs (MuTupleRep 0)
194 dataHS = blah_hs (DataRep 0)
197 = StInt (toInteger words)
199 words = fixedHdrSizeInWords + varHdrSizeInWords blah
202 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
204 Size of a @PrimRep@, in bytes.
207 sizeOf :: PrimRep -> Integer{-in bytes-}
208 -- the result is an Integer only because it's more convenient
210 sizeOf pr = case (primRepToSize pr) of
211 IF_ARCH_alpha({B -> 1; BU -> 1; {-W -> 2; WU -> 2; L -> 4; SF -> 4;-} _ -> 8},)
212 IF_ARCH_sparc({B -> 1; BU -> 1; {-HW -> 2; HWU -> 2;-} W -> 4; {-D -> 8;-} F -> 4; DF -> 8},)
213 IF_ARCH_i386( {B -> 1; {-S -> 2;-} L -> 4; F -> 4; DF -> 8 },)
216 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
218 Now the volatile saves and restores. We add the basic guys to the
219 list of ``user'' registers provided. Note that there are more basic
220 registers on the restore list, because some are reloaded from
223 (@volatileRestores@ used only for wrapper-hungry PrimOps.)
226 volatileSaves, volatileRestores :: [MagicId] -> [StixTree]
228 save_cands = [BaseReg,SpA,SuA,SpB,SuB,Hp,HpLim,RetReg]
229 restore_cands = save_cands ++ [StkStubReg,StdUpdRetVecReg]
232 = map save ((filter callerSaves) (save_cands ++ vols))
234 save x = StAssign (magicIdPrimRep x) loc reg
236 reg = StReg (StixMagicId x)
237 loc = case stgReg x of
239 Always _ -> panic "volatileSaves"
241 volatileRestores vols
242 = map restore ((filter callerSaves) (restore_cands ++ vols))
244 restore x = StAssign (magicIdPrimRep x) reg loc
246 reg = StReg (StixMagicId x)
247 loc = case stgReg x of
249 Always _ -> panic "volatileRestores"
252 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
254 Obviously slightly weedy
255 (Note that the floating point values aren't terribly important.)
258 targetMinDouble = MachDouble (-1.7976931348623157e+308)
259 targetMaxDouble = MachDouble (1.7976931348623157e+308)
260 targetMinInt = mkMachInt (-2147483647)
261 targetMaxInt = mkMachInt 2147483647
264 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
266 Storage manager nonsense. Note that the indices are dependent on
267 the definition of the smInfo structure in SMinterface.lh
270 storageMgrInfo, smCAFlist, smOldMutables, smOldLim :: StixTree
272 storageMgrInfo = sStLitLbl SLIT("StorageMgrInfo")
273 smCAFlist = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_CAFLIST))
274 smOldMutables = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_OLDMUTABLES))
275 smOldLim = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_OLDLIM))
276 smStablePtrTable = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_STABLEPOINTERTABLE))
279 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
281 This algorithm for determining the $\log_2$ of exact powers of 2 comes
282 from GCC. It requires bit manipulation primitives, and we use GHC
290 exactLog2 :: Integer -> Maybe Integer
292 = if (x <= 0 || x >= 2147483648) then
295 case (fromInteger x) of { I# x# ->
296 if (w2i ((i2w x#) `and#` (i2w (0# -# x#))) /=# x#) then
299 Just (toInteger (I# (pow2 x#)))
302 shiftr x y = shiftRA# x y
304 pow2 x# | x# ==# 1# = 0#
305 | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` i2w_s 1#))
308 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
312 #if alpha_TARGET_ARCH
313 = ALWAYS -- For BI (same as BR)
314 | EQQ -- For CMP and BI (NB: "EQ" is a 1.3 Prelude name)
316 | GTT -- For BI only (NB: "GT" is a 1.3 Prelude name)
317 | LE -- For CMP and BI
318 | LTT -- For CMP and BI (NB: "LT" is a 1.3 Prelude name)
320 | NEVER -- For BI (null instruction)
321 | ULE -- For CMP only
322 | ULT -- For CMP only
325 = ALWAYS -- What's really used? ToDo
339 #if sparc_TARGET_ARCH
340 = ALWAYS -- What's really used? ToDo
361 #if alpha_TARGET_ARCH
364 -- | W -- word (2 bytes): UNUSED
366 -- | L -- longword (4 bytes): UNUSED
367 | Q -- quadword (8 bytes)
368 -- | FF -- VAX F-style floating pt: UNUSED
369 -- | GF -- VAX G-style floating pt: UNUSED
370 -- | DF -- VAX D-style floating pt: UNUSED
371 -- | SF -- IEEE single-precision floating pt: UNUSED
372 | TF -- IEEE double-precision floating pt
376 -- | HB -- higher byte **UNUSED**
379 | F -- IEEE single-precision floating pt
380 | DF -- IEEE single-precision floating pt
382 #if sparc_TARGET_ARCH
384 | BU -- byte (unsigned)
385 -- | HW -- halfword, 2 bytes (signed): UNUSED
386 -- | HWU -- halfword, 2 bytes (unsigned): UNUSED
388 -- | D -- doubleword, 8 bytes: UNUSED
389 | F -- IEEE single-precision floating pt
390 | DF -- IEEE single-precision floating pt
393 primRepToSize :: PrimRep -> Size
395 primRepToSize PtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
396 primRepToSize CodePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
397 primRepToSize DataPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
398 primRepToSize RetRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
399 primRepToSize CostCentreRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
400 primRepToSize CharRep = IF_ARCH_alpha( BU, IF_ARCH_i386( L, IF_ARCH_sparc( BU,)))
401 primRepToSize IntRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
402 primRepToSize WordRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
403 primRepToSize AddrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
404 primRepToSize FloatRep = IF_ARCH_alpha( TF, IF_ARCH_i386( F, IF_ARCH_sparc( F ,)))
405 primRepToSize DoubleRep = IF_ARCH_alpha( TF, IF_ARCH_i386( DF,IF_ARCH_sparc( DF,)))
406 primRepToSize ArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
407 primRepToSize ByteArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
408 primRepToSize StablePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
409 primRepToSize ForeignObjRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
412 %************************************************************************
414 \subsection{Machine's assembly language}
416 %************************************************************************
418 We have a few common ``instructions'' (nearly all the pseudo-ops) but
419 mostly all of @Instr@ is machine-specific.
423 = COMMENT FAST_STRING -- comment pseudo-op
424 | SEGMENT CodeSegment -- {data,text} segment pseudo-op
425 | LABEL CLabel -- global label pseudo-op
426 | ASCII Bool -- True <=> needs backslash conversion
427 String -- the literal string
433 #if alpha_TARGET_ARCH
435 -- data Instr continues...
439 | LD Size Reg Addr -- size, dst, src
440 | LDA Reg Addr -- dst, src
441 | LDAH Reg Addr -- dst, src
442 | LDGP Reg Addr -- dst, src
443 | LDI Size Reg Imm -- size, dst, src
444 | ST Size Reg Addr -- size, src, dst
449 | ABS Size RI Reg -- size, src, dst
450 | NEG Size Bool RI Reg -- size, overflow, src, dst
451 | ADD Size Bool Reg RI Reg -- size, overflow, src, src, dst
452 | SADD Size Size Reg RI Reg -- size, scale, src, src, dst
453 | SUB Size Bool Reg RI Reg -- size, overflow, src, src, dst
454 | SSUB Size Size Reg RI Reg -- size, scale, src, src, dst
455 | MUL Size Bool Reg RI Reg -- size, overflow, src, src, dst
456 | DIV Size Bool Reg RI Reg -- size, unsigned, src, src, dst
457 | REM Size Bool Reg RI Reg -- size, unsigned, src, src, dst
459 -- Simple bit-twiddling.
479 | CMP Cond Reg RI Reg
486 | FADD Size Reg Reg Reg
487 | FDIV Size Reg Reg Reg
488 | FMUL Size Reg Reg Reg
489 | FSUB Size Reg Reg Reg
490 | CVTxy Size Size Reg Reg
491 | FCMP Size Cond Reg Reg Reg
503 -- Alpha-specific pseudo-ops.
512 #endif {- alpha_TARGET_ARCH -}
518 -- data Instr continues...
522 | MOV Size Operand Operand
523 | MOVZX Size Operand Operand -- size is the size of operand 2
524 | MOVSX Size Operand Operand -- size is the size of operand 2
526 -- Load effective address (also a very useful three-operand add instruction :-)
528 | LEA Size Operand Operand
532 | ADD Size Operand Operand
533 | SUB Size Operand Operand
535 -- Multiplication (signed and unsigned), Division (signed and unsigned),
536 -- result in %eax, %edx.
538 | IMUL Size Operand Operand
541 -- Simple bit-twiddling.
543 | AND Size Operand Operand
544 | OR Size Operand Operand
545 | XOR Size Operand Operand
547 | NEGI Size Operand -- NEG instruction (name clash with Cond)
548 | SHL Size Operand Operand -- 1st operand must be an Imm
549 | SAR Size Operand Operand -- 1st operand must be an Imm
550 | SHR Size Operand Operand -- 1st operand must be an Imm
553 -- Float Arithmetic. -- ToDo for 386
555 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
556 -- right up until we spit them out.
558 | SAHF -- stores ah into flags
560 | FADD Size Operand -- src
562 | FIADD Size Addr -- src
564 | FCOM Size Operand -- src
566 | FDIV Size Operand -- src
568 | FIDIV Size Addr -- src
569 | FDIVR Size Operand -- src
571 | FIDIVR Size Addr -- src
572 | FICOM Size Addr -- src
573 | FILD Size Addr Reg -- src, dst
574 | FIST Size Addr -- dst
575 | FLD Size Operand -- src
578 | FMUL Size Operand -- src
580 | FIMUL Size Addr -- src
584 | FST Size Operand -- dst
585 | FSTP Size Operand -- dst
586 | FSUB Size Operand -- src
588 | FISUB Size Addr -- src
589 | FSUBR Size Operand -- src
591 | FISUBR Size Addr -- src
593 | FCOMP Size Operand -- src
601 | TEST Size Operand Operand
602 | CMP Size Operand Operand
612 | JMP Operand -- target
613 | JXX Cond CLabel -- target
618 | CLTD -- sign extend %eax into %edx:%eax
621 = OpReg Reg -- register
622 | OpImm Imm -- immediate value
623 | OpAddr Addr -- memory reference
625 #endif {- i386_TARGET_ARCH -}
629 #if sparc_TARGET_ARCH
631 -- data Instr continues...
635 | LD Size Addr Reg -- size, src, dst
636 | ST Size Reg Addr -- size, src, dst
640 | ADD Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
641 | SUB Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
643 -- Simple bit-twiddling.
645 | AND Bool Reg RI Reg -- cc?, src1, src2, dst
646 | ANDN Bool Reg RI Reg -- cc?, src1, src2, dst
647 | OR Bool Reg RI Reg -- cc?, src1, src2, dst
648 | ORN Bool Reg RI Reg -- cc?, src1, src2, dst
649 | XOR Bool Reg RI Reg -- cc?, src1, src2, dst
650 | XNOR Bool Reg RI Reg -- cc?, src1, src2, dst
651 | SLL Reg RI Reg -- src1, src2, dst
652 | SRL Reg RI Reg -- src1, src2, dst
653 | SRA Reg RI Reg -- src1, src2, dst
654 | SETHI Imm Reg -- src, dst
655 | NOP -- Really SETHI 0, %g0, but worth an alias
659 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
660 -- right up until we spit them out.
662 | FABS Size Reg Reg -- src dst
663 | FADD Size Reg Reg Reg -- src1, src2, dst
664 | FCMP Bool Size Reg Reg -- exception?, src1, src2, dst
665 | FDIV Size Reg Reg Reg -- src1, src2, dst
666 | FMOV Size Reg Reg -- src, dst
667 | FMUL Size Reg Reg Reg -- src1, src2, dst
668 | FNEG Size Reg Reg -- src, dst
669 | FSQRT Size Reg Reg -- src, dst
670 | FSUB Size Reg Reg Reg -- src1, src2, dst
671 | FxTOy Size Size Reg Reg -- src, dst
675 | BI Cond Bool Imm -- cond, annul?, target
676 | BF Cond Bool Imm -- cond, annul?, target
679 | CALL Imm Int Bool -- target, args, terminal
686 riZero (RIImm (ImmInt 0)) = True
687 riZero (RIImm (ImmInteger 0)) = True
688 riZero (RIReg (FixedReg ILIT(0))) = True
691 #endif {- sparc_TARGET_ARCH -}