2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
46 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
49 , eax, ebx, ecx, edx, esi, esp
50 , st0, st1, st2, st3, st4, st5, st6, st7
55 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
61 #include "HsVersions.h"
63 import AbsCSyn ( MagicId(..) )
64 import AbsCUtils ( magicIdPrimRep )
65 import CLabel ( CLabel )
66 import PrimOp ( PrimOp(..) )
67 import PrimRep ( PrimRep(..) )
68 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
71 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
74 import UniqSupply ( getUnique, returnUs, thenUs, UniqSM )
78 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
83 | ImmInteger Integer -- Sigh.
84 | ImmCLbl CLabel -- AbstractC Label (with baggage)
85 | ImmLab SDoc -- Simple string label (underscore-able)
86 | ImmLit SDoc -- Simple string
88 | LO Imm -- Possible restrictions...
91 strImmLit s = ImmLit (text s)
94 IF_ARCH_alpha({-prepend nothing-}
95 ,IF_ARCH_i386( '0' : 'd' :
96 ,IF_ARCH_sparc('0' : 'r' :,)))
100 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
104 #if alpha_TARGET_ARCH
111 = AddrBaseIndex Base Index Displacement
114 type Base = Maybe Reg
115 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
116 type Displacement = Imm
119 #if sparc_TARGET_ARCH
124 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
128 #if alpha_TARGET_ARCH
129 _ -> panic "MachMisc.addrOffset not defined for Alpha"
132 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
133 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
134 AddrBaseIndex r i (ImmInteger n)
135 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
138 #if sparc_TARGET_ARCH
139 AddrRegImm r (ImmInt n)
140 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
141 | otherwise -> Nothing
144 AddrRegImm r (ImmInteger n)
145 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
146 | otherwise -> Nothing
147 where n2 = n + toInteger off
149 AddrRegReg r (FixedReg ILIT(0))
150 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
151 | otherwise -> Nothing
158 #if alpha_TARGET_ARCH
160 fits8Bits :: Integer -> Bool
161 fits8Bits i = i >= -256 && i < 256
165 #if sparc_TARGET_ARCH
167 fits13Bits :: Int -> Bool
170 fits13Bits :: Integer -> Bool
173 fits13Bits :: Integral a => a -> Bool
174 fits13Bits x = x >= -4096 && x < 4096
178 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
183 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
185 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
186 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
187 The rest are either in real machine registers or stored as offsets
191 data RegLoc = Save StixTree | Always StixTree
194 Trees for register save locations:
196 saveLoc :: MagicId -> StixTree
198 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
202 stgReg :: MagicId -> RegLoc
205 = case (magicIdRegMaybe x) of
206 Just _ -> Save nonReg
207 Nothing -> Always nonReg
209 offset = baseRegOffset x
211 baseLoc = case (magicIdRegMaybe BaseReg) of
212 Just _ -> StReg (StixMagicId BaseReg)
213 Nothing -> sStLitLbl SLIT("MainRegTable")
216 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
217 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
218 BaseReg -> sStLitLbl SLIT("MainRegTable")
219 -- these Hp&HpLim cases perhaps should
220 -- not be here for i386 (???) WDP 96/03
221 #ifndef i386_TARGET_ARCH
222 -- Yup, Hp&HpLim are not mapped into registers for x86's at the mo, so
223 -- fetching Hp off BaseReg is the sensible option, since that's
224 -- where gcc generated code stuffs/expects it (RTBL_Hp & RTBL_HpLim).
226 -- In fact, why use StorageMgrInfo at all?
227 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
228 HpLim -> StInd PtrRep (sStLitLbl
229 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
231 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
232 StInt (1*BYTES_PER_WORD)])
234 r2 = VanillaReg PtrRep ILIT(2)
235 infoptr = case (stgReg r2) of
237 Save _ -> StReg (StixMagicId r2)
238 _ -> StInd (magicIdPrimRep x)
239 (StPrim IntAddOp [baseLoc,
240 StInt (toInteger (offset*BYTES_PER_WORD))])
243 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
245 @spRel@ gives us a stack relative addressing mode for volatile
246 temporaries and for excess call arguments. @fpRel@, where
247 applicable, is the same but for the frame pointer.
250 spRel :: Int -- desired stack offset in words, positive or negative
255 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
257 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
260 #if sparc_TARGET_ARCH
261 fpRel :: Int -> MachRegsAddr
262 -- Duznae work for offsets greater than 13 bits; we just hope for
265 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
269 %************************************************************************
271 \subsection[Reg]{Real registers}
273 %************************************************************************
275 Static Registers correspond to actual machine registers. These should
276 be avoided until the last possible moment.
278 Dynamic registers are allocated on the fly, usually to represent a single
279 value in the abstract assembly code (i.e. dynamic registers are usually
280 single assignment). Ultimately, they are mapped to available machine
281 registers before spitting out the code.
285 = FixedReg FAST_INT -- A pre-allocated machine register
287 | MappedReg FAST_INT -- A dynamically allocated machine register
289 | MemoryReg Int PrimRep -- A machine "register" actually held in
290 -- a memory allocated table of
291 -- registers which didn't fit in real
294 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
295 -- always mapped to one of the earlier
296 -- two (?) before we're done.
297 mkReg :: Unique -> PrimRep -> Reg
300 getNewRegNCG :: PrimRep -> UniqSM Reg
302 = getUnique `thenUs` \ u ->
303 returnUs (UnmappedReg u pk)
305 instance Text Reg where
306 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
307 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
308 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
309 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
312 instance Outputable Reg where
313 ppr r = text (show r)
316 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
317 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
318 cmpReg (MemoryReg i _) (MemoryReg i' _) = i `compare` i'
319 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = compare u u'
321 = let tag1 = tagReg r1
324 if tag1 _LT_ tag2 then LT else GT
326 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
327 tagReg (MappedReg _) = ILIT(2)
328 tagReg (MemoryReg _ _) = ILIT(3)
329 tagReg (UnmappedReg _ _) = ILIT(4)
331 cmp_ihash :: FAST_INT -> FAST_INT -> Ordering
332 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ else if a1 _LT_ a2 then LT else GT
334 instance Eq Reg where
335 a == b = case (a `compare` b) of { EQ -> True; _ -> False }
336 a /= b = case (a `compare` b) of { EQ -> False; _ -> True }
338 instance Ord Reg where
339 a <= b = case (a `compare` b) of { LT -> True; EQ -> True; GT -> False }
340 a < b = case (a `compare` b) of { LT -> True; EQ -> False; GT -> False }
341 a >= b = case (a `compare` b) of { LT -> False; EQ -> True; GT -> True }
342 a > b = case (a `compare` b) of { LT -> False; EQ -> False; GT -> True }
343 compare a b = cmpReg a b
345 instance Uniquable Reg where
346 uniqueOf (UnmappedReg u _) = u
347 uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i)
348 uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i)
349 uniqueOf (MemoryReg i _) = mkPseudoUnique3 i
355 realReg :: RegNo -> Reg
357 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
359 extractMappedRegNos :: [Reg] -> [RegNo]
361 extractMappedRegNos regs
364 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
365 ex _ acc = acc -- leave it out
368 ** Machine-specific Reg stuff: **
370 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
371 point registers. The mapping of STG registers to alpha machine registers
372 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
374 #if alpha_TARGET_ARCH
378 v0, f0, ra, pv, gp, sp, zeroh :: Reg
380 f0 = realReg (fReg 0)
381 ra = FixedReg ILIT(26)
383 gp = FixedReg ILIT(29)
384 sp = FixedReg ILIT(30)
385 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
387 t9, t10, t11, t12 :: Reg
395 Intel x86 architecture:
396 - All registers except 7 (esp) are available for use.
397 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
398 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
399 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
400 - Registers 8-15 hold extended floating point values.
404 gReg,fReg :: Int -> Int
408 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
409 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
410 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
411 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
412 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
413 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
414 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
415 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
416 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
417 st0 = realReg (fReg 0)
418 st1 = realReg (fReg 1)
419 st2 = realReg (fReg 2)
420 st3 = realReg (fReg 3)
421 st4 = realReg (fReg 4)
422 st5 = realReg (fReg 5)
423 st6 = realReg (fReg 6)
424 st7 = realReg (fReg 7)
429 The SPARC has 64 registers of interest; 32 integer registers and 32
430 floating point registers. The mapping of STG registers to SPARC
431 machine registers is defined in StgRegs.h. We are, of course,
432 prepared for any eventuality.
435 #if sparc_TARGET_ARCH
437 gReg,lReg,iReg,oReg,fReg :: Int -> Int
445 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
446 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
448 g0, fp, sp, o0, f0 :: Reg
449 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
450 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
451 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
452 o0 = realReg (oReg 0)
453 f0 = realReg (fReg 0)
458 Redefine the literals used for machine-registers with non-numeric
459 names in the header files. Gag me with a spoon, eh?
461 #if alpha_TARGET_ARCH
513 #if sparc_TARGET_ARCH
582 baseRegOffset :: MagicId -> Int
584 baseRegOffset StkOReg = OFFSET_StkO
585 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
586 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
587 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
588 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
589 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
590 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
591 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
592 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
593 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
594 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
595 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
596 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
597 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
598 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
599 baseRegOffset TagReg = OFFSET_Tag
600 baseRegOffset RetReg = OFFSET_Ret
601 baseRegOffset SpA = OFFSET_SpA
602 baseRegOffset SuA = OFFSET_SuA
603 baseRegOffset SpB = OFFSET_SpB
604 baseRegOffset SuB = OFFSET_SuB
605 baseRegOffset Hp = OFFSET_Hp
606 baseRegOffset HpLim = OFFSET_HpLim
607 baseRegOffset LivenessReg = OFFSET_Liveness
609 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
610 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
611 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
612 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
613 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
618 callerSaves :: MagicId -> Bool
620 #ifdef CALLER_SAVES_Base
621 callerSaves BaseReg = True
623 #ifdef CALLER_SAVES_StkO
624 callerSaves StkOReg = True
626 #ifdef CALLER_SAVES_R1
627 callerSaves (VanillaReg _ ILIT(1)) = True
629 #ifdef CALLER_SAVES_R2
630 callerSaves (VanillaReg _ ILIT(2)) = True
632 #ifdef CALLER_SAVES_R3
633 callerSaves (VanillaReg _ ILIT(3)) = True
635 #ifdef CALLER_SAVES_R4
636 callerSaves (VanillaReg _ ILIT(4)) = True
638 #ifdef CALLER_SAVES_R5
639 callerSaves (VanillaReg _ ILIT(5)) = True
641 #ifdef CALLER_SAVES_R6
642 callerSaves (VanillaReg _ ILIT(6)) = True
644 #ifdef CALLER_SAVES_R7
645 callerSaves (VanillaReg _ ILIT(7)) = True
647 #ifdef CALLER_SAVES_R8
648 callerSaves (VanillaReg _ ILIT(8)) = True
650 #ifdef CALLER_SAVES_FltReg1
651 callerSaves (FloatReg ILIT(1)) = True
653 #ifdef CALLER_SAVES_FltReg2
654 callerSaves (FloatReg ILIT(2)) = True
656 #ifdef CALLER_SAVES_FltReg3
657 callerSaves (FloatReg ILIT(3)) = True
659 #ifdef CALLER_SAVES_FltReg4
660 callerSaves (FloatReg ILIT(4)) = True
662 #ifdef CALLER_SAVES_DblReg1
663 callerSaves (DoubleReg ILIT(1)) = True
665 #ifdef CALLER_SAVES_DblReg2
666 callerSaves (DoubleReg ILIT(2)) = True
668 #ifdef CALLER_SAVES_Tag
669 callerSaves TagReg = True
671 #ifdef CALLER_SAVES_Ret
672 callerSaves RetReg = True
674 #ifdef CALLER_SAVES_SpA
675 callerSaves SpA = True
677 #ifdef CALLER_SAVES_SuA
678 callerSaves SuA = True
680 #ifdef CALLER_SAVES_SpB
681 callerSaves SpB = True
683 #ifdef CALLER_SAVES_SuB
684 callerSaves SuB = True
686 #ifdef CALLER_SAVES_Hp
687 callerSaves Hp = True
689 #ifdef CALLER_SAVES_HpLim
690 callerSaves HpLim = True
692 #ifdef CALLER_SAVES_Liveness
693 callerSaves LivenessReg = True
695 #ifdef CALLER_SAVES_StdUpdRetVec
696 callerSaves StdUpdRetVecReg = True
698 #ifdef CALLER_SAVES_StkStub
699 callerSaves StkStubReg = True
701 callerSaves _ = False
705 magicIdRegMaybe :: MagicId -> Maybe Reg
708 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
711 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
714 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
717 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
720 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
723 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
726 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
729 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
732 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
735 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
738 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
741 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
744 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
747 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
750 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
753 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
756 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
759 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
762 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
765 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
768 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
771 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
774 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
777 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
780 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
782 #ifdef REG_StdUpdRetVec
783 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
786 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
788 magicIdRegMaybe _ = Nothing
791 %************************************************************************
793 \subsection{Free, reserved, call-clobbered, and argument registers}
795 %************************************************************************
797 @freeRegs@ is the list of registers we can use in register allocation.
798 @freeReg@ (below) says if a particular register is free.
800 With a per-instruction clobber list, we might be able to get some of
801 these back, but it's probably not worth the hassle.
803 @callClobberedRegs@ ... the obvious.
805 @argRegs@: assuming a call with N arguments, what registers will be
806 used to hold arguments? (NB: it doesn't know whether the arguments
807 are integer or floating-point...)
810 reservedRegs :: [RegNo]
812 #if alpha_TARGET_ARCH
813 = [NCG_Reserved_I1, NCG_Reserved_I2,
814 NCG_Reserved_F1, NCG_Reserved_F2]
817 = [{-certainly cannot afford any!-}]
819 #if sparc_TARGET_ARCH
820 = [NCG_Reserved_I1, NCG_Reserved_I2,
821 NCG_Reserved_F1, NCG_Reserved_F2,
822 NCG_Reserved_D1, NCG_Reserved_D2]
825 -------------------------------
828 = freeMappedRegs IF_ARCH_alpha( [0..63],
829 IF_ARCH_i386( [0..15],
830 IF_ARCH_sparc( [0..63],)))
832 -------------------------------
833 callClobberedRegs :: [Reg]
836 #if alpha_TARGET_ARCH
837 [0, 1, 2, 3, 4, 5, 6, 7, 8,
838 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
839 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
840 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
841 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
842 #endif {- alpha_TARGET_ARCH -}
845 #endif {- i386_TARGET_ARCH -}
846 #if sparc_TARGET_ARCH
848 [oReg i | i <- [0..5]] ++
849 [gReg i | i <- [1..7]] ++
850 [fReg i | i <- [0..31]] )
851 #endif {- sparc_TARGET_ARCH -}
853 -------------------------------
854 argRegs :: Int -> [Reg]
857 #if alpha_TARGET_ARCH
858 argRegs 1 = freeMappedRegs [16, fReg 16]
859 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
860 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
861 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
862 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
863 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
864 #endif {- alpha_TARGET_ARCH -}
866 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
867 #endif {- i386_TARGET_ARCH -}
868 #if sparc_TARGET_ARCH
869 argRegs 1 = freeMappedRegs (map oReg [0])
870 argRegs 2 = freeMappedRegs (map oReg [0,1])
871 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
872 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
873 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
874 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
875 #endif {- sparc_TARGET_ARCH -}
876 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
878 -------------------------------
880 #if alpha_TARGET_ARCH
881 allArgRegs :: [(Reg, Reg)]
883 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
884 #endif {- alpha_TARGET_ARCH -}
886 #if sparc_TARGET_ARCH
889 allArgRegs = map realReg [oReg i | i <- [0..5]]
890 #endif {- sparc_TARGET_ARCH -}
892 -------------------------------
893 freeMappedRegs :: [Int] -> [Reg]
899 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
903 freeReg :: FAST_INT -> FAST_BOOL
905 #if alpha_TARGET_ARCH
906 freeReg ILIT(26) = _FALSE_ -- return address (ra)
907 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
908 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
909 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
910 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
911 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
915 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
918 #if sparc_TARGET_ARCH
919 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
920 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
921 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
922 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
923 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
924 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
928 freeReg ILIT(REG_Base) = _FALSE_
931 freeReg ILIT(REG_StkO) = _FALSE_
934 freeReg ILIT(REG_R1) = _FALSE_
937 freeReg ILIT(REG_R2) = _FALSE_
940 freeReg ILIT(REG_R3) = _FALSE_
943 freeReg ILIT(REG_R4) = _FALSE_
946 freeReg ILIT(REG_R5) = _FALSE_
949 freeReg ILIT(REG_R6) = _FALSE_
952 freeReg ILIT(REG_R7) = _FALSE_
955 freeReg ILIT(REG_R8) = _FALSE_
958 freeReg ILIT(REG_Flt1) = _FALSE_
961 freeReg ILIT(REG_Flt2) = _FALSE_
964 freeReg ILIT(REG_Flt3) = _FALSE_
967 freeReg ILIT(REG_Flt4) = _FALSE_
970 freeReg ILIT(REG_Dbl1) = _FALSE_
973 freeReg ILIT(REG_Dbl2) = _FALSE_
976 freeReg ILIT(REG_Tag) = _FALSE_
979 freeReg ILIT(REG_Ret) = _FALSE_
982 freeReg ILIT(REG_SpA) = _FALSE_
985 freeReg ILIT(REG_SuA) = _FALSE_
988 freeReg ILIT(REG_SpB) = _FALSE_
991 freeReg ILIT(REG_SuB) = _FALSE_
994 freeReg ILIT(REG_Hp) = _FALSE_
997 freeReg ILIT(REG_HpLim) = _FALSE_
1000 freeReg ILIT(REG_Liveness) = _FALSE_
1002 #ifdef REG_StdUpdRetVec
1003 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1006 freeReg ILIT(REG_StkStub) = _FALSE_
1010 -- we hang onto two double regs for dedicated
1011 -- use; this is not necessary on Alphas and
1012 -- may not be on other non-SPARCs.
1014 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1017 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1019 | otherwise = _TRUE_