2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "HsVersions.h"
14 #include "nativeGen/NCG.h"
47 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zero
50 , eax, ebx, ecx, edx, esi, esp
51 , st0, st1, st2, st3, st4, st5, st6, st7
56 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
64 import AbsCSyn ( MagicId(..) )
65 import AbsCUtils ( magicIdPrimRep )
66 import Pretty ( ppStr, ppRational, ppShow )
67 import PrimOp ( PrimOp(..) )
68 import PrimRep ( PrimRep(..) )
69 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
72 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
73 Unique{-instance Ord3-}
75 import UniqSupply ( getUnique, returnUs, thenUs, UniqSM(..) )
76 import Unpretty ( uppStr, Unpretty(..) )
80 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
85 | ImmInteger Integer -- Sigh.
86 | ImmCLbl CLabel -- AbstractC Label (with baggage)
87 | ImmLab Unpretty -- Simple string label (underscore-able)
88 | ImmLit Unpretty -- Simple string
90 | LO Imm -- Possible restrictions...
94 strImmLit s = ImmLit (uppStr s)
97 IF_ARCH_alpha({-prepend nothing-}
98 ,IF_ARCH_i386( '0' : 'd' :
99 ,IF_ARCH_sparc('0' : 'r' :,)))
100 ppShow 80 (ppRational r))
103 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
107 #if alpha_TARGET_ARCH
114 = Addr Base Index Displacement
117 type Base = Maybe Reg
118 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
119 type Displacement = Imm
122 #if sparc_TARGET_ARCH
127 addrOffset :: Addr -> Int -> Maybe Addr
131 #if alpha_TARGET_ARCH
132 _ -> panic "MachMisc.addrOffset not defined for Alpha"
135 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
136 Addr r i (ImmInt n) -> Just (Addr r i (ImmInt (n + off)))
137 Addr r i (ImmInteger n)
138 -> Just (Addr r i (ImmInt (fromInteger (n + toInteger off))))
141 #if sparc_TARGET_ARCH
142 AddrRegImm r (ImmInt n)
143 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
144 | otherwise -> Nothing
147 AddrRegImm r (ImmInteger n)
148 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
149 | otherwise -> Nothing
150 where n2 = n + toInteger off
152 AddrRegReg r (FixedReg ILIT(0))
153 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
154 | otherwise -> Nothing
161 #if alpha_TARGET_ARCH
163 fits8Bits :: Integer -> Bool
164 fits8Bits i = i >= -256 && i < 256
168 #if sparc_TARGET_ARCH
170 fits13Bits :: Int -> Bool
173 fits13Bits :: Integer -> Bool
176 fits13Bits :: Integral a => a -> Bool
177 fits13Bits x = x >= -4096 && x < 4096
181 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
186 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
188 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
189 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
190 The rest are either in real machine registers or stored as offsets
194 data RegLoc = Save StixTree | Always StixTree
197 Trees for register save locations:
199 saveLoc :: MagicId -> StixTree
201 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
205 stgReg :: MagicId -> RegLoc
208 = case (magicIdRegMaybe x) of
209 Just _ -> Save nonReg
210 Nothing -> Always nonReg
212 offset = baseRegOffset x
214 baseLoc = case (magicIdRegMaybe BaseReg) of
215 Just _ -> StReg (StixMagicId BaseReg)
216 Nothing -> sStLitLbl SLIT("MainRegTable")
219 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
220 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
221 BaseReg -> sStLitLbl SLIT("MainRegTable")
222 -- these Hp&HpLim cases perhaps should
223 -- not be here for i386 (???) WDP 96/03
224 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
225 HpLim -> StInd PtrRep (sStLitLbl
226 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
227 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
228 StInt (1*BYTES_PER_WORD)])
230 r2 = VanillaReg PtrRep ILIT(2)
231 infoptr = case (stgReg r2) of
233 Save _ -> StReg (StixMagicId r2)
234 _ -> StInd (magicIdPrimRep x)
235 (StPrim IntAddOp [baseLoc,
236 StInt (toInteger (offset*BYTES_PER_WORD))])
239 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
241 @spRel@ gives us a stack relative addressing mode for volatile
242 temporaries and for excess call arguments. @fpRel@, where
243 applicable, is the same but for the frame pointer.
246 spRel :: Int -- desired stack offset in words, positive or negative
251 = Addr (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
253 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
256 #if sparc_TARGET_ARCH
258 -- Duznae work for offsets greater than 13 bits; we just hope for
261 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
265 %************************************************************************
267 \subsection[Reg]{Real registers}
269 %************************************************************************
271 Static Registers correspond to actual machine registers. These should
272 be avoided until the last possible moment.
274 Dynamic registers are allocated on the fly, usually to represent a single
275 value in the abstract assembly code (i.e. dynamic registers are usually
276 single assignment). Ultimately, they are mapped to available machine
277 registers before spitting out the code.
281 = FixedReg FAST_INT -- A pre-allocated machine register
283 | MappedReg FAST_INT -- A dynamically allocated machine register
285 | MemoryReg Int PrimRep -- A machine "register" actually held in
286 -- a memory allocated table of
287 -- registers which didn't fit in real
290 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
291 -- always mapped to one of the earlier
292 -- two (?) before we're done.
294 mkReg :: Unique -> PrimRep -> Reg
297 getNewRegNCG :: PrimRep -> UniqSM Reg
299 = getUnique `thenUs` \ u ->
300 returnUs (UnmappedReg u pk)
302 instance Text Reg where
303 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
304 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
305 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
306 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
309 instance Outputable Reg where
310 ppr sty r = ppStr (show r)
313 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
314 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
315 cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i'
316 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u'
318 = let tag1 = tagReg r1
321 if tag1 _LT_ tag2 then LT_ else GT_
323 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
324 tagReg (MappedReg _) = ILIT(2)
325 tagReg (MemoryReg _ _) = ILIT(3)
326 tagReg (UnmappedReg _ _) = ILIT(4)
328 cmp_i :: Int -> Int -> TAG_
329 cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_
331 cmp_ihash :: FAST_INT -> FAST_INT -> TAG_
332 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_
334 instance Ord3 Reg where
337 instance Eq Reg where
338 a == b = case (a `cmp` b) of { EQ_ -> True; _ -> False }
339 a /= b = case (a `cmp` b) of { EQ_ -> False; _ -> True }
341 instance Ord Reg where
342 a <= b = case (a `cmp` b) of { LT_ -> True; EQ_ -> True; GT__ -> False }
343 a < b = case (a `cmp` b) of { LT_ -> True; EQ_ -> False; GT__ -> False }
344 a >= b = case (a `cmp` b) of { LT_ -> False; EQ_ -> True; GT__ -> True }
345 a > b = case (a `cmp` b) of { LT_ -> False; EQ_ -> False; GT__ -> True }
346 _tagCmp a b = case (a `cmp` b) of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT }
348 instance Uniquable Reg where
349 uniqueOf (UnmappedReg u _) = u
350 uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i)
351 uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i)
352 uniqueOf (MemoryReg i _) = mkPseudoUnique3 i
358 realReg :: RegNo -> Reg
360 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
362 extractMappedRegNos :: [Reg] -> [RegNo]
364 extractMappedRegNos regs
367 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
368 ex _ acc = acc -- leave it out
371 ** Machine-specific Reg stuff: **
373 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
374 point registers. The mapping of STG registers to alpha machine registers
375 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
377 #if alpha_TARGET_ARCH
381 v0, f0, ra, pv, gp, sp, zero :: Reg
383 f0 = realReg (fReg 0)
384 ra = FixedReg ILIT(26)
386 gp = FixedReg ILIT(29)
387 sp = FixedReg ILIT(30)
388 zero = FixedReg ILIT(31)
390 t9, t10, t11, t12 :: Reg
398 Intel x86 architecture:
399 - All registers except 7 (esp) are available for use.
400 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
401 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
402 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
403 - Registers 8-15 hold extended floating point values.
407 gReg,fReg :: Int -> Int
411 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
412 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
413 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
414 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
415 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
416 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
417 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
418 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
419 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
420 st0 = realReg (fReg 0)
421 st1 = realReg (fReg 1)
422 st2 = realReg (fReg 2)
423 st3 = realReg (fReg 3)
424 st4 = realReg (fReg 4)
425 st5 = realReg (fReg 5)
426 st6 = realReg (fReg 6)
427 st7 = realReg (fReg 7)
432 The SPARC has 64 registers of interest; 32 integer registers and 32
433 floating point registers. The mapping of STG registers to SPARC
434 machine registers is defined in StgRegs.h. We are, of course,
435 prepared for any eventuality.
438 #if sparc_TARGET_ARCH
440 gReg,lReg,iReg,oReg,fReg :: Int -> Int
448 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
449 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
451 g0, fp, sp, o0, f0 :: Reg
452 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
453 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
454 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
455 o0 = realReg (oReg 0)
456 f0 = realReg (fReg 0)
461 Redefine the literals used for machine-registers with non-numeric
462 names in the header files. Gag me with a spoon, eh?
464 #if alpha_TARGET_ARCH
516 #if sparc_TARGET_ARCH
585 baseRegOffset :: MagicId -> Int
587 baseRegOffset StkOReg = OFFSET_StkO
588 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
589 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
590 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
591 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
592 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
593 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
594 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
595 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
596 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
597 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
598 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
599 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
600 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
601 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
602 baseRegOffset TagReg = OFFSET_Tag
603 baseRegOffset RetReg = OFFSET_Ret
604 baseRegOffset SpA = OFFSET_SpA
605 baseRegOffset SuA = OFFSET_SuA
606 baseRegOffset SpB = OFFSET_SpB
607 baseRegOffset SuB = OFFSET_SuB
608 baseRegOffset Hp = OFFSET_Hp
609 baseRegOffset HpLim = OFFSET_HpLim
610 baseRegOffset LivenessReg = OFFSET_Liveness
612 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
613 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
614 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
615 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
616 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
621 callerSaves :: MagicId -> Bool
623 #ifdef CALLER_SAVES_Base
624 callerSaves BaseReg = True
626 #ifdef CALLER_SAVES_StkO
627 callerSaves StkOReg = True
629 #ifdef CALLER_SAVES_R1
630 callerSaves (VanillaReg _ ILIT(1)) = True
632 #ifdef CALLER_SAVES_R2
633 callerSaves (VanillaReg _ ILIT(2)) = True
635 #ifdef CALLER_SAVES_R3
636 callerSaves (VanillaReg _ ILIT(3)) = True
638 #ifdef CALLER_SAVES_R4
639 callerSaves (VanillaReg _ ILIT(4)) = True
641 #ifdef CALLER_SAVES_R5
642 callerSaves (VanillaReg _ ILIT(5)) = True
644 #ifdef CALLER_SAVES_R6
645 callerSaves (VanillaReg _ ILIT(6)) = True
647 #ifdef CALLER_SAVES_R7
648 callerSaves (VanillaReg _ ILIT(7)) = True
650 #ifdef CALLER_SAVES_R8
651 callerSaves (VanillaReg _ ILIT(8)) = True
653 #ifdef CALLER_SAVES_FltReg1
654 callerSaves (FloatReg ILIT(1)) = True
656 #ifdef CALLER_SAVES_FltReg2
657 callerSaves (FloatReg ILIT(2)) = True
659 #ifdef CALLER_SAVES_FltReg3
660 callerSaves (FloatReg ILIT(3)) = True
662 #ifdef CALLER_SAVES_FltReg4
663 callerSaves (FloatReg ILIT(4)) = True
665 #ifdef CALLER_SAVES_DblReg1
666 callerSaves (DoubleReg ILIT(1)) = True
668 #ifdef CALLER_SAVES_DblReg2
669 callerSaves (DoubleReg ILIT(2)) = True
671 #ifdef CALLER_SAVES_Tag
672 callerSaves TagReg = True
674 #ifdef CALLER_SAVES_Ret
675 callerSaves RetReg = True
677 #ifdef CALLER_SAVES_SpA
678 callerSaves SpA = True
680 #ifdef CALLER_SAVES_SuA
681 callerSaves SuA = True
683 #ifdef CALLER_SAVES_SpB
684 callerSaves SpB = True
686 #ifdef CALLER_SAVES_SuB
687 callerSaves SuB = True
689 #ifdef CALLER_SAVES_Hp
690 callerSaves Hp = True
692 #ifdef CALLER_SAVES_HpLim
693 callerSaves HpLim = True
695 #ifdef CALLER_SAVES_Liveness
696 callerSaves LivenessReg = True
698 #ifdef CALLER_SAVES_StdUpdRetVec
699 callerSaves StdUpdRetVecReg = True
701 #ifdef CALLER_SAVES_StkStub
702 callerSaves StkStubReg = True
704 callerSaves _ = False
708 magicIdRegMaybe :: MagicId -> Maybe Reg
711 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
714 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
717 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
720 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
723 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
726 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
729 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
732 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
735 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
738 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
741 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
744 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
747 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
750 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
753 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
756 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
759 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
762 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
765 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
768 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
771 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
774 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
777 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
780 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
783 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
785 #ifdef REG_StdUpdRetVec
786 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
789 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
791 magicIdRegMaybe _ = Nothing
794 %************************************************************************
796 \subsection{Free, reserved, call-clobbered, and argument registers}
798 %************************************************************************
800 @freeRegs@ is the list of registers we can use in register allocation.
801 @freeReg@ (below) says if a particular register is free.
803 With a per-instruction clobber list, we might be able to get some of
804 these back, but it's probably not worth the hassle.
806 @callClobberedRegs@ ... the obvious.
808 @argRegs@: assuming a call with N arguments, what registers will be
809 used to hold arguments? (NB: it doesn't know whether the arguments
810 are integer or floating-point...)
813 reservedRegs :: [RegNo]
815 #if alpha_TARGET_ARCH
816 = [NCG_Reserved_I1, NCG_Reserved_I2,
817 NCG_Reserved_F1, NCG_Reserved_F2]
820 = [{-certainly cannot afford any!-}]
822 #if sparc_TARGET_ARCH
823 = [NCG_Reserved_I1, NCG_Reserved_I2,
824 NCG_Reserved_F1, NCG_Reserved_F2,
825 NCG_Reserved_D1, NCG_Reserved_D2]
828 -------------------------------
831 = freeMappedRegs IF_ARCH_alpha( [0..63],
832 IF_ARCH_i386( [0..15],
833 IF_ARCH_sparc( [0..63],)))
835 -------------------------------
836 callClobberedRegs :: [Reg]
839 #if alpha_TARGET_ARCH
840 [0, 1, 2, 3, 4, 5, 6, 7, 8,
841 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
842 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
843 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
844 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
845 #endif {- alpha_TARGET_ARCH -}
848 #endif {- i386_TARGET_ARCH -}
849 #if sparc_TARGET_ARCH
851 [oReg i | i <- [0..5]] ++
852 [gReg i | i <- [1..7]] ++
853 [fReg i | i <- [0..31]] )
854 #endif {- sparc_TARGET_ARCH -}
856 -------------------------------
857 argRegs :: Int -> [Reg]
860 #if alpha_TARGET_ARCH
861 argRegs 1 = freeMappedRegs [16, fReg 16]
862 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
863 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
864 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
865 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
866 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
867 #endif {- alpha_TARGET_ARCH -}
869 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
870 #endif {- i386_TARGET_ARCH -}
871 #if sparc_TARGET_ARCH
872 argRegs 1 = freeMappedRegs (map oReg [0])
873 argRegs 2 = freeMappedRegs (map oReg [0,1])
874 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
875 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
876 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
877 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
878 #endif {- sparc_TARGET_ARCH -}
879 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
881 -------------------------------
883 #if alpha_TARGET_ARCH
884 allArgRegs :: [(Reg, Reg)]
886 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
887 #endif {- alpha_TARGET_ARCH -}
889 #if sparc_TARGET_ARCH
892 allArgRegs = map realReg [oReg i | i <- [0..5]]
893 #endif {- sparc_TARGET_ARCH -}
895 -------------------------------
896 freeMappedRegs :: [Int] -> [Reg]
902 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
906 freeReg :: FAST_INT -> FAST_BOOL
908 #if alpha_TARGET_ARCH
909 freeReg ILIT(26) = _FALSE_ -- return address (ra)
910 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
911 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
912 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
913 freeReg ILIT(31) = _FALSE_ -- always zero (zero)
914 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
918 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
921 #if sparc_TARGET_ARCH
922 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
923 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
924 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
925 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
926 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
927 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
931 freeReg ILIT(REG_Base) = _FALSE_
934 freeReg ILIT(REG_StkO) = _FALSE_
937 freeReg ILIT(REG_R1) = _FALSE_
940 freeReg ILIT(REG_R2) = _FALSE_
943 freeReg ILIT(REG_R3) = _FALSE_
946 freeReg ILIT(REG_R4) = _FALSE_
949 freeReg ILIT(REG_R5) = _FALSE_
952 freeReg ILIT(REG_R6) = _FALSE_
955 freeReg ILIT(REG_R7) = _FALSE_
958 freeReg ILIT(REG_R8) = _FALSE_
961 freeReg ILIT(REG_Flt1) = _FALSE_
964 freeReg ILIT(REG_Flt2) = _FALSE_
967 freeReg ILIT(REG_Flt3) = _FALSE_
970 freeReg ILIT(REG_Flt4) = _FALSE_
973 freeReg ILIT(REG_Dbl1) = _FALSE_
976 freeReg ILIT(REG_Dbl2) = _FALSE_
979 freeReg ILIT(REG_Tag) = _FALSE_
982 freeReg ILIT(REG_Ret) = _FALSE_
985 freeReg ILIT(REG_SpA) = _FALSE_
988 freeReg ILIT(REG_SuA) = _FALSE_
991 freeReg ILIT(REG_SpB) = _FALSE_
994 freeReg ILIT(REG_SuB) = _FALSE_
997 freeReg ILIT(REG_Hp) = _FALSE_
1000 freeReg ILIT(REG_HpLim) = _FALSE_
1003 freeReg ILIT(REG_Liveness) = _FALSE_
1005 #ifdef REG_StdUpdRetVec
1006 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1009 freeReg ILIT(REG_StkStub) = _FALSE_
1013 -- we hang onto two double regs for dedicated
1014 -- use; this is not necessary on Alphas and
1015 -- may not be on other non-SPARCs.
1017 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1020 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1022 | otherwise = _TRUE_