2 % (c) The AQUA Project, Glasgow University, 1996
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "HsVersions.h"
14 #include "nativeGen/NCG.h"
47 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zero
50 , eax, ebx, ecx, edx, esi, esp
51 , st0, st1, st2, st3, st4, st5, st6, st7
56 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
64 import AbsCSyn ( MagicId(..) )
65 import AbsCUtils ( magicIdPrimRep )
66 import Pretty ( ppStr, ppRational, ppShow )
67 import PrimOp ( PrimOp(..) )
68 import PrimRep ( PrimRep(..) )
69 import Stix ( sStLitLbl, StixTree(..), StixReg(..),
72 import Unique ( Unique{-instance Ord3-} )
73 import UniqSupply ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
74 getUnique, returnUs, thenUs, UniqSM(..)
76 import Unpretty ( uppStr, Unpretty(..) )
80 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
85 | ImmInteger Integer -- Sigh.
86 | ImmCLbl CLabel -- AbstractC Label (with baggage)
87 | ImmLab Unpretty -- Simple string label (underscore-able)
88 | ImmLit Unpretty -- Simple string
90 | LO Imm -- Possible restrictions...
94 strImmLit s = ImmLit (uppStr s)
97 IF_ARCH_alpha({-prepend nothing-}
98 ,IF_ARCH_i386( '0' : 'd' :
99 ,IF_ARCH_sparc('0' : 'r' :,)))
100 ppShow 80 (ppRational r))
103 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
107 #if alpha_TARGET_ARCH
114 = Addr Base Index Displacement
117 type Base = Maybe Reg
118 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
119 type Displacement = Imm
122 #if sparc_TARGET_ARCH
127 addrOffset :: Addr -> Int -> Maybe Addr
131 #if alpha_TARGET_ARCH
132 _ -> panic "MachMisc.addrOffset not defined for Alpha"
135 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
136 Addr r i (ImmInt n) -> Just (Addr r i (ImmInt (n + off)))
137 Addr r i (ImmInteger n)
138 -> Just (Addr r i (ImmInt (fromInteger (n + toInteger off))))
141 #if sparc_TARGET_ARCH
142 AddrRegImm r (ImmInt n)
143 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
144 | otherwise -> Nothing
147 AddrRegImm r (ImmInteger n)
148 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
149 | otherwise -> Nothing
150 where n2 = n + toInteger off
152 AddrRegReg r (FixedReg ILIT(0))
153 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
154 | otherwise -> Nothing
161 #if alpha_TARGET_ARCH
163 fits8Bits :: Integer -> Bool
164 fits8Bits i = i >= -256 && i < 256
168 #if sparc_TARGET_ARCH
170 fits13Bits :: Int -> Bool
173 fits13Bits :: Integer -> Bool
176 fits13Bits :: Integral a => a -> Bool
177 fits13Bits x = x >= -4096 && x < 4096
181 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
186 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
188 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
189 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
190 The rest are either in real machine registers or stored as offsets
194 data RegLoc = Save StixTree | Always StixTree
197 Trees for register save locations:
199 saveLoc :: MagicId -> StixTree
201 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
205 stgReg :: MagicId -> RegLoc
208 = case (magicIdRegMaybe x) of
209 Just _ -> Save nonReg
210 Nothing -> Always nonReg
212 offset = baseRegOffset x
214 baseLoc = case (magicIdRegMaybe BaseReg) of
215 Just _ -> StReg (StixMagicId BaseReg)
216 Nothing -> sStLitLbl SLIT("MainRegTable")
219 StkStubReg -> sStLitLbl SLIT("STK_STUB_closure")
220 StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame")
221 BaseReg -> sStLitLbl SLIT("MainRegTable")
222 -- these Hp&HpLim cases perhaps should
223 -- not be here for i386 (???) WDP 96/03
224 Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo"))
225 HpLim -> StInd PtrRep (sStLitLbl
226 (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR)))
227 TagReg -> StInd IntRep (StPrim IntSubOp [infoptr,
228 StInt (1*BYTES_PER_WORD)])
230 r2 = VanillaReg PtrRep ILIT(2)
231 infoptr = case (stgReg r2) of
233 Save _ -> StReg (StixMagicId r2)
234 _ -> StInd (magicIdPrimRep x)
235 (StPrim IntAddOp [baseLoc,
236 StInt (toInteger (offset*BYTES_PER_WORD))])
239 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
241 @spRel@ gives us a stack relative addressing mode for volatile
242 temporaries and for excess call arguments. @fpRel@, where
243 applicable, is the same but for the frame pointer.
246 spRel :: Int -- desired stack offset in words, positive or negative
251 = Addr (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
253 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
256 #if sparc_TARGET_ARCH
258 -- Duznae work for offsets greater than 13 bits; we just hope for
261 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
265 %************************************************************************
267 \subsection[Reg]{Real registers}
269 %************************************************************************
271 Static Registers correspond to actual machine registers. These should
272 be avoided until the last possible moment.
274 Dynamic registers are allocated on the fly, usually to represent a single
275 value in the abstract assembly code (i.e. dynamic registers are usually
276 single assignment). Ultimately, they are mapped to available machine
277 registers before spitting out the code.
281 = FixedReg FAST_INT -- A pre-allocated machine register
283 | MappedReg FAST_INT -- A dynamically allocated machine register
285 | MemoryReg Int PrimRep -- A machine "register" actually held in
286 -- a memory allocated table of
287 -- registers which didn't fit in real
290 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
291 -- always mapped to one of the earlier
292 -- two (?) before we're done.
294 mkReg :: Unique -> PrimRep -> Reg
297 getNewRegNCG :: PrimRep -> UniqSM Reg
299 = getUnique `thenUs` \ u ->
300 returnUs (UnmappedReg u pk)
302 instance Text Reg where
303 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
304 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
305 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
306 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
309 instance Outputable Reg where
310 ppr sty r = ppStr (show r)
313 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
314 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
315 cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i'
316 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u'
318 = let tag1 = tagReg r1
321 if tag1 _LT_ tag2 then LT_ else GT_
323 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
324 tagReg (MappedReg _) = ILIT(2)
325 tagReg (MemoryReg _ _) = ILIT(3)
326 tagReg (UnmappedReg _ _) = ILIT(4)
328 cmp_i :: Int -> Int -> TAG_
329 cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_
331 cmp_ihash :: FAST_INT -> FAST_INT -> TAG_
332 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_
334 instance Eq Reg where
335 a == b = case cmpReg a b of { EQ_ -> True; _ -> False }
336 a /= b = case cmpReg a b of { EQ_ -> False; _ -> True }
338 instance Ord Reg where
339 a <= b = case cmpReg a b of { LT_ -> True; EQ_ -> True; GT__ -> False }
340 a < b = case cmpReg a b of { LT_ -> True; EQ_ -> False; GT__ -> False }
341 a >= b = case cmpReg a b of { LT_ -> False; EQ_ -> True; GT__ -> True }
342 a > b = case cmpReg a b of { LT_ -> False; EQ_ -> False; GT__ -> True }
343 _tagCmp a b = case cmpReg a b of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT }
345 instance NamedThing Reg where
346 -- the *only* method that should be defined is "getItsUnique"!
347 -- (so we can use UniqFMs/UniqSets on Regs
348 getItsUnique (UnmappedReg u _) = u
349 getItsUnique (FixedReg i) = mkPseudoUnique1 IBOX(i)
350 getItsUnique (MappedReg i) = mkPseudoUnique2 IBOX(i)
351 getItsUnique (MemoryReg i _) = mkPseudoUnique3 i
357 realReg :: RegNo -> Reg
359 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
361 extractMappedRegNos :: [Reg] -> [RegNo]
363 extractMappedRegNos regs
366 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
367 ex _ acc = acc -- leave it out
370 ** Machine-specific Reg stuff: **
372 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
373 point registers. The mapping of STG registers to alpha machine registers
374 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
376 #if alpha_TARGET_ARCH
380 v0, f0, ra, pv, gp, sp, zero :: Reg
382 f0 = realReg (fReg 0)
383 ra = FixedReg ILIT(26)
385 gp = FixedReg ILIT(29)
386 sp = FixedReg ILIT(30)
387 zero = FixedReg ILIT(31)
389 t9, t10, t11, t12 :: Reg
397 Intel x86 architecture:
398 - All registers except 7 (esp) are available for use.
399 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
400 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
401 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
402 - Registers 8-15 hold extended floating point values.
406 gReg,fReg :: Int -> Int
410 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
411 eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
412 ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 }
413 ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 }
414 edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 }
415 esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 }
416 edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 }
417 ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 }
418 esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 }
419 st0 = realReg (fReg 0)
420 st1 = realReg (fReg 1)
421 st2 = realReg (fReg 2)
422 st3 = realReg (fReg 3)
423 st4 = realReg (fReg 4)
424 st5 = realReg (fReg 5)
425 st6 = realReg (fReg 6)
426 st7 = realReg (fReg 7)
431 The SPARC has 64 registers of interest; 32 integer registers and 32
432 floating point registers. The mapping of STG registers to SPARC
433 machine registers is defined in StgRegs.h. We are, of course,
434 prepared for any eventuality.
437 #if sparc_TARGET_ARCH
439 gReg,lReg,iReg,oReg,fReg :: Int -> Int
447 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
448 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
450 g0, fp, sp, o0, f0 :: Reg
451 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
452 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
453 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
454 o0 = realReg (oReg 0)
455 f0 = realReg (fReg 0)
460 Redefine the literals used for machine-registers with non-numeric
461 names in the header files. Gag me with a spoon, eh?
463 #if alpha_TARGET_ARCH
515 #if sparc_TARGET_ARCH
584 baseRegOffset :: MagicId -> Int
586 baseRegOffset StkOReg = OFFSET_StkO
587 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
588 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
589 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
590 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
591 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
592 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
593 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
594 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
595 baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1
596 baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2
597 baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3
598 baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4
599 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1
600 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2
601 baseRegOffset TagReg = OFFSET_Tag
602 baseRegOffset RetReg = OFFSET_Ret
603 baseRegOffset SpA = OFFSET_SpA
604 baseRegOffset SuA = OFFSET_SuA
605 baseRegOffset SpB = OFFSET_SpB
606 baseRegOffset SuB = OFFSET_SuB
607 baseRegOffset Hp = OFFSET_Hp
608 baseRegOffset HpLim = OFFSET_HpLim
609 baseRegOffset LivenessReg = OFFSET_Liveness
611 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
612 baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg"
613 baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg"
614 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
615 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
620 callerSaves :: MagicId -> Bool
622 #ifdef CALLER_SAVES_Base
623 callerSaves BaseReg = True
625 #ifdef CALLER_SAVES_StkO
626 callerSaves StkOReg = True
628 #ifdef CALLER_SAVES_R1
629 callerSaves (VanillaReg _ ILIT(1)) = True
631 #ifdef CALLER_SAVES_R2
632 callerSaves (VanillaReg _ ILIT(2)) = True
634 #ifdef CALLER_SAVES_R3
635 callerSaves (VanillaReg _ ILIT(3)) = True
637 #ifdef CALLER_SAVES_R4
638 callerSaves (VanillaReg _ ILIT(4)) = True
640 #ifdef CALLER_SAVES_R5
641 callerSaves (VanillaReg _ ILIT(5)) = True
643 #ifdef CALLER_SAVES_R6
644 callerSaves (VanillaReg _ ILIT(6)) = True
646 #ifdef CALLER_SAVES_R7
647 callerSaves (VanillaReg _ ILIT(7)) = True
649 #ifdef CALLER_SAVES_R8
650 callerSaves (VanillaReg _ ILIT(8)) = True
652 #ifdef CALLER_SAVES_FltReg1
653 callerSaves (FloatReg ILIT(1)) = True
655 #ifdef CALLER_SAVES_FltReg2
656 callerSaves (FloatReg ILIT(2)) = True
658 #ifdef CALLER_SAVES_FltReg3
659 callerSaves (FloatReg ILIT(3)) = True
661 #ifdef CALLER_SAVES_FltReg4
662 callerSaves (FloatReg ILIT(4)) = True
664 #ifdef CALLER_SAVES_DblReg1
665 callerSaves (DoubleReg ILIT(1)) = True
667 #ifdef CALLER_SAVES_DblReg2
668 callerSaves (DoubleReg ILIT(2)) = True
670 #ifdef CALLER_SAVES_Tag
671 callerSaves TagReg = True
673 #ifdef CALLER_SAVES_Ret
674 callerSaves RetReg = True
676 #ifdef CALLER_SAVES_SpA
677 callerSaves SpA = True
679 #ifdef CALLER_SAVES_SuA
680 callerSaves SuA = True
682 #ifdef CALLER_SAVES_SpB
683 callerSaves SpB = True
685 #ifdef CALLER_SAVES_SuB
686 callerSaves SuB = True
688 #ifdef CALLER_SAVES_Hp
689 callerSaves Hp = True
691 #ifdef CALLER_SAVES_HpLim
692 callerSaves HpLim = True
694 #ifdef CALLER_SAVES_Liveness
695 callerSaves LivenessReg = True
697 #ifdef CALLER_SAVES_StdUpdRetVec
698 callerSaves StdUpdRetVecReg = True
700 #ifdef CALLER_SAVES_StkStub
701 callerSaves StkStubReg = True
703 callerSaves _ = False
707 magicIdRegMaybe :: MagicId -> Maybe Reg
710 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
713 magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg))
716 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
719 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
722 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
725 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
728 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
731 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
734 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
737 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
740 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1))
743 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2))
746 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3))
749 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4))
752 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1))
755 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2))
758 magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg))
761 magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret))
764 magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA))
767 magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA))
770 magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB))
773 magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB))
776 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
779 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
782 magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness))
784 #ifdef REG_StdUpdRetVec
785 magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec))
788 magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub))
790 magicIdRegMaybe _ = Nothing
793 %************************************************************************
795 \subsection{Free, reserved, call-clobbered, and argument registers}
797 %************************************************************************
799 @freeRegs@ is the list of registers we can use in register allocation.
800 @freeReg@ (below) says if a particular register is free.
802 With a per-instruction clobber list, we might be able to get some of
803 these back, but it's probably not worth the hassle.
805 @callClobberedRegs@ ... the obvious.
807 @argRegs@: assuming a call with N arguments, what registers will be
808 used to hold arguments? (NB: it doesn't know whether the arguments
809 are integer or floating-point...)
812 reservedRegs :: [RegNo]
814 #if alpha_TARGET_ARCH
815 = [NCG_Reserved_I1, NCG_Reserved_I2,
816 NCG_Reserved_F1, NCG_Reserved_F2]
819 = [{-certainly cannot afford any!-}]
821 #if sparc_TARGET_ARCH
822 = [NCG_Reserved_I1, NCG_Reserved_I2,
823 NCG_Reserved_F1, NCG_Reserved_F2,
824 NCG_Reserved_D1, NCG_Reserved_D2]
827 -------------------------------
830 = freeMappedRegs IF_ARCH_alpha( [0..63],
831 IF_ARCH_i386( [0..15],
832 IF_ARCH_sparc( [0..63],)))
834 -------------------------------
835 callClobberedRegs :: [Reg]
838 #if alpha_TARGET_ARCH
839 [0, 1, 2, 3, 4, 5, 6, 7, 8,
840 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
841 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
842 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
843 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
844 #endif {- alpha_TARGET_ARCH -}
847 #endif {- i386_TARGET_ARCH -}
848 #if sparc_TARGET_ARCH
850 [oReg i | i <- [0..5]] ++
851 [gReg i | i <- [1..7]] ++
852 [fReg i | i <- [0..31]] )
853 #endif {- sparc_TARGET_ARCH -}
855 -------------------------------
856 argRegs :: Int -> [Reg]
859 #if alpha_TARGET_ARCH
860 argRegs 1 = freeMappedRegs [16, fReg 16]
861 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
862 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
863 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
864 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
865 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
866 #endif {- alpha_TARGET_ARCH -}
868 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
869 #endif {- i386_TARGET_ARCH -}
870 #if sparc_TARGET_ARCH
871 argRegs 1 = freeMappedRegs (map oReg [0])
872 argRegs 2 = freeMappedRegs (map oReg [0,1])
873 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
874 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
875 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
876 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
877 #endif {- sparc_TARGET_ARCH -}
878 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
880 -------------------------------
882 #if alpha_TARGET_ARCH
883 allArgRegs :: [(Reg, Reg)]
885 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
886 #endif {- alpha_TARGET_ARCH -}
888 #if sparc_TARGET_ARCH
891 allArgRegs = map realReg [oReg i | i <- [0..5]]
892 #endif {- sparc_TARGET_ARCH -}
894 -------------------------------
895 freeMappedRegs :: [Int] -> [Reg]
901 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
905 freeReg :: FAST_INT -> FAST_BOOL
907 #if alpha_TARGET_ARCH
908 freeReg ILIT(26) = _FALSE_ -- return address (ra)
909 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
910 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
911 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
912 freeReg ILIT(31) = _FALSE_ -- always zero (zero)
913 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
917 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
920 #if sparc_TARGET_ARCH
921 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
922 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
923 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
924 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
925 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
926 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
930 freeReg ILIT(REG_Base) = _FALSE_
933 freeReg ILIT(REG_StkO) = _FALSE_
936 freeReg ILIT(REG_R1) = _FALSE_
939 freeReg ILIT(REG_R2) = _FALSE_
942 freeReg ILIT(REG_R3) = _FALSE_
945 freeReg ILIT(REG_R4) = _FALSE_
948 freeReg ILIT(REG_R5) = _FALSE_
951 freeReg ILIT(REG_R6) = _FALSE_
954 freeReg ILIT(REG_R7) = _FALSE_
957 freeReg ILIT(REG_R8) = _FALSE_
960 freeReg ILIT(REG_Flt1) = _FALSE_
963 freeReg ILIT(REG_Flt2) = _FALSE_
966 freeReg ILIT(REG_Flt3) = _FALSE_
969 freeReg ILIT(REG_Flt4) = _FALSE_
972 freeReg ILIT(REG_Dbl1) = _FALSE_
975 freeReg ILIT(REG_Dbl2) = _FALSE_
978 freeReg ILIT(REG_Tag) = _FALSE_
981 freeReg ILIT(REG_Ret) = _FALSE_
984 freeReg ILIT(REG_SpA) = _FALSE_
987 freeReg ILIT(REG_SuA) = _FALSE_
990 freeReg ILIT(REG_SpB) = _FALSE_
993 freeReg ILIT(REG_SuB) = _FALSE_
996 freeReg ILIT(REG_Hp) = _FALSE_
999 freeReg ILIT(REG_HpLim) = _FALSE_
1002 freeReg ILIT(REG_Liveness) = _FALSE_
1004 #ifdef REG_StdUpdRetVec
1005 freeReg ILIT(REG_StdUpdRetVec) = _FALSE_
1008 freeReg ILIT(REG_StkStub) = _FALSE_
1012 -- we hang onto two double regs for dedicated
1013 -- use; this is not necessary on Alphas and
1014 -- may not be on other non-SPARCs.
1016 | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_
1019 | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_
1021 | otherwise = _TRUE_