2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
45 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
48 , eax, ebx, ecx, edx, esi, esp
49 , fake0, fake1, fake2, fake3, fake4, fake5
54 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
60 #include "HsVersions.h"
62 import AbsCSyn ( MagicId(..) )
63 import AbsCUtils ( magicIdPrimRep )
64 import CLabel ( CLabel, mkMainRegTableLabel )
65 import PrimOp ( PrimOp(..) )
66 import PrimRep ( PrimRep(..) )
67 import Stix ( StixTree(..), StixReg(..),
68 getUniqueNat, returnNat, thenNat, NatM )
69 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
72 --import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM )
76 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
81 | ImmInteger Integer -- Sigh.
82 | ImmCLbl CLabel -- AbstractC Label (with baggage)
83 | ImmLab Bool SDoc -- Simple string label (underscore-able)
84 -- Bool==True ==> in a different DLL
85 | ImmLit SDoc -- Simple string
89 | LO Imm -- Possible restrictions...
92 strImmLit s = ImmLit (text s)
95 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
106 = AddrBaseIndex Base Index Displacement
109 type Base = Maybe Reg
110 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
111 type Displacement = Imm
114 #if sparc_TARGET_ARCH
119 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
123 #if alpha_TARGET_ARCH
124 _ -> panic "MachMisc.addrOffset not defined for Alpha"
127 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
128 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
129 AddrBaseIndex r i (ImmInteger n)
130 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
133 #if sparc_TARGET_ARCH
134 AddrRegImm r (ImmInt n)
135 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
136 | otherwise -> Nothing
139 AddrRegImm r (ImmInteger n)
140 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
141 | otherwise -> Nothing
142 where n2 = n + toInteger off
144 AddrRegReg r (FixedReg ILIT(0))
145 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
146 | otherwise -> Nothing
153 #if alpha_TARGET_ARCH
155 fits8Bits :: Integer -> Bool
156 fits8Bits i = i >= -256 && i < 256
160 #if sparc_TARGET_ARCH
162 fits13Bits :: Int -> Bool
165 fits13Bits :: Integer -> Bool
168 fits13Bits :: Integral a => a -> Bool
169 fits13Bits x = x >= -4096 && x < 4096
173 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
174 ++show i++");\nprobably because of large constant data structures;" ++
175 "\nworkaround: use -fvia-C on this module.\n")
180 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
182 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
183 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
184 The rest are either in real machine registers or stored as offsets
188 data RegLoc = Save StixTree | Always StixTree
191 Trees for register save locations:
193 saveLoc :: MagicId -> StixTree
195 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
199 stgReg :: MagicId -> RegLoc
202 = case (magicIdRegMaybe x) of
203 Just _ -> Save nonReg
204 Nothing -> Always nonReg
206 offset = baseRegOffset x
208 baseLoc = case (magicIdRegMaybe BaseReg) of
209 Just _ -> StReg (StixMagicId BaseReg)
210 Nothing -> StCLbl mkMainRegTableLabel
213 BaseReg -> StCLbl mkMainRegTableLabel
215 _ -> StInd (magicIdPrimRep x)
216 (StPrim IntAddOp [baseLoc,
217 StInt (toInteger (offset*BYTES_PER_WORD))])
220 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
222 @spRel@ gives us a stack relative addressing mode for volatile
223 temporaries and for excess call arguments. @fpRel@, where
224 applicable, is the same but for the frame pointer.
227 spRel :: Int -- desired stack offset in words, positive or negative
232 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
234 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
237 #if sparc_TARGET_ARCH
238 fpRel :: Int -> MachRegsAddr
239 -- Duznae work for offsets greater than 13 bits; we just hope for
242 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
246 %************************************************************************
248 \subsection[Reg]{Real registers}
250 %************************************************************************
252 Static Registers correspond to actual machine registers. These should
253 be avoided until the last possible moment.
255 Dynamic registers are allocated on the fly, usually to represent a single
256 value in the abstract assembly code (i.e. dynamic registers are usually
257 single assignment). Ultimately, they are mapped to available machine
258 registers before spitting out the code.
262 = FixedReg FAST_INT -- A pre-allocated machine register
264 | MappedReg FAST_INT -- A dynamically allocated machine register
266 | MemoryReg Int PrimRep -- A machine "register" actually held in
267 -- a memory allocated table of
268 -- registers which didn't fit in real
271 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
272 -- always mapped to one of the earlier
273 -- two (?) before we're done.
274 mkReg :: Unique -> PrimRep -> Reg
277 getNewRegNCG :: PrimRep -> NatM Reg
279 = getUniqueNat `thenNat` \ u ->
280 returnNat (UnmappedReg u pk)
282 instance Show Reg where
283 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
284 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
285 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
286 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
289 instance Outputable Reg where
290 ppr r = text (show r)
293 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
294 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
295 cmpReg (MemoryReg i _) (MemoryReg i' _) = i `compare` i'
296 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = compare u u'
298 = let tag1 = tagReg r1
301 if tag1 _LT_ tag2 then LT else GT
303 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
304 tagReg (MappedReg _) = ILIT(2)
305 tagReg (MemoryReg _ _) = ILIT(3)
306 tagReg (UnmappedReg _ _) = ILIT(4)
308 cmp_ihash :: FAST_INT -> FAST_INT -> Ordering
309 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ else if a1 _LT_ a2 then LT else GT
311 instance Eq Reg where
312 a == b = case (a `compare` b) of { EQ -> True; _ -> False }
313 a /= b = case (a `compare` b) of { EQ -> False; _ -> True }
315 instance Ord Reg where
316 a <= b = case (a `compare` b) of { LT -> True; EQ -> True; GT -> False }
317 a < b = case (a `compare` b) of { LT -> True; EQ -> False; GT -> False }
318 a >= b = case (a `compare` b) of { LT -> False; EQ -> True; GT -> True }
319 a > b = case (a `compare` b) of { LT -> False; EQ -> False; GT -> True }
320 compare a b = cmpReg a b
322 instance Uniquable Reg where
323 getUnique (UnmappedReg u _) = u
324 getUnique (FixedReg i) = mkPseudoUnique1 IBOX(i)
325 getUnique (MappedReg i) = mkPseudoUnique2 IBOX(i)
326 getUnique (MemoryReg i _) = mkPseudoUnique3 i
332 realReg :: RegNo -> Reg
334 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
336 extractMappedRegNos :: [Reg] -> [RegNo]
338 extractMappedRegNos regs
341 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
342 ex _ acc = acc -- leave it out
344 mappedRegNo :: Reg -> RegNo
345 mappedRegNo (MappedReg i) = IBOX(i)
346 mappedRegNo _ = pprPanic "mappedRegNo" empty
349 ** Machine-specific Reg stuff: **
351 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
352 point registers. The mapping of STG registers to alpha machine registers
353 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
355 #if alpha_TARGET_ARCH
359 v0, f0, ra, pv, gp, sp, zeroh :: Reg
361 f0 = realReg (fReg 0)
362 ra = FixedReg ILIT(26)
364 gp = FixedReg ILIT(29)
365 sp = FixedReg ILIT(30)
366 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
368 t9, t10, t11, t12 :: Reg
376 Intel x86 architecture:
377 - All registers except 7 (esp) are available for use.
378 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
379 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
380 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
381 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
382 fp registers, and 3-operand insns for them, and we translate this into
383 real stack-based x86 fp code after register allocation.
388 gReg,fReg :: Int -> Int
392 fake0, fake1, fake2, fake3, fake4, fake5, eax, ebx, ecx, edx, esp :: Reg
393 eax = realReg (gReg 0)
394 ebx = realReg (gReg 1)
395 ecx = realReg (gReg 2)
396 edx = realReg (gReg 3)
397 esi = realReg (gReg 4)
398 edi = realReg (gReg 5)
399 ebp = realReg (gReg 6)
400 esp = realReg (gReg 7)
401 fake0 = realReg (fReg 0)
402 fake1 = realReg (fReg 1)
403 fake2 = realReg (fReg 2)
404 fake3 = realReg (fReg 3)
405 fake4 = realReg (fReg 4)
406 fake5 = realReg (fReg 5)
410 The SPARC has 64 registers of interest; 32 integer registers and 32
411 floating point registers. The mapping of STG registers to SPARC
412 machine registers is defined in StgRegs.h. We are, of course,
413 prepared for any eventuality.
416 #if sparc_TARGET_ARCH
418 gReg,lReg,iReg,oReg,fReg :: Int -> Int
426 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
427 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
429 g0, fp, sp, o0, f0 :: Reg
430 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
431 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
432 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
433 o0 = realReg (oReg 0)
434 f0 = realReg (fReg 0)
439 Redefine the literals used for machine-registers with non-numeric
440 names in the header files. Gag me with a spoon, eh?
442 #if alpha_TARGET_ARCH
492 #if sparc_TARGET_ARCH
561 baseRegOffset :: MagicId -> Int
563 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
564 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
565 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
566 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
567 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
568 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
569 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
570 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
571 baseRegOffset (VanillaReg _ ILIT(9)) = OFFSET_R9
572 baseRegOffset (VanillaReg _ ILIT(10)) = OFFSET_R10
573 baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1
574 baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2
575 baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3
576 baseRegOffset (FloatReg ILIT(4)) = OFFSET_F4
577 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_D1
578 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_D2
579 baseRegOffset Sp = OFFSET_Sp
580 baseRegOffset Su = OFFSET_Su
581 baseRegOffset SpLim = OFFSET_SpLim
583 baseRegOffset (LongReg _ ILIT(1)) = OFFSET_Lng1
586 baseRegOffset (LongReg _ ILIT(2)) = OFFSET_Lng2
588 baseRegOffset Hp = OFFSET_Hp
589 baseRegOffset HpLim = OFFSET_HpLim
590 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
591 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
593 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
594 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
595 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
600 callerSaves :: MagicId -> Bool
602 #ifdef CALLER_SAVES_Base
603 callerSaves BaseReg = True
605 #ifdef CALLER_SAVES_R1
606 callerSaves (VanillaReg _ ILIT(1)) = True
608 #ifdef CALLER_SAVES_R2
609 callerSaves (VanillaReg _ ILIT(2)) = True
611 #ifdef CALLER_SAVES_R3
612 callerSaves (VanillaReg _ ILIT(3)) = True
614 #ifdef CALLER_SAVES_R4
615 callerSaves (VanillaReg _ ILIT(4)) = True
617 #ifdef CALLER_SAVES_R5
618 callerSaves (VanillaReg _ ILIT(5)) = True
620 #ifdef CALLER_SAVES_R6
621 callerSaves (VanillaReg _ ILIT(6)) = True
623 #ifdef CALLER_SAVES_R7
624 callerSaves (VanillaReg _ ILIT(7)) = True
626 #ifdef CALLER_SAVES_R8
627 callerSaves (VanillaReg _ ILIT(8)) = True
629 #ifdef CALLER_SAVES_F1
630 callerSaves (FloatReg ILIT(1)) = True
632 #ifdef CALLER_SAVES_F2
633 callerSaves (FloatReg ILIT(2)) = True
635 #ifdef CALLER_SAVES_F3
636 callerSaves (FloatReg ILIT(3)) = True
638 #ifdef CALLER_SAVES_F4
639 callerSaves (FloatReg ILIT(4)) = True
641 #ifdef CALLER_SAVES_D1
642 callerSaves (DoubleReg ILIT(1)) = True
644 #ifdef CALLER_SAVES_D2
645 callerSaves (DoubleReg ILIT(2)) = True
647 #ifdef CALLER_SAVES_L1
648 callerSaves (LongReg _ ILIT(1)) = True
650 #ifdef CALLER_SAVES_Sp
651 callerSaves Sp = True
653 #ifdef CALLER_SAVES_Su
654 callerSaves Su = True
656 #ifdef CALLER_SAVES_SpLim
657 callerSaves SpLim = True
659 #ifdef CALLER_SAVES_Hp
660 callerSaves Hp = True
662 #ifdef CALLER_SAVES_HpLim
663 callerSaves HpLim = True
665 #ifdef CALLER_SAVES_CurrentTSO
666 callerSaves CurrentTSO = True
668 #ifdef CALLER_SAVES_CurrentNursery
669 callerSaves CurrentNursery = True
671 callerSaves _ = False
675 magicIdRegMaybe :: MagicId -> Maybe Reg
678 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
681 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
684 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
687 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
690 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
693 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
696 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
699 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
702 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
705 magicIdRegMaybe (VanillaReg _ ILIT(9)) = Just (FixedReg ILIT(REG_R9))
708 magicIdRegMaybe (VanillaReg _ ILIT(10)) = Just (FixedReg ILIT(REG_R10))
711 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_F1))
714 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_F2))
717 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_F3))
720 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_F4))
723 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_D1))
726 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_D2))
729 magicIdRegMaybe Sp = Just (FixedReg ILIT(REG_Sp))
732 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (FixedReg ILIT(REG_Lng1))
735 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (FixedReg ILIT(REG_Lng2))
738 magicIdRegMaybe Su = Just (FixedReg ILIT(REG_Su))
741 magicIdRegMaybe SpLim = Just (FixedReg ILIT(REG_SpLim))
744 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
747 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
749 #ifdef REG_CurrentTSO
750 magicIdRegMaybe CurrentTSO = Just (FixedReg ILIT(REG_CurrentTSO))
752 #ifdef REG_CurrentNursery
753 magicIdRegMaybe CurrentNursery = Just (FixedReg ILIT(REG_CurrentNursery))
755 magicIdRegMaybe _ = Nothing
759 -------------------------------
762 = freeMappedRegs IF_ARCH_alpha( [0..63],
763 IF_ARCH_i386( [0..13],
764 IF_ARCH_sparc( [0..63],)))
766 -------------------------------
767 callClobberedRegs :: [Reg]
770 #if alpha_TARGET_ARCH
771 [0, 1, 2, 3, 4, 5, 6, 7, 8,
772 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
773 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
774 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
775 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
776 #endif {- alpha_TARGET_ARCH -}
779 #endif {- i386_TARGET_ARCH -}
780 #if sparc_TARGET_ARCH
782 [oReg i | i <- [0..5]] ++
783 [gReg i | i <- [1..7]] ++
784 [fReg i | i <- [0..31]] )
785 #endif {- sparc_TARGET_ARCH -}
787 -------------------------------
788 argRegs :: Int -> [Reg]
792 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
794 #if alpha_TARGET_ARCH
795 argRegs 1 = freeMappedRegs [16, fReg 16]
796 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
797 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
798 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
799 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
800 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
801 #endif {- alpha_TARGET_ARCH -}
802 #if sparc_TARGET_ARCH
803 argRegs 1 = freeMappedRegs (map oReg [0])
804 argRegs 2 = freeMappedRegs (map oReg [0,1])
805 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
806 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
807 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
808 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
809 #endif {- sparc_TARGET_ARCH -}
810 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
811 #endif {- i386_TARGET_ARCH -}
813 -------------------------------
815 #if alpha_TARGET_ARCH
816 allArgRegs :: [(Reg, Reg)]
818 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
819 #endif {- alpha_TARGET_ARCH -}
821 #if sparc_TARGET_ARCH
824 allArgRegs = map realReg [oReg i | i <- [0..5]]
825 #endif {- sparc_TARGET_ARCH -}
827 -------------------------------
828 freeMappedRegs :: [Int] -> [Reg]
834 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
838 freeReg :: FAST_INT -> FAST_BOOL
840 #if alpha_TARGET_ARCH
841 freeReg ILIT(26) = _FALSE_ -- return address (ra)
842 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
843 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
844 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
845 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
846 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
850 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
853 #if sparc_TARGET_ARCH
854 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
855 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
856 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
857 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
858 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
859 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
863 freeReg ILIT(REG_Base) = _FALSE_
866 freeReg ILIT(REG_R1) = _FALSE_
869 freeReg ILIT(REG_R2) = _FALSE_
872 freeReg ILIT(REG_R3) = _FALSE_
875 freeReg ILIT(REG_R4) = _FALSE_
878 freeReg ILIT(REG_R5) = _FALSE_
881 freeReg ILIT(REG_R6) = _FALSE_
884 freeReg ILIT(REG_R7) = _FALSE_
887 freeReg ILIT(REG_R8) = _FALSE_
890 freeReg ILIT(REG_F1) = _FALSE_
893 freeReg ILIT(REG_F2) = _FALSE_
896 freeReg ILIT(REG_F3) = _FALSE_
899 freeReg ILIT(REG_F4) = _FALSE_
902 freeReg ILIT(REG_D1) = _FALSE_
905 freeReg ILIT(REG_D2) = _FALSE_
908 freeReg ILIT(REG_Sp) = _FALSE_
911 freeReg ILIT(REG_Su) = _FALSE_
914 freeReg ILIT(REG_SpLim) = _FALSE_
917 freeReg ILIT(REG_Hp) = _FALSE_
920 freeReg ILIT(REG_HpLim) = _FALSE_
923 -- we hang onto two double regs for dedicated
924 -- use; this is not necessary on Alphas and
925 -- may not be on other non-SPARCs.
927 | n _EQ_ (ILIT(REG_D1) _ADD_ ILIT(1)) = _FALSE_
930 | n _EQ_ (ILIT(REG_D2) _ADD_ ILIT(1)) = _FALSE_