1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
24 #include "HsVersions.h"
26 import Cmm ( BlockId )
27 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH
28 import MachOp ( MachRep(..) )
33 import Constants ( rESERVED_C_STACK_BYTES )
36 -- -----------------------------------------------------------------------------
39 -- @regUsage@ returns the sets of src and destination registers used
40 -- by a particular instruction. Machine registers that are
41 -- pre-allocated to stgRegs are filtered out, because they are
42 -- uninteresting from a register allocation standpoint. (We wouldn't
43 -- want them to end up on the free list!) As far as we are concerned,
44 -- the fixed registers simply don't exist (for allocation purposes,
47 -- regUsage doesn't need to do any trickery for jumps and such. Just
48 -- state precisely the regs read and written by that insn. The
49 -- consequences of control flow transfers, as far as register
50 -- allocation goes, are taken care of by the register allocator.
52 data RegUsage = RU [Reg] [Reg]
57 regUsage :: Instr -> RegUsage
59 interesting (VirtualRegI _) = True
60 interesting (VirtualRegHi _) = True
61 interesting (VirtualRegF _) = True
62 interesting (VirtualRegD _) = True
63 interesting (RealReg i) = isFastTrue (freeReg i)
67 regUsage instr = case instr of
68 LD B reg addr -> usage (regAddr addr, [reg, t9])
69 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
70 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
71 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 LD sz reg addr -> usage (regAddr addr, [reg])
73 LDA reg addr -> usage (regAddr addr, [reg])
74 LDAH reg addr -> usage (regAddr addr, [reg])
75 LDGP reg addr -> usage (regAddr addr, [reg])
76 LDI sz reg imm -> usage ([], [reg])
77 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
78 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
79 ST sz reg addr -> usage (reg : regAddr addr, [])
80 CLR reg -> usage ([], [reg])
81 ABS sz ri reg -> usage (regRI ri, [reg])
82 NEG sz ov ri reg -> usage (regRI ri, [reg])
83 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
84 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
89 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 NOT ri reg -> usage (regRI ri, [reg])
91 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 FCLR reg -> usage ([], [reg])
104 FABS r1 r2 -> usage ([r1], [r2])
105 FNEG sz r1 r2 -> usage ([r1], [r2])
106 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
107 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
111 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
112 FMOV r1 r2 -> usage ([r1], [r2])
115 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
116 BI cond reg lbl -> usage ([reg], [])
117 BF cond reg lbl -> usage ([reg], [])
118 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
120 BSR _ n -> RU (argRegSet n) callClobberedRegSet
121 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
126 usage (src, dst) = RU (mkRegSet (filter interesting src))
127 (mkRegSet (filter interesting dst))
129 interesting (FixedReg _) = False
132 regAddr (AddrReg r1) = [r1]
133 regAddr (AddrRegImm r1 _) = [r1]
134 regAddr (AddrImm _) = []
136 regRI (RIReg r) = [r]
139 #endif /* alpha_TARGET_ARCH */
140 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
143 regUsage instr = case instr of
144 MOV sz src dst -> usageRW src dst
145 MOVZxL sz src dst -> usageRW src dst
146 MOVSxL sz src dst -> usageRW src dst
147 LEA sz src dst -> usageRW src dst
148 ADD sz src dst -> usageRM src dst
149 ADC sz src dst -> usageRM src dst
150 SUB sz src dst -> usageRM src dst
151 IMUL sz src dst -> usageRM src dst
152 IMUL64 sd1 sd2 -> mkRU [sd1,sd2] [sd1,sd2]
153 MUL sz src dst -> usageRM src dst
154 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
155 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 AND sz src dst -> usageRM src dst
157 OR sz src dst -> usageRM src dst
158 XOR sz src dst -> usageRM src dst
159 NOT sz op -> usageM op
160 NEGI sz op -> usageM op
161 SHL sz imm dst -> usageRM imm dst
162 SAR sz imm dst -> usageRM imm dst
163 SHR sz imm dst -> usageRM imm dst
164 BT sz imm src -> mkRU (use_R src) []
166 PUSH sz op -> mkRU (use_R op) []
167 POP sz op -> mkRU [] (def_W op)
168 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
169 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
170 SETCC cond op -> mkRU [] (def_W op)
171 JXX cond lbl -> mkRU [] []
172 JMP op -> mkRU (use_R op) []
173 JMP_TBL op ids -> mkRU (use_R op) []
174 CALL (Left imm) -> mkRU [] callClobberedRegs
175 CALL (Right reg) -> mkRU [reg] callClobberedRegs
176 CLTD -> mkRU [eax] [edx]
179 GMOV src dst -> mkRU [src] [dst]
180 GLD sz src dst -> mkRU (use_EA src) [dst]
181 GST sz src dst -> mkRU (src : use_EA dst) []
183 GLDZ dst -> mkRU [] [dst]
184 GLD1 dst -> mkRU [] [dst]
186 GFTOI src dst -> mkRU [src] [dst]
187 GDTOI src dst -> mkRU [src] [dst]
189 GITOF src dst -> mkRU [src] [dst]
190 GITOD src dst -> mkRU [src] [dst]
192 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
193 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
194 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
195 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
197 GCMP sz src1 src2 -> mkRU [src1,src2] []
198 GABS sz src dst -> mkRU [src] [dst]
199 GNEG sz src dst -> mkRU [src] [dst]
200 GSQRT sz src dst -> mkRU [src] [dst]
201 GSIN sz src dst -> mkRU [src] [dst]
202 GCOS sz src dst -> mkRU [src] [dst]
203 GTAN sz src dst -> mkRU [src] [dst]
208 _other -> panic "regUsage: unrecognised instr"
211 -- 2 operand form; first operand Read; second Written
212 usageRW :: Operand -> Operand -> RegUsage
213 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
214 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
216 -- 2 operand form; first operand Read; second Modified
217 usageRM :: Operand -> Operand -> RegUsage
218 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
219 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
221 -- 1 operand form; operand Modified
222 usageM :: Operand -> RegUsage
223 usageM (OpReg reg) = mkRU [reg] [reg]
224 usageM (OpAddr ea) = mkRU (use_EA ea) []
226 -- Registers defd when an operand is written.
227 def_W (OpReg reg) = [reg]
228 def_W (OpAddr ea) = []
230 -- Registers used when an operand is read.
231 use_R (OpReg reg) = [reg]
232 use_R (OpImm imm) = []
233 use_R (OpAddr ea) = use_EA ea
235 -- Registers used to compute an effective address.
236 use_EA (ImmAddr _ _) = []
237 use_EA (AddrBaseIndex Nothing Nothing _) = []
238 use_EA (AddrBaseIndex (Just b) Nothing _) = [b]
239 use_EA (AddrBaseIndex Nothing (Just (i,_)) _) = [i]
240 use_EA (AddrBaseIndex (Just b) (Just (i,_)) _) = [b,i]
242 mkRU src dst = RU (filter interesting src)
243 (filter interesting dst)
245 #endif /* i386_TARGET_ARCH */
246 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
247 #if sparc_TARGET_ARCH
249 regUsage instr = case instr of
250 LD sz addr reg -> usage (regAddr addr, [reg])
251 ST sz reg addr -> usage (reg : regAddr addr, [])
252 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
253 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
254 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
255 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
256 RDY rd -> usage ([], [rd])
257 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
258 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
259 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
260 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
261 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
262 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
263 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
264 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
265 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
266 SETHI imm reg -> usage ([], [reg])
267 FABS s r1 r2 -> usage ([r1], [r2])
268 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
269 FCMP e s r1 r2 -> usage ([r1, r2], [])
270 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
271 FMOV s r1 r2 -> usage ([r1], [r2])
272 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
273 FNEG s r1 r2 -> usage ([r1], [r2])
274 FSQRT s r1 r2 -> usage ([r1], [r2])
275 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
276 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
278 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
279 JMP dst addr -> usage (regAddr addr, [])
281 CALL (Left imm) n True -> noUsage
282 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
283 CALL (Right reg) n True -> usage ([reg], [])
284 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
288 usage (src, dst) = RU (regSetFromList (filter interesting src))
289 (regSetFromList (filter interesting dst))
291 regAddr (AddrRegReg r1 r2) = [r1, r2]
292 regAddr (AddrRegImm r1 _) = [r1]
294 regRI (RIReg r) = [r]
297 #endif /* sparc_TARGET_ARCH */
298 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
299 #if powerpc_TARGET_ARCH
301 regUsage instr = case instr of
302 LD sz reg addr -> usage (regAddr addr, [reg])
303 LA sz reg addr -> usage (regAddr addr, [reg])
304 ST sz reg addr -> usage (reg : regAddr addr, [])
305 STU sz reg addr -> usage (reg : regAddr addr, [])
306 LIS reg imm -> usage ([], [reg])
307 LI reg imm -> usage ([], [reg])
308 MR reg1 reg2 -> usage ([reg2], [reg1])
309 CMP sz reg ri -> usage (reg : regRI ri,[])
310 CMPL sz reg ri -> usage (reg : regRI ri,[])
311 BCC cond lbl -> noUsage
312 MTCTR reg -> usage ([reg],[])
313 BCTR targets -> noUsage
314 BL imm params -> usage (params, callClobberedRegs)
315 BCTRL params -> usage (params, callClobberedRegs)
316 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
317 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
318 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
319 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
320 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
321 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
322 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
323 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
324 MULLW_MayOflo reg1 reg2 reg3
325 -> usage ([reg2,reg3], [reg1])
326 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
327 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
328 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
329 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
330 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
331 NEG reg1 reg2 -> usage ([reg2], [reg1])
332 NOT reg1 reg2 -> usage ([reg2], [reg1])
333 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
334 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
335 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
336 RLWINM reg1 reg2 sh mb me
337 -> usage ([reg2], [reg1])
338 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
339 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
340 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
341 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
342 FNEG r1 r2 -> usage ([r2], [r1])
343 FCMP r1 r2 -> usage ([r1,r2], [])
344 FCTIWZ r1 r2 -> usage ([r2], [r1])
345 FRSP r1 r2 -> usage ([r2], [r1])
346 MFCR reg -> usage ([], [reg])
347 MFLR reg -> usage ([], [reg])
348 FETCHPC reg -> usage ([], [reg])
351 usage (src, dst) = RU (filter interesting src)
352 (filter interesting dst)
353 regAddr (AddrRegReg r1 r2) = [r1, r2]
354 regAddr (AddrRegImm r1 _) = [r1]
356 regRI (RIReg r) = [r]
358 #endif /* powerpc_TARGET_ARCH */
361 -- -----------------------------------------------------------------------------
362 -- Determine the possible destinations from the current instruction.
364 -- (we always assume that the next instruction is also a valid destination;
365 -- if this isn't the case then the jump should be at the end of the basic
368 jumpDests :: Instr -> [BlockId] -> [BlockId]
373 JMP_TBL _ ids -> ids ++ acc
374 #elif powerpc_TARGET_ARCH
376 BCTR targets -> targets ++ acc
381 -- -----------------------------------------------------------------------------
382 -- 'patchRegs' function
384 -- 'patchRegs' takes an instruction and applies the given mapping to
385 -- all the register references.
387 patchRegs :: Instr -> (Reg -> Reg) -> Instr
389 #if alpha_TARGET_ARCH
391 patchRegs instr env = case instr of
392 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
393 LDA reg addr -> LDA (env reg) (fixAddr addr)
394 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
395 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
396 LDI sz reg imm -> LDI sz (env reg) imm
397 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
398 CLR reg -> CLR (env reg)
399 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
400 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
401 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
402 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
403 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
404 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
405 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
406 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
407 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
408 NOT ar reg -> NOT (fixRI ar) (env reg)
409 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
410 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
411 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
412 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
413 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
414 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
415 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
416 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
417 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
418 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
419 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
420 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
421 FCLR reg -> FCLR (env reg)
422 FABS r1 r2 -> FABS (env r1) (env r2)
423 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
424 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
425 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
426 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
427 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
428 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
429 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
430 FMOV r1 r2 -> FMOV (env r1) (env r2)
431 BI cond reg lbl -> BI cond (env reg) lbl
432 BF cond reg lbl -> BF cond (env reg) lbl
433 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
434 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
437 fixAddr (AddrReg r1) = AddrReg (env r1)
438 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
439 fixAddr other = other
441 fixRI (RIReg r) = RIReg (env r)
444 #endif /* alpha_TARGET_ARCH */
445 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
448 patchRegs instr env = case instr of
449 MOV sz src dst -> patch2 (MOV sz) src dst
450 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
451 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
452 LEA sz src dst -> patch2 (LEA sz) src dst
453 ADD sz src dst -> patch2 (ADD sz) src dst
454 ADC sz src dst -> patch2 (ADC sz) src dst
455 SUB sz src dst -> patch2 (SUB sz) src dst
456 IMUL sz src dst -> patch2 (IMUL sz) src dst
457 IMUL64 sd1 sd2 -> IMUL64 (env sd1) (env sd2)
458 MUL sz src dst -> patch2 (MUL sz) src dst
459 IDIV sz op -> patch1 (IDIV sz) op
460 DIV sz op -> patch1 (DIV sz) op
461 AND sz src dst -> patch2 (AND sz) src dst
462 OR sz src dst -> patch2 (OR sz) src dst
463 XOR sz src dst -> patch2 (XOR sz) src dst
464 NOT sz op -> patch1 (NOT sz) op
465 NEGI sz op -> patch1 (NEGI sz) op
466 SHL sz imm dst -> patch1 (SHL sz imm) dst
467 SAR sz imm dst -> patch1 (SAR sz imm) dst
468 SHR sz imm dst -> patch1 (SHR sz imm) dst
469 BT sz imm src -> patch1 (BT sz imm) src
470 TEST sz src dst -> patch2 (TEST sz) src dst
471 CMP sz src dst -> patch2 (CMP sz) src dst
472 PUSH sz op -> patch1 (PUSH sz) op
473 POP sz op -> patch1 (POP sz) op
474 SETCC cond op -> patch1 (SETCC cond) op
475 JMP op -> patch1 JMP op
476 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
478 GMOV src dst -> GMOV (env src) (env dst)
479 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
480 GST sz src dst -> GST sz (env src) (lookupAddr dst)
482 GLDZ dst -> GLDZ (env dst)
483 GLD1 dst -> GLD1 (env dst)
485 GFTOI src dst -> GFTOI (env src) (env dst)
486 GDTOI src dst -> GDTOI (env src) (env dst)
488 GITOF src dst -> GITOF (env src) (env dst)
489 GITOD src dst -> GITOD (env src) (env dst)
491 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
492 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
493 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
494 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
496 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
497 GABS sz src dst -> GABS sz (env src) (env dst)
498 GNEG sz src dst -> GNEG sz (env src) (env dst)
499 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
500 GSIN sz src dst -> GSIN sz (env src) (env dst)
501 GCOS sz src dst -> GCOS sz (env src) (env dst)
502 GTAN sz src dst -> GTAN sz (env src) (env dst)
504 CALL (Left imm) -> instr
505 CALL (Right reg) -> CALL (Right (env reg))
513 _other -> panic "patchRegs: unrecognised instr"
516 patch1 insn op = insn $! patchOp op
517 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
519 patchOp (OpReg reg) = OpReg (env reg)
520 patchOp (OpImm imm) = OpImm imm
521 patchOp (OpAddr ea) = OpAddr (lookupAddr ea)
523 lookupAddr (ImmAddr imm off) = ImmAddr imm off
524 lookupAddr (AddrBaseIndex base index disp)
525 = AddrBaseIndex (lookupBase base) (lookupIndex index) disp
527 lookupBase Nothing = Nothing
528 lookupBase (Just r) = Just (env r)
530 lookupIndex Nothing = Nothing
531 lookupIndex (Just (r,i)) = Just (env r, i)
533 #endif /* i386_TARGET_ARCH */
534 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
535 #if sparc_TARGET_ARCH
537 patchRegs instr env = case instr of
538 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
539 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
540 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
541 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
542 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
543 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
544 RDY rd -> RDY (env rd)
545 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
546 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
547 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
548 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
549 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
550 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
551 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
552 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
553 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
554 SETHI imm reg -> SETHI imm (env reg)
555 FABS s r1 r2 -> FABS s (env r1) (env r2)
556 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
557 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
558 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
559 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
560 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
561 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
562 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
563 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
564 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
565 JMP dsts addr -> JMP dsts (fixAddr addr)
566 CALL (Left i) n t -> CALL (Left i) n t
567 CALL (Right r) n t -> CALL (Right (env r)) n t
570 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
571 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
573 fixRI (RIReg r) = RIReg (env r)
576 #endif /* sparc_TARGET_ARCH */
577 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
578 #if powerpc_TARGET_ARCH
580 patchRegs instr env = case instr of
581 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
582 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
583 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
584 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
585 LIS reg imm -> LIS (env reg) imm
586 LI reg imm -> LI (env reg) imm
587 MR reg1 reg2 -> MR (env reg1) (env reg2)
588 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
589 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
590 BCC cond lbl -> BCC cond lbl
591 MTCTR reg -> MTCTR (env reg)
592 BCTR targets -> BCTR targets
593 BL imm argRegs -> BL imm argRegs -- argument regs
594 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
595 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
596 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
597 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
598 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
599 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
600 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
601 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
602 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
603 MULLW_MayOflo reg1 reg2 reg3
604 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
605 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
606 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
607 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
608 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
609 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
610 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
611 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
612 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
613 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
614 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
615 RLWINM reg1 reg2 sh mb me
616 -> RLWINM (env reg1) (env reg2) sh mb me
617 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
618 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
619 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
620 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
621 FNEG r1 r2 -> FNEG (env r1) (env r2)
622 FCMP r1 r2 -> FCMP (env r1) (env r2)
623 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
624 FRSP r1 r2 -> FRSP (env r1) (env r2)
625 MFCR reg -> MFCR (env reg)
626 MFLR reg -> MFLR (env reg)
627 FETCHPC reg -> FETCHPC (env reg)
630 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
631 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
633 fixRI (RIReg r) = RIReg (env r)
635 #endif /* powerpc_TARGET_ARCH */
637 -- -----------------------------------------------------------------------------
638 -- Detecting reg->reg moves
640 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
641 -- by assigning the src and dest temporaries to the same real register.
643 isRegRegMove :: Instr -> Maybe (Reg,Reg)
644 #ifdef i386_TARGET_ARCH
646 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
647 #elif powerpc_TARGET_ARCH
648 isRegRegMove (MR dst src) = Just (src,dst)
650 #warning ToDo: isRegRegMove
652 isRegRegMove _ = Nothing
654 -- -----------------------------------------------------------------------------
655 -- Generating spill instructions
658 :: Reg -- register to spill (should be a real)
659 -> Int -- current stack delta
660 -> Int -- spill slot to use
662 mkSpillInstr reg delta slot
663 = ASSERT(isRealReg reg)
665 off = spillSlotToOffset slot
667 #ifdef alpha_TARGET_ARCH
668 {-Alpha: spill below the stack pointer (?)-}
669 ST sz dyn (spRel (- (off `div` 8)))
671 #ifdef i386_TARGET_ARCH
672 let off_w = (off-delta) `div` 4
673 in case regClass reg of
674 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
675 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
677 #ifdef sparc_TARGET_ARCH
678 {-SPARC: spill below frame pointer leaving 2 words/spill-}
679 let{off_w = 1 + (off `div` 4);
680 sz = case regClass vreg of {
684 in ST sz dyn (fpRel (- off_w))
686 #ifdef powerpc_TARGET_ARCH
687 let sz = case regClass reg of
690 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
695 :: Reg -- register to load (should be a real)
696 -> Int -- current stack delta
697 -> Int -- spill slot to use
699 mkLoadInstr reg delta slot
700 = ASSERT(isRealReg reg)
702 off = spillSlotToOffset slot
704 #ifdef alpha_TARGET_ARCH
705 LD sz dyn (spRel (- (off `div` 8)))
707 #ifdef i386_TARGET_ARCH
708 let off_w = (off-delta) `div` 4
709 in case regClass reg of {
710 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
711 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
713 #ifdef sparc_TARGET_ARCH
714 let{off_w = 1 + (off `div` 4);
715 sz = case regClass vreg of {
719 in LD sz (fpRel (- off_w)) dyn
721 #ifdef powerpc_TARGET_ARCH
722 let sz = case regClass reg of
725 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
730 spillSlotSize = IF_ARCH_i386(12, 8)
733 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
735 -- convert a spill slot number to a *byte* offset, with no sign:
736 -- decide on a per arch basis whether you are spilling above or below
737 -- the C stack pointer.
738 spillSlotToOffset :: Int -> Int
739 spillSlotToOffset slot
740 | slot >= 0 && slot < maxSpillSlots
741 = 64 + spillSlotSize * slot
743 = pprPanic "spillSlotToOffset:"
744 (text "invalid spill location: " <> int slot)