1 /* -----------------------------------------------------------------------------
2 * $Id: MachRegs.h,v 1.2 1998/12/02 13:21:13 simonm Exp $
4 * Registers used in STG code. Might or might not correspond to
5 * actual machine registers.
7 * ---------------------------------------------------------------------------*/
12 /* This file is #included into Haskell code in the compiler: #defines
13 * only in here please.
16 /* define NO_REGS to omit register declarations - used in RTS C code
17 * that needs all the STG definitions but not the global register
22 /* ----------------------------------------------------------------------------
23 Caller saves and callee-saves regs.
25 Caller-saves regs have to be saved around C-calls made from STG
26 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
27 is designated caller-saves in that machine's C calling convention.
29 Additionally, the following macros should be defined when
31 CALLER_SAVES_USER one or more of R<n>, F, D
34 CALLER_SAVES_SYSTEM one or more of Sp, Su, SpLim, Hp, HpLim
37 This is so that the callWrapper mechanism knows which kind of
38 wrapper to generate for certain types of C call.
39 -------------------------------------------------------------------------- */
41 /* -----------------------------------------------------------------------------
42 The DEC Alpha register mapping
45 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
46 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
47 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
48 caller-save registers provided we do the appropriate save/restore stuff.
50 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
52 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
53 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
54 occasionally required by the assembler to handle non-primitive
55 instructions (e.g. ldb, remq). Sigh!
76 -------------------------------------------------------------------------- */
78 #if defined(alpha_TARGET_ARCH)
79 # define REG(x) __asm__("$" #x)
81 # define CALLER_SAVES_R2
82 # define CALLER_SAVES_R3
83 # define CALLER_SAVES_R4
84 # define CALLER_SAVES_R5
85 # define CALLER_SAVES_R6
86 # define CALLER_SAVES_R7
87 # define CALLER_SAVES_R8
89 # define CALLER_SAVES_USER
110 # define REG_SpLim 11
113 # define REG_HpLim 13
115 # define NCG_Reserved_I1 22
116 # define NCG_Reserved_I2 27
117 # define NCG_Reserved_F1 f29
118 # define NCG_Reserved_F2 f30
120 #endif /* alpha_TARGET_ARCH */
122 /* -----------------------------------------------------------------------------
123 The HP-PA register mapping
125 We cater for HP-PA 1.1.
127 \tr{%r0}--\tr{%r1} are special.
128 \tr{%r2} is the return pointer.
129 \tr{%r3} is the frame pointer.
130 \tr{%r4}--\tr{%r18} are callee-save registers.
131 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
132 \tr{%r20}--\tr{%r22} are caller-save registers.
133 \tr{%r23}--\tr{%r26} are parameter registers.
134 \tr{%r27} is a global data pointer.
135 \tr{%r28}--\tr{%r29} are temporaries.
136 \tr{%r30} is the stack pointer.
137 \tr{%r31} is a temporary.
139 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
140 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
141 -------------------------------------------------------------------------- */
143 #if hppa1_1_TARGET_ARCH
145 #define REG(x) __asm__("%" #x)
161 #define REG_D1 fr20 /* L & R */
162 #define REG_D2 fr21 /* L & R */
171 #define NCG_Reserved_I1 r28
172 #define NCG_Reserved_I2 r29
173 #define NCG_Reserved_F1 fr8
174 #define NCG_Reserved_F2 fr8R
175 #define NCG_Reserved_D1 fr10
176 #define NCG_Reserved_D2 fr11
180 /* -----------------------------------------------------------------------------
181 The Intel iX86 register mapping
183 Ok, we've only got 6 general purpose registers, a frame pointer and a
184 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
185 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
186 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
195 Leaving Su, SpLim, and HpLim out of the picture.
196 -------------------------------------------------------------------------- */
201 #define REG(x) __asm__("%" #x)
206 #if STOLEN_X86_REGS >= 3
210 #if STOLEN_X86_REGS >= 4
214 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
215 #define MAX_REAL_FLOAT_REG 0
216 #define MAX_REAL_DOUBLE_REG 0
220 /* -----------------------------------------------------------------------------
221 The Motorola 680x0 register mapping
223 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
224 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
225 be done through address registers; data registers are used for
226 comparison values and data.
228 Here's the register-usage picture for m68k boxes with GCC.
231 a0 & used directly by GCC \\
232 a1 & used directly by GCC \\
234 a2..a5 & callee-saved: available for STG registers \\
235 & (a5 may be special, ``global'' register for PIC?) \\
237 a6 & C-stack frame pointer \\
238 a7 & C-stack pointer \\
240 d0 & used directly by GCC \\
241 d1 & used directly by GCC \\
242 d2 & really needed for local optimisation by GCC \\
244 d3..d7 & callee-saved: available for STG registers
246 fp0 & call-clobbered \\
247 fp1 & call-clobbered \\
248 fp2..fp7 & callee-saved: available for STG registers
250 -------------------------------------------------------------------------- */
254 #define REG(x) __asm__(#x)
267 #define MAX_REAL_VANILLA_REG 2
281 /* -----------------------------------------------------------------------------
282 The DECstation (MIPS) register mapping
284 Here's at least some simple stuff about registers on a MIPS.
286 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
287 ``prize'' stolen registers. There is also a wad of callee-save
288 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
291 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
292 We can steal some, but we might have to save/restore around ccalls.
293 -------------------------------------------------------------------------- */
295 #if mipsel_TARGET_ARCH || mipseb_TARGET_ARCH
297 #define REG(x) __asm__("$" #x)
299 #define CALLER_SAVES_R1
300 #define CALLER_SAVES_R2
301 #define CALLER_SAVES_R3
302 #define CALLER_SAVES_R4
303 #define CALLER_SAVES_R5
304 #define CALLER_SAVES_R6
305 #define CALLER_SAVES_R7
306 #define CALLER_SAVES_R8
308 #define CALLER_SAVES_USER
334 #endif /* mipse[lb] */
336 /* -----------------------------------------------------------------------------
337 The PowerPC register mapping
339 0 system glue? (caller-save, volatile)
340 1 SP (callee-save, non-volatile)
341 2 RTOC (callee-save, non-volatile)
342 3-10 args/return (caller-save, volatile)
343 11,12 system glue? (caller-save, volatile)
344 13-31 (callee-save, non-volatile)
346 f0 (caller-save, volatile)
347 f1-f13 args/return (caller-save, volatile)
348 f14-f31 (callee-save, non-volatile)
350 \tr{13}--\tr{31} are wonderful callee-save registers.
351 \tr{0}--\tr{12} are caller-save registers.
353 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
355 I think we can do the Whole Business with callee-save registers only!
356 -------------------------------------------------------------------------- */
358 #if powerpc_TARGET_ARCH || rs6000_TARGET_ARCH
360 #define REG(x) __asm__(#x)
381 #define REG_SpLim r24
384 #define REG_HpLim r26
388 /* -----------------------------------------------------------------------------
389 The Sun SPARC register mapping
391 The SPARC register (window) story: Remember, within the Haskell
392 Threaded World, we essentially ``shut down'' the register-window
393 mechanism---the window doesn't move at all while in this World. It
394 *does* move, of course, if we call out to arbitrary~C...
396 The %i, %l, and %o registers (8 each) are the input, local, and
397 output registers visible in one register window. The 8 %g (global)
398 registers are visible all the time.
400 %o0..%o7 not available; can be zapped by callee
401 (%o6 is C-stack ptr; %o7 hold ret addrs)
402 %i0..%i7 available (except %i6 is used as frame ptr)
403 (and %i7 tends to have ret-addr-ish things)
405 %g0..%g4 not available; prone to stomping by division, etc.
406 %g5..%g7 not available; reserved for the OS
408 Note: %g3 is *definitely* clobbered in the builtin divide code (and
409 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
410 being the better part of valor, we also don't take %g4.
411 -------------------------------------------------------------------------- */
413 #if sparc_TARGET_ARCH
415 #define REG(x) __asm__("%" #x)
417 #define CALLER_SAVES_USER
419 #define CALLER_SAVES_F1
420 #define CALLER_SAVES_F2
421 #define CALLER_SAVES_F3
422 #define CALLER_SAVES_F4
423 #define CALLER_SAVES_D1
424 #define CALLER_SAVES_D2
449 #define NCG_Reserved_I1 g1
450 #define NCG_Reserved_I2 g2
451 #define NCG_Reserved_F1 f14
452 #define NCG_Reserved_F2 f15
453 #define NCG_Reserved_D1 f16
454 #define NCG_Reserved_D2 f18
458 /* These constants define how many stg registers are *actually* in
459 * registers: the code generator uses this information to avoid
460 * generating code to load/store registers which are really offsets
463 * Registers above these values might still be used, for instance to
464 * communicate with PrimOps and RTS functions.
467 #ifndef MAX_REAL_VANILLA_REG
468 #define MAX_REAL_VANILLA_REG 8
471 #ifndef MAX_REAL_FLOAT_REG
472 #define MAX_REAL_FLOAT_REG 4
475 #ifndef MAX_REAL_DOUBLE_REG
476 #define MAX_REAL_DOUBLE_REG 2
481 #endif /* MACHREGS_H */