[project @ 2000-08-21 15:40:14 by sewardj]
authorsewardj <unknown>
Mon, 21 Aug 2000 15:40:15 +0000 (15:40 +0000)
committersewardj <unknown>
Mon, 21 Aug 2000 15:40:15 +0000 (15:40 +0000)
commitb71148fc3dc7f89c92c144c8e2c30c3eada8a83d
tree3a823c0ffa76a4bc45ef8dce8181fc20eb45e066
parent4e477c5857d64a10fd9701da3208102cb1b2e1f4
[project @ 2000-08-21 15:40:14 by sewardj]
Make the register allocator deal properly with switch tables.
Previously, it didn't calculate the correct flow edges away from the
indirect jump (in fact it didn't reckon there were any flow edges
leaving it :) which makes a nonsense of the live variable analysis in
the branches.

A jump insn can now optionally be annotated with a list of destination
labels, and if so, the register allocator creates flow edges to all of
them.

Jump tables are now re-enabled.  They remain disabled for 4.08.1,
since we aren't fixing the problem properly on that branch.

I assume this problem wasn't exposed by the old register allocator
because of the live-range-approximation hacks used in it.  Since it
was undocumented, we'll never know.

Sparc builds will now break until I fix them.
ghc/compiler/nativeGen/AbsCStixGen.lhs
ghc/compiler/nativeGen/AsmCodeGen.lhs
ghc/compiler/nativeGen/AsmRegAlloc.lhs
ghc/compiler/nativeGen/MachCode.lhs
ghc/compiler/nativeGen/MachMisc.lhs
ghc/compiler/nativeGen/PprMach.lhs
ghc/compiler/nativeGen/RegAllocInfo.lhs
ghc/compiler/nativeGen/Stix.lhs
ghc/compiler/nativeGen/StixMacro.lhs