2 % (c) The AQUA Project, Glasgow University, 1993-1998
4 \section[MachMisc]{Description of various machine-specific things}
7 #include "nativeGen/NCG.h"
11 sizeOf, primRepToSize,
15 volatileSaves, volatileRestores,
17 targetMaxDouble, targetMaxInt, targetMinDouble, targetMinInt,
23 Instr(..), IF_ARCH_i386(Operand(..) COMMA,)
26 IF_ARCH_i386(i386_insert_ffrees COMMA,)
34 RI(..), riZero, fpRelEA, moveSp, fPair
38 #include "HsVersions.h"
39 -- #include "config.h"
41 import AbsCSyn ( MagicId(..) )
42 import AbsCUtils ( magicIdPrimRep )
43 import CLabel ( CLabel, isAsmTemp )
44 import Literal ( mkMachInt, Literal(..) )
45 import MachRegs ( stgReg, callerSaves, RegLoc(..),
48 # if sparc_TARGET_ARCH
52 import PrimRep ( PrimRep(..) )
53 import Stix ( StixTree(..), StixReg(..), CodeSegment, DestInfo(..) )
54 import Panic ( panic )
55 import GlaExts ( word2Int#, int2Word#, shiftRL#, and#, (/=#) )
56 import Outputable ( pprPanic, ppr )
57 import IOExts ( trace )
61 underscorePrefix :: Bool -- leading underscore on assembler labels?
63 #ifdef LEADING_UNDERSCORE
64 underscorePrefix = True
66 underscorePrefix = False
69 ---------------------------
70 fmtAsmLbl :: String -> String -- for formatting labels
74 {- The alpha assembler likes temporary labels to look like $L123
75 instead of L123. (Don't toss the L, because then Lf28
84 % ----------------------------------------------------------------
86 We (allegedly) put the first six C-call arguments in registers;
87 where do we start putting the rest of them?
89 eXTRA_STK_ARGS_HERE :: Int
91 = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,???)))
94 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
96 Size of a @PrimRep@, in bytes.
99 sizeOf :: PrimRep -> Integer{-in bytes-}
100 -- the result is an Integer only because it's more convenient
102 sizeOf pr = case (primRepToSize pr) of
103 IF_ARCH_alpha({B -> 1; BU -> 1; {-W -> 2; WU -> 2;-} L -> 4; {-SF -> 4;-} _ -> 8},)
104 IF_ARCH_sparc({B -> 1; BU -> 1; {-HW -> 2; HWU -> 2;-} W -> 4; {-D -> 8;-} F -> 4; DF -> 8},)
105 IF_ARCH_i386( {B -> 1; {-S -> 2;-} L -> 4; F -> 4; DF -> 8 },)
108 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
110 Now the volatile saves and restores. We add the basic guys to the
111 list of ``user'' registers provided. Note that there are more basic
112 registers on the restore list, because some are reloaded from
115 (@volatileRestores@ used only for wrapper-hungry PrimOps.)
118 volatileSaves, volatileRestores :: [MagicId] -> [StixTree]
120 save_cands = [BaseReg,Sp,Su,SpLim,Hp,HpLim]
121 restore_cands = save_cands
124 = map save ((filter callerSaves) (save_cands ++ vols))
126 save x = StAssign (magicIdPrimRep x) loc reg
128 reg = StReg (StixMagicId x)
129 loc = case stgReg x of
131 Always _ -> panic "volatileSaves"
133 volatileRestores vols
134 = map restore ((filter callerSaves) (restore_cands ++ vols))
136 restore x = StAssign (magicIdPrimRep x) reg loc
138 reg = StReg (StixMagicId x)
139 loc = case stgReg x of
141 Always _ -> panic "volatileRestores"
144 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
146 Obviously slightly weedy
147 (Note that the floating point values aren't terribly important.)
150 targetMinDouble = MachDouble (-1.7976931348623157e+308)
151 targetMaxDouble = MachDouble (1.7976931348623157e+308)
152 targetMinInt = mkMachInt (-2147483648)
153 targetMaxInt = mkMachInt 2147483647
156 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
158 This algorithm for determining the $\log_2$ of exact powers of 2 comes
159 from GCC. It requires bit manipulation primitives, and we use GHC
166 exactLog2 :: Integer -> Maybe Integer
168 = if (x <= 0 || x >= 2147483648) then
171 case (fromInteger x) of { I# x# ->
172 if (w2i ((i2w x#) `and#` (i2w (0# -# x#))) /=# x#) then
175 Just (toInteger (I# (pow2 x#)))
178 shiftr x y = shiftRL# x y
180 pow2 x# | x# ==# 1# = 0#
181 | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` 1#))
184 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
188 #if alpha_TARGET_ARCH
189 = ALWAYS -- For BI (same as BR)
190 | EQQ -- For CMP and BI (NB: "EQ" is a 1.3 Prelude name)
192 | GTT -- For BI only (NB: "GT" is a 1.3 Prelude name)
193 | LE -- For CMP and BI
194 | LTT -- For CMP and BI (NB: "LT" is a 1.3 Prelude name)
196 | NEVER -- For BI (null instruction)
197 | ULE -- For CMP only
198 | ULT -- For CMP only
201 = ALWAYS -- What's really used? ToDo
215 #if sparc_TARGET_ARCH
216 = ALWAYS -- What's really used? ToDo
237 #if alpha_TARGET_ARCH
240 -- | W -- word (2 bytes): UNUSED
242 | L -- longword (4 bytes)
243 | Q -- quadword (8 bytes)
244 -- | FF -- VAX F-style floating pt: UNUSED
245 -- | GF -- VAX G-style floating pt: UNUSED
246 -- | DF -- VAX D-style floating pt: UNUSED
247 -- | SF -- IEEE single-precision floating pt: UNUSED
248 | TF -- IEEE double-precision floating pt
252 -- | HB -- higher byte **UNUSED**
255 | F -- IEEE single-precision floating pt
256 | DF -- IEEE single-precision floating pt
257 | F80 -- Intel 80-bit internal FP format; only used for spilling
259 #if sparc_TARGET_ARCH
261 | BU -- byte (unsigned)
262 -- | HW -- halfword, 2 bytes (signed): UNUSED
263 -- | HWU -- halfword, 2 bytes (unsigned): UNUSED
265 -- | D -- doubleword, 8 bytes: UNUSED
266 | F -- IEEE single-precision floating pt
267 | DF -- IEEE single-precision floating pt
270 primRepToSize :: PrimRep -> Size
272 primRepToSize PtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
273 primRepToSize CodePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
274 primRepToSize DataPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
275 primRepToSize RetRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
276 primRepToSize CostCentreRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
277 primRepToSize CharRep = IF_ARCH_alpha( L, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
278 primRepToSize Int8Rep = IF_ARCH_alpha( B, IF_ARCH_i386( B, IF_ARCH_sparc( B ,)))
279 primRepToSize IntRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
280 primRepToSize WordRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
281 primRepToSize AddrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
282 primRepToSize FloatRep = IF_ARCH_alpha( TF, IF_ARCH_i386( F, IF_ARCH_sparc( F ,)))
283 primRepToSize DoubleRep = IF_ARCH_alpha( TF, IF_ARCH_i386( DF,IF_ARCH_sparc( DF,)))
284 primRepToSize ArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
285 primRepToSize ByteArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
286 primRepToSize WeakPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
287 primRepToSize ForeignObjRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
288 primRepToSize BCORep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
289 primRepToSize StablePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
290 primRepToSize ThreadIdRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
291 -- SUP: Wrong!!! Only for testing the rest of the NCG
292 primRepToSize Word64Rep = trace "primRepToSize: Word64Rep not handled" B
293 primRepToSize Int64Rep = trace "primRepToSize: Int64Rep not handled" B
296 %************************************************************************
298 \subsection{Machine's assembly language}
300 %************************************************************************
302 We have a few common ``instructions'' (nearly all the pseudo-ops) but
303 mostly all of @Instr@ is machine-specific.
307 = COMMENT FAST_STRING -- comment pseudo-op
308 | SEGMENT CodeSegment -- {data,text} segment pseudo-op
309 | LABEL CLabel -- global label pseudo-op
310 | ASCII Bool -- True <=> needs backslash conversion
311 String -- the literal string
314 | DELTA Int -- specify current stack offset for
315 -- benefit of subsequent passes
319 #if alpha_TARGET_ARCH
321 -- data Instr continues...
325 | LD Size Reg MachRegsAddr -- size, dst, src
326 | LDA Reg MachRegsAddr -- dst, src
327 | LDAH Reg MachRegsAddr -- dst, src
328 | LDGP Reg MachRegsAddr -- dst, src
329 | LDI Size Reg Imm -- size, dst, src
330 | ST Size Reg MachRegsAddr -- size, src, dst
335 | ABS Size RI Reg -- size, src, dst
336 | NEG Size Bool RI Reg -- size, overflow, src, dst
337 | ADD Size Bool Reg RI Reg -- size, overflow, src, src, dst
338 | SADD Size Size Reg RI Reg -- size, scale, src, src, dst
339 | SUB Size Bool Reg RI Reg -- size, overflow, src, src, dst
340 | SSUB Size Size Reg RI Reg -- size, scale, src, src, dst
341 | MUL Size Bool Reg RI Reg -- size, overflow, src, src, dst
342 | DIV Size Bool Reg RI Reg -- size, unsigned, src, src, dst
343 | REM Size Bool Reg RI Reg -- size, unsigned, src, src, dst
345 -- Simple bit-twiddling.
365 | CMP Cond Reg RI Reg
372 | FADD Size Reg Reg Reg
373 | FDIV Size Reg Reg Reg
374 | FMUL Size Reg Reg Reg
375 | FSUB Size Reg Reg Reg
376 | CVTxy Size Size Reg Reg
377 | FCMP Size Cond Reg Reg Reg
385 | JMP Reg MachRegsAddr Int
387 | JSR Reg MachRegsAddr Int
389 -- Alpha-specific pseudo-ops.
398 #endif {- alpha_TARGET_ARCH -}
401 Intel, in their infinite wisdom, selected a stack model for floating
402 point registers on x86. That might have made sense back in 1979 --
403 nowadays we can see it for the nonsense it really is. A stack model
404 fits poorly with the existing nativeGen infrastructure, which assumes
405 flat integer and FP register sets. Prior to this commit, nativeGen
406 could not generate correct x86 FP code -- to do so would have meant
407 somehow working the register-stack paradigm into the register
408 allocator and spiller, which sounds very difficult.
410 We have decided to cheat, and go for a simple fix which requires no
411 infrastructure modifications, at the expense of generating ropey but
412 correct FP code. All notions of the x86 FP stack and its insns have
413 been removed. Instead, we pretend (to the instruction selector and
414 register allocator) that x86 has six floating point registers, %fake0
415 .. %fake5, which can be used in the usual flat manner. We further
416 claim that x86 has floating point instructions very similar to SPARC
417 and Alpha, that is, a simple 3-operand register-register arrangement.
418 Code generation and register allocation proceed on this basis.
420 When we come to print out the final assembly, our convenient fiction
421 is converted to dismal reality. Each fake instruction is
422 independently converted to a series of real x86 instructions.
423 %fake0 .. %fake5 are mapped to %st(0) .. %st(5). To do reg-reg
424 arithmetic operations, the two operands are pushed onto the top of the
425 FP stack, the operation done, and the result copied back into the
426 relevant register. There are only six %fake registers because 2 are
427 needed for the translation, and x86 has 8 in total.
429 The translation is inefficient but is simple and it works. A cleverer
430 translation would handle a sequence of insns, simulating the FP stack
431 contents, would not impose a fixed mapping from %fake to %st regs, and
432 hopefully could avoid most of the redundant reg-reg moves of the
435 We might as well make use of whatever unique FP facilities Intel have
436 chosen to bless us with (let's not be churlish, after all).
437 Hence GLDZ and GLD1. Bwahahahahahahaha!
442 -- data Instr continues...
446 | MOV Size Operand Operand
447 | MOVZxL Size Operand Operand -- size is the size of operand 1
448 | MOVSxL Size Operand Operand -- size is the size of operand 1
450 -- Load effective address (also a very useful three-operand add instruction :-)
452 | LEA Size Operand Operand
456 | ADD Size Operand Operand
457 | SUB Size Operand Operand
459 -- Multiplication (signed and unsigned), Division (signed and unsigned),
460 -- result in %eax, %edx.
462 | IMUL Size Operand Operand
465 -- Simple bit-twiddling.
467 | AND Size Operand Operand
468 | OR Size Operand Operand
469 | XOR Size Operand Operand
471 | NEGI Size Operand -- NEG instruction (name clash with Cond)
472 | SHL Size Imm Operand -- Only immediate shifts allowed
473 | SAR Size Imm Operand -- Only immediate shifts allowed
474 | SHR Size Imm Operand -- Only immediate shifts allowed
475 | BT Size Imm Operand
480 -- Note that we cheat by treating G{ABS,MOV,NEG} of doubles
481 -- as single instructions right up until we spit them out.
483 -- all the 3-operand fake fp insns are src1 src2 dst
484 -- and furthermore are constrained to be fp regs only.
485 -- IMPORTANT: keep is_G_insn up to date with any changes here
486 | GMOV Reg Reg -- src(fpreg), dst(fpreg)
487 | GLD Size MachRegsAddr Reg -- src, dst(fpreg)
488 | GST Size Reg MachRegsAddr -- src(fpreg), dst
490 | GLDZ Reg -- dst(fpreg)
491 | GLD1 Reg -- dst(fpreg)
493 | GFTOD Reg Reg -- src(fpreg), dst(fpreg)
494 | GFTOI Reg Reg -- src(fpreg), dst(intreg)
496 | GDTOF Reg Reg -- src(fpreg), dst(fpreg)
497 | GDTOI Reg Reg -- src(fpreg), dst(intreg)
499 | GITOF Reg Reg -- src(intreg), dst(fpreg)
500 | GITOD Reg Reg -- src(intreg), dst(fpreg)
502 | GADD Size Reg Reg Reg -- src1, src2, dst
503 | GDIV Size Reg Reg Reg -- src1, src2, dst
504 | GSUB Size Reg Reg Reg -- src1, src2, dst
505 | GMUL Size Reg Reg Reg -- src1, src2, dst
507 | GCMP Size Reg Reg -- src1, src2
509 | GABS Size Reg Reg -- src, dst
510 | GNEG Size Reg Reg -- src, dst
511 | GSQRT Size Reg Reg -- src, dst
512 | GSIN Size Reg Reg -- src, dst
513 | GCOS Size Reg Reg -- src, dst
514 | GTAN Size Reg Reg -- src, dst
516 | GFREE -- do ffree on all x86 regs; an ugly hack
519 | TEST Size Operand Operand
520 | CMP Size Operand Operand
532 | JMP DestInfo Operand -- possible dests, target
533 | JXX Cond CLabel -- target
538 | CLTD -- sign extend %eax into %edx:%eax
541 = OpReg Reg -- register
542 | OpImm Imm -- immediate value
543 | OpAddr MachRegsAddr -- memory reference
546 i386_insert_ffrees :: [Instr] -> [Instr]
547 i386_insert_ffrees insns
548 | any is_G_instr insns
549 = concatMap ffree_before_nonlocal_transfers insns
553 ffree_before_nonlocal_transfers insn
555 CALL _ -> [GFREE, insn]
556 -- Jumps to immediate labels are local
557 JMP _ (OpImm (ImmCLbl clbl)) | isAsmTemp clbl -> [insn]
558 -- If a jump mentions dests, it is a local jump thru
560 JMP (DestInfo _) _ -> [insn]
561 JMP _ _ -> [GFREE, insn]
565 -- if you ever add a new FP insn to the fake x86 FP insn set,
566 -- you must update this too
567 is_G_instr :: Instr -> Bool
570 GMOV _ _ -> True; GLD _ _ _ -> True; GST _ _ _ -> True;
571 GLDZ _ -> True; GLD1 _ -> True;
572 GFTOD _ _ -> True; GFTOI _ _ -> True;
573 GDTOF _ _ -> True; GDTOI _ _ -> True;
574 GITOF _ _ -> True; GITOD _ _ -> True;
575 GADD _ _ _ _ -> True; GDIV _ _ _ _ -> True
576 GSUB _ _ _ _ -> True; GMUL _ _ _ _ -> True
577 GCMP _ _ _ -> True; GABS _ _ _ -> True
578 GNEG _ _ _ -> True; GSQRT _ _ _ -> True
579 GSIN _ _ _ -> True; GCOS _ _ _ -> True; GTAN _ _ _ -> True;
580 GFREE -> panic "is_G_instr: GFREE (!)"
583 #endif {- i386_TARGET_ARCH -}
587 #if sparc_TARGET_ARCH
589 -- data Instr continues...
593 | LD Size MachRegsAddr Reg -- size, src, dst
594 | ST Size Reg MachRegsAddr -- size, src, dst
598 | ADD Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
599 | SUB Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
601 -- Simple bit-twiddling.
603 | AND Bool Reg RI Reg -- cc?, src1, src2, dst
604 | ANDN Bool Reg RI Reg -- cc?, src1, src2, dst
605 | OR Bool Reg RI Reg -- cc?, src1, src2, dst
606 | ORN Bool Reg RI Reg -- cc?, src1, src2, dst
607 | XOR Bool Reg RI Reg -- cc?, src1, src2, dst
608 | XNOR Bool Reg RI Reg -- cc?, src1, src2, dst
609 | SLL Reg RI Reg -- src1, src2, dst
610 | SRL Reg RI Reg -- src1, src2, dst
611 | SRA Reg RI Reg -- src1, src2, dst
612 | SETHI Imm Reg -- src, dst
613 | NOP -- Really SETHI 0, %g0, but worth an alias
617 -- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
618 -- right up until we spit them out.
620 | FABS Size Reg Reg -- src dst
621 | FADD Size Reg Reg Reg -- src1, src2, dst
622 | FCMP Bool Size Reg Reg -- exception?, src1, src2, dst
623 | FDIV Size Reg Reg Reg -- src1, src2, dst
624 | FMOV Size Reg Reg -- src, dst
625 | FMUL Size Reg Reg Reg -- src1, src2, dst
626 | FNEG Size Reg Reg -- src, dst
627 | FSQRT Size Reg Reg -- src, dst
628 | FSUB Size Reg Reg Reg -- src1, src2, dst
629 | FxTOy Size Size Reg Reg -- src, dst
633 | BI Cond Bool Imm -- cond, annul?, target
634 | BF Cond Bool Imm -- cond, annul?, target
636 | JMP MachRegsAddr -- target
637 | CALL Imm Int Bool -- target, args, terminal
644 riZero (RIImm (ImmInt 0)) = True
645 riZero (RIImm (ImmInteger 0)) = True
646 riZero (RIReg (RealReg 0)) = True
649 -- Calculate the effective address which would be used by the
650 -- corresponding fpRel sequence. fpRel is in MachRegs.lhs,
651 -- alas -- can't have fpRelEA here because of module dependencies.
652 fpRelEA :: Int -> Reg -> Instr
654 = ADD False False fp (RIImm (ImmInt (n * BYTES_PER_WORD))) dst
656 -- Code to shift the stack pointer by n words.
657 moveSp :: Int -> Instr
659 = ADD False False sp (RIImm (ImmInt (n * BYTES_PER_WORD))) sp
661 -- Produce the second-half-of-a-double register given the first half.
663 fPair (RealReg n) | n >= 32 && n `mod` 2 == 0 = RealReg (n+1)
664 fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
665 #endif {- sparc_TARGET_ARCH -}