SPARC NCG: Fix 64 bit addition, carry bit wasn't getting set.

diff --git a/compiler/nativeGen/SPARC/CodeGen/Gen64.hs b/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
index d9ada98..f620e72 100644 (file)
--- a/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
@@ -15,6 +15,7 @@ import SPARC.Regs
 import SPARC.AddrMode
 import SPARC.Imm
 import SPARC.Instr
 import SPARC.AddrMode
 import SPARC.Imm
 import SPARC.Instr

+import SPARC.Ppr()

 import NCGMonad
 import Instruction
 import Size
 import NCGMonad
 import Instruction
 import Size

@@ -35,15 +36,26 @@ assignMem_I64Code addrTree valueTree
  = do
      ChildCode64 vcode rlo     <- iselExpr64 valueTree  
 
  = do
      ChildCode64 vcode rlo     <- iselExpr64 valueTree  
 

-     (src, code) <- getSomeReg addrTree
+     (src, acode) <- getSomeReg addrTree

      let 
          rhi = getHiVRegFromLo rlo
  
          -- Big-endian store
          mov_hi = ST II32 rhi (AddrRegImm src (ImmInt 0))
          mov_lo = ST II32 rlo (AddrRegImm src (ImmInt 4))
      let 
          rhi = getHiVRegFromLo rlo
  
          -- Big-endian store
          mov_hi = ST II32 rhi (AddrRegImm src (ImmInt 0))
          mov_lo = ST II32 rlo (AddrRegImm src (ImmInt 4))

+         
+        code   = vcode `appOL` acode `snocOL` mov_hi `snocOL` mov_lo

 
 

-     return (vcode `appOL` code `snocOL` mov_hi `snocOL` mov_lo)
+{-     pprTrace "assignMem_I64Code" 
+       (vcat   [ text "addrTree:  " <+> ppr addrTree
+               , text "valueTree: " <+> ppr valueTree
+               , text "vcode:"
+               , vcat $ map ppr $ fromOL vcode 
+               , text ""
+               , text "acode:"
+               , vcat $ map ppr $ fromOL acode ])
+       $ -}
+     return code

 
 
 -- | Code to assign a 64 bit value to a register.
 
 
 -- | Code to assign a 64 bit value to a register.

@@ -113,17 +125,18 @@ iselExpr64 (CmmLoad addrTree ty)
 
 -- Add a literal to a 64 bit integer
 iselExpr64 (CmmMachOp (MO_Add _) [e1, CmmLit (CmmInt i _)]) 
 
 -- Add a literal to a 64 bit integer
 iselExpr64 (CmmMachOp (MO_Add _) [e1, CmmLit (CmmInt i _)]) 

- = do  ChildCode64 _ r1_lo <- iselExpr64 e1
+ = do  ChildCode64 code1 r1_lo <- iselExpr64 e1

        let r1_hi       = getHiVRegFromLo r1_lo
        
        r_dst_lo        <- getNewRegNat II32
        let r_dst_hi    =  getHiVRegFromLo r_dst_lo 
        
        let r1_hi       = getHiVRegFromLo r1_lo
        
        r_dst_lo        <- getNewRegNat II32
        let r_dst_hi    =  getHiVRegFromLo r_dst_lo 
        

-       return  $ ChildCode64
-                       ( toOL
-                       [ ADD False False r1_lo (RIImm (ImmInteger i)) r_dst_lo
-                       , ADD True  False r1_hi (RIReg g0)         r_dst_hi ])
-                       r_dst_lo
+       let code =      code1
+               `appOL` toOL
+                       [ ADD False True  r1_lo (RIImm (ImmInteger i)) r_dst_lo
+                       , ADD True  False r1_hi (RIReg g0)         r_dst_hi ]
+                       
+       return  $ ChildCode64 code r_dst_lo

 
 
 -- Addition of II64
 
 
 -- Addition of II64

@@ -140,7 +153,7 @@ iselExpr64 (CmmMachOp (MO_Add _) [e1, e2])
        let code =      code1
                `appOL` code2
                `appOL` toOL
        let code =      code1
                `appOL` code2
                `appOL` toOL

-                       [ ADD False False r1_lo (RIReg r2_lo) r_dst_lo
+                       [ ADD False True  r1_lo (RIReg r2_lo) r_dst_lo

                        , ADD True  False r1_hi (RIReg r2_hi) r_dst_hi ]
        
        return  $ ChildCode64 code r_dst_lo
                        , ADD True  False r1_hi (RIReg r2_hi) r_dst_hi ]
        
        return  $ ChildCode64 code r_dst_lo

diff --git a/compiler/nativeGen/SPARC/Instr.hs b/compiler/nativeGen/SPARC/Instr.hs
index b21f947..3006782 100644 (file)
--- a/compiler/nativeGen/SPARC/Instr.hs
+++ b/compiler/nativeGen/SPARC/Instr.hs
@@ -126,6 +126,11 @@ data Instr
        | ST            Size Reg AddrMode               -- size, src, dst
 
        -- Int Arithmetic.
        | ST            Size Reg AddrMode               -- size, src, dst
 
        -- Int Arithmetic.

+       --      x:   add/sub with carry bit. 
+       --              In SPARC V9 addx and friends were renamed addc. 
+       --
+       --      cc:  modify condition codes
+       -- 

        | ADD           Bool Bool Reg RI Reg            -- x?, cc?, src1, src2, dst
        | SUB           Bool Bool Reg RI Reg            -- x?, cc?, src1, src2, dst
 
        | ADD           Bool Bool Reg RI Reg            -- x?, cc?, src1, src2, dst
        | SUB           Bool Bool Reg RI Reg            -- x?, cc?, src1, src2, dst