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update Sparc store/load barrier (#3019), and fix comments
author
Simon Marlow
<marlowsd@gmail.com>
Thu, 12 Feb 2009 09:23:40 +0000
(09:23 +0000)
committer
Simon Marlow
<marlowsd@gmail.com>
Thu, 12 Feb 2009 09:23:40 +0000
(09:23 +0000)
includes/SMP.h
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diff --git
a/includes/SMP.h
b/includes/SMP.h
index
2cc3fb2
..
ac98feb
100644
(file)
--- a/
includes/SMP.h
+++ b/
includes/SMP.h
@@
-179,7
+179,7
@@
write_barrier(void) {
#elif powerpc_HOST_ARCH
__asm__ __volatile__ ("lwsync" : : : "memory");
#elif sparc_HOST_ARCH
#elif powerpc_HOST_ARCH
__asm__ __volatile__ ("lwsync" : : : "memory");
#elif sparc_HOST_ARCH
- /* Sparc in TSO mode does not require write/write barriers. */
+ /* Sparc in TSO mode does not require store/store barriers. */
__asm__ __volatile__ ("" : : : "memory");
#elif !defined(WITHSMP)
return;
__asm__ __volatile__ ("" : : : "memory");
#elif !defined(WITHSMP)
return;
@@
-197,8
+197,7
@@
store_load_barrier(void) {
#elif powerpc_HOST_ARCH
__asm__ __volatile__ ("sync" : : : "memory");
#elif sparc_HOST_ARCH
#elif powerpc_HOST_ARCH
__asm__ __volatile__ ("sync" : : : "memory");
#elif sparc_HOST_ARCH
- /* Sparc in TSO mode does not require store/load barriers. */
- __asm__ __volatile__ ("membar" : : : "memory");
+ __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
#elif !defined(WITHSMP)
return;
#else
#elif !defined(WITHSMP)
return;
#else