-- %l6(r22) - %l7(r23) are allocable --------------
-- %i0(r24) - %i5(r29)
- -- are STG regs Sp, Base, SpLim, Hp, HpLim, R6
+ -- are STG regs Sp, Base, SpLim, Hp, R6
24 -> fastBool False
25 -> fastBool False
26 -> fastBool False
27 -> fastBool False
- 28 -> fastBool False
+
+ -- %i5(r28) is allocable --------------------------
+
29 -> fastBool False
-- %i6(r30)
Sp -> Just (RealReg 24) -- %i0
SpLim -> Just (RealReg 26) -- %i2
Hp -> Just (RealReg 27) -- %i3
- HpLim -> Just (RealReg 28) -- %i4
BaseReg -> Just (RealReg 25) -- %i1
/* -----------------------------------------------------------------------------
The Sun SPARC register mapping
+ !! IMPORTANT: if you change this register mapping you must also update
+ compiler/nativeGen/SPARC/Regs.hs. That file handles the
+ mapping for the NCG. This one only affects via-c code.
+
The SPARC register (window) story: Remember, within the Haskell
Threaded World, we essentially ``shut down'' the register-window
mechanism---the window doesn't move at all while in this World. It
%i1 Base
%i2 SpLim
%i3 Hp
+ %i4 alloc
%i5 R6
%i6 C frame ptr
%i7 C ret addr
-
The paired nature of the floating point registers causes complications for
the native code generator. For convenience, we pretend that the first 22
fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are