fix for gcc 3.3 preprocessor: no layout, end-of-line comments or complex
Haskell comments in macro arguments.
please merge to STABLE
fmtAsmLbl :: String -> String -- for formatting labels
fmtAsmLbl s
fmtAsmLbl :: String -> String -- for formatting labels
fmtAsmLbl s
{- The alpha assembler likes temporary labels to look like $L123
instead of L123. (Don't toss the L, because then Lf28
turns into $f28.)
-}
{- The alpha assembler likes temporary labels to look like $L123
instead of L123. (Don't toss the L, because then Lf28
turns into $f28.)
-}
'$' : s
,{-otherwise-}
'.':'L':s
'$' : s
,{-otherwise-}
'.':'L':s
{-I386: spill above stack pointer leaving 3 words/spill-}
,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
{-I386: spill above stack pointer leaving 3 words/spill-}
,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
- in case regClass vreg of
- RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w))
- _ -> GST F80 dyn (spRel off_w) -- RcFloat/RcDouble
+ in case regClass vreg of {
+ RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w));
+ _ -> GST F80 dyn (spRel off_w)} {- RcFloat/RcDouble -}
{-SPARC: spill below frame pointer leaving 2 words/spill-}
,IF_ARCH_sparc(
{-SPARC: spill below frame pointer leaving 2 words/spill-}
,IF_ARCH_sparc(
- let off_w = 1 + (off `div` 4)
- sz = case regClass vreg of
- RcInteger -> W
- RcFloat -> F
- RcDouble -> DF
+ let{off_w = 1 + (off `div` 4);
+ sz = case regClass vreg of {
+ RcInteger -> W;
+ RcFloat -> F;
+ RcDouble -> DF}}
in ST sz dyn (fpRel (- off_w))
,IF_ARCH_powerpc(
in ST sz dyn (fpRel (- off_w))
,IF_ARCH_powerpc(
- let sz = case regClass vreg of
- RcInteger -> W
- RcFloat -> F
- RcDouble -> DF
+ let{sz = case regClass vreg of {
+ RcInteger -> W;
+ RcFloat -> F;
+ RcDouble -> DF}}
in ST sz dyn (AddrRegImm sp (ImmInt (off-delta)))
,))))
in ST sz dyn (AddrRegImm sp (ImmInt (off-delta)))
,))))
IF_ARCH_alpha( LD sz dyn (spRel (- (off `div` 8)))
,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
IF_ARCH_alpha( LD sz dyn (spRel (- (off `div` 8)))
,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
- in case regClass vreg of
- RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn)
- _ -> GLD F80 (spRel off_w) dyn -- RcFloat/RcDouble
+ in case regClass vreg of {
+ RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn);
+ _ -> GLD F80 (spRel off_w) dyn} {- RcFloat/RcDouble -}
- let off_w = 1 + (off `div` 4)
- sz = case regClass vreg of
- RcInteger -> W
- RcFloat -> F
- RcDouble -> DF
+ let{off_w = 1 + (off `div` 4);
+ sz = case regClass vreg of {
+ RcInteger -> W;
+ RcFloat -> F;
+ RcDouble -> DF}}
in LD sz (fpRel (- off_w)) dyn
,IF_ARCH_powerpc(
in LD sz (fpRel (- off_w)) dyn
,IF_ARCH_powerpc(
- let sz = case regClass vreg of
- RcInteger -> W
- RcFloat -> F
- RcDouble -> DF
+ let{sz = case regClass vreg of {
+ RcInteger -> W;
+ RcFloat -> F;
+ RcDouble -> DF}}
in LD sz dyn (AddrRegImm sp (ImmInt (off-delta)))
,))))
\end{code}
in LD sz dyn (AddrRegImm sp (ImmInt (off-delta)))
,))))
\end{code}