\r
ISR(SIG_FPGA_INTERRUPT15) { \r
interrupt_count++;\r
- fpga_interrupts(1);\r
+ //fpga_interrupts(1);\r
sei();\r
}\r
\r
}\r
\r
int readFPGA() {\r
- fpga_interrupts(0);\r
int ret = FISUA;\r
- fpga_interrupts(1);\r
+ //fpga_interrupts(1);\r
return ret;\r
}\r
\r
cts(1);\r
\r
int x=0, y=0, z=0;\r
+ int flag=0;\r
for(;;) {\r
int i, d=0;\r
int r = recv();\r
send('I');\r
send('T');\r
send('S');\r
- PORTE |= (1<<3);\r
+ fpga_interrupts(0);\r
+ if (flag) {PORTE |= (1<<5);}\r
break;\r
\r
case 1:\r
break;\r
\r
case 2:\r
+ flag=1;\r
send(readFPGA());\r
break;\r
-\r
+ /*\r
case 3: {\r
int32_t local_interrupt_count = interrupt_count;\r
interrupt_count = 0;\r
send((local_interrupt_count >> 0) & 0xff);\r
break;\r
}\r
-\r
+ */\r
/*\r
case 3:\r
//init_timer();\r