checkpoint

[slipway.git] / src / edu / berkeley / slipway / FtdiBoardSlave.c

diff --git a/src/edu/berkeley/slipway/FtdiBoardSlave.c b/src/edu/berkeley/slipway/FtdiBoardSlave.c
index e9aba2e..a49a85c 100644 (file)
--- a/src/edu/berkeley/slipway/FtdiBoardSlave.c
+++ b/src/edu/berkeley/slipway/FtdiBoardSlave.c
@@ -13,6 +13,8 @@
 #include <avr/io.h>\r
 #include <avr/interrupt.h>\r
 \r
+volatile int32_t upper = 0;\r
+\r
 int err = 0;\r
 \r
 void initUART0(unsigned int baudRate, unsigned int doubleRate) {\r
@@ -70,15 +72,19 @@ inline int write_nearlyFull() {
   return (write_buf_tail-write_buf_head) > (BUFSIZE/2);\r
 }\r
 \r
+int32_t timer = 0;\r
+\r
 inline char recv() {\r
   int q;\r
   char ret;\r
+\r
+  PORTE |=  (1<<3);\r
   while(read_empty()) cts(1);\r
+  PORTE &= ~(1<<3);\r
+\r
   ret = read_buf[read_buf_head];\r
   read_buf_head = inc(read_buf_head);\r
   if (!read_nearlyFull()) cts(1);\r
-  if (PORTE & (1<<3)) PORTE &= ~(1<<3);\r
-  else                PORTE |=  (1<<3);\r
   return ret;\r
 }\r
 \r
@@ -96,11 +102,11 @@ ISR(SIG_UART0_DATA) {
 }\r
 \r
 void send(char c) {\r
+  PORTE |=  (1<<2);\r
   while (write_full());\r
+  PORTE &= ~(1<<2);\r
   write_buf[write_buf_tail] = c;\r
   write_buf_tail = inc(write_buf_tail);\r
-  if (PORTE & (1<<2)) PORTE &= ~(1<<2);\r
-  else                PORTE |=  (1<<2);\r
   UCSR0B |= (1 << UDRIE0);\r
 }\r
 \r
@@ -131,12 +137,35 @@ ISR(SIG_FPGA_INTERRUPT0) {
   sei();\r
 }\r
 \r
-void die() { cli(); PORTE|=(1<<5); _delay_ms(2000); while(1) { } }\r
+volatile int dead = 0;\r
+\r
+ISR(SIG_OVERFLOW1) { \r
+  upper = upper + 1;\r
+\r
+  if (!dead) {\r
+    if (PORTE & (1<<5)) PORTE &= ~(1<<5);\r
+    else                PORTE |=  (1<<5);\r
+  }\r
+\r
+  TCNT1 = 0;\r
+  sei();\r
+}\r
+\r
+//void die() { dead = 1; cli(); PORTE|=(1<<5); _delay_ms(2000); while(1) { } }\r
+\r
+void die(int two, int three, int five) {\r
+  dead = 1;\r
+  PORTE &~ ((1<<2) | (1<<3) | (1<<5));\r
+  if (two) PORTE |= (1<<2);\r
+  if (three) PORTE |= (1<<3);\r
+  if (five) PORTE |= (1<<5);\r
+  while(1) { }\r
+}\r
 \r
 ISR(SIG_UART0_RECV) {\r
-  if (UCSR0A & (1 << FE0))    err = 201;//{ portd(2,0); portd(3,1); die(); }  // framing error, lock up with LED=01\r
-  if ((UCSR0A & (1 << OR0)))  err = 202;//{ portd(2,1); portd(3,0); die(); }  // overflow; lock up with LED=10\r
-  if (read_full())            err = 203;//{ portd(2,1); portd(3,1); die(); }  // buffer overrun\r
+  if (UCSR0A & (1 << FE0))   die(0, 0, 1);\r
+  if ((UCSR0A & (1 << OR0))) die(0, 1, 1);\r
+  if (read_full()) die(1, 0, 1);\r
 \r
   read_buf[read_buf_tail] = UDR0;\r
   read_buf_tail = inc(read_buf_tail);\r
@@ -163,16 +192,23 @@ int main() {
   DDRE  = (1<<7) | (1<<5) | (1<<3) | (1<<2);\r
   PORTE = 0;\r
 \r
+  PORTE |=  (1<<5);\r
+\r
   read_buf_head = 0;\r
   read_buf_tail = 0;\r
   write_buf_head = 0;\r
   write_buf_tail = 0;\r
-  initUART0(0, 0);  //for slow board\r
+  initUART0(1, 0);  //for slow board\r
 \r
   EIMF = 0xFF;\r
   SREG = INT0;\r
   sei();\r
 \r
+  TCNT1 = 0;\r
+  TIFR&=~(1<<TOV1);\r
+  TIMSK|=(1<<TOIE1);\r
+  TCCR1B = 3;\r
+\r
   cts(0);\r
   cts(1);\r
 \r
@@ -188,8 +224,8 @@ int main() {
         send('I');\r
         send('T');\r
         send('S');\r
-        fpga_interrupts(0);\r
-        if (flag) {PORTE |=  (1<<5);}\r
+        fpga_interrupts(1);\r
+        if (flag) die(1, 1, 1);\r
         break;\r
 \r
       case 1:\r
@@ -212,6 +248,19 @@ int main() {
         send((local_interrupt_count >> 16) & 0xff);\r
         send((local_interrupt_count >>  8) & 0xff);\r
         send((local_interrupt_count >>  0) & 0xff);\r
+ \r
+        int32_t local_timer = TCNT1;\r
+        int32_t local_upper = upper;\r
+        TCCR1B = 0;\r
+        TIFR&=~(1<<TOV1);\r
+        TIMSK|=(1<<TOIE1);\r
+        upper = 0;\r
+        TCNT1 = 0;\r
+        TCCR1B = 3;\r
+        send((local_upper >>  8) & 0xff);\r
+        send((local_upper >>  0) & 0xff);\r
+        send((local_timer >>  8) & 0xff);\r
+        send((local_timer >>  0) & 0xff);\r
         break;\r
       }\r
 \r