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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
71 & \color{red} Updated diagram in section 3 to put dispatch path near MSB\\
72 & \color{red} Changed DP[37:25] to DP[37:27]\\
73 & \color{red} Added note on page 4 regarding previous\\
75 & Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\
76 & Clarify what ``{\tt X-Extended}'' means \\
77 & Change C-bit source selector from {\tt Di} to {\tt Dc} \\
79 & Distinguish {\tt Z}-flag from OLC=0\\
80 & Add {\tt flush} instruction\\
81 & Change {\t I} bit from ``Interruptable'' to ``Immune''\\
83 & Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
85 & Note that decision to requeue is based on value of OLC {\it before} execution\\
86 & Note that decision to open the hatch is based on value of {\tt OS} bit\\
88 & Added {\tt OLC=0} predicate \\
89 & Eliminated {\tt TAPL} (made possible by previous change) \\
90 & Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
92 & Fixed a few typos \\
93 & Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
94 & Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
96 & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
97 & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
99 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
100 & Reworked encoding of {\tt set} instruction \\
103 & Factored in Russell Kao's comments (thanks!)\\
104 & Added mechanism for setting C-flag from fabric even on outboxes\\
106 %& Made {\tt OLC} test a predicate-controlled condition\\
107 %& Rewrote ``on deck'' section \\
108 %& Added ``{\tt unset}'' value for {\tt ILC}\\
109 %& Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
112 %& added comment about address-to-path ship \\
113 %& changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
114 %& changed the order of instructions in the encoding map \\
116 %& added epilogue fifo to diagrams \\
117 %& indicated that a token sent to the instruction port is treated as a torpedo \\
119 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
120 %& replaced {\tt literal} with {\tt shift} instruction \\
122 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
123 %& Removed ability to manually set the {\tt C} flag \\
124 %& Expanded predicate field to three bits \\
125 %& New literals scheme (via shifting) \\
126 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
127 %& Added summary of instruction encodings on last page \\
129 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
131 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
132 %& update table 3.1.2 \\
133 %& rename {\tt S} flag to {\tt C} \\
134 %& noted that {\tt setFlags} can be used as {\tt nop} \\
136 %& removed the {\tt L} flag (epilogues can now do this) \\
137 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
138 %& renamed {\tt data} instruction to {\tt literal} \\
139 %& renamed {\tt send} instruction to {\tt move} \\
141 %& added ``if its predicate is true'' to repeat count \\
142 %& added note that red wires do not contact ships \\
143 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
144 %& removed black dot from diagrams \\
145 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
146 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
147 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
148 %& added section ``Torpedo Details'' \\
149 %& removed {\tt torpedo} instruction \\
152 %& renamed loop+repeat to outer+inner (not in red) \\
153 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
154 %& rewrote ``inner and outer loops'' section \\
155 %& updated all diagrams \\
158 %& Moved address bits to the LSB-side of a 37-bit instruction \\
159 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
160 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
161 %& Created the {\tt Hold} field \\
162 %& Changed how ReLooping works \\
163 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
170 \epsfig{file=all,height=1.5in}
171 \epsfig{file=overview-new,height=1.5in}
176 \section{Overview of Fleet}
178 A Fleet processor is organized around a {\it switch fabric}, which is
179 a packet-switched network with reliable in-order delivery. The switch
180 fabric is used to carry data between different functional units,
181 called {\it ships}. Each ship is connected to the switch fabric by
182 one or more programmable elements known as {\it docks}.
184 A {\it path} specifies a route through the switch fabric from a
185 particular {\it source} to a particular {\it destination}. The
186 combination of a path and a single word to be delivered is called a
187 {\it packet}. The switch fabric carries packets from their sources to
188 their destinations. Each dock has two destinations: one for {\it
189 instructions} and one for {\it data}. A Fleet is programmed by
190 depositing instruction packets into the switch fabric with paths that
191 will lead them to instruction destinations of the docks at which they
194 When a packet arrives at the instruction destination of a dock, it is
195 enqueued for execution. Before the instruction executes, it may cause
196 the dock to wait for a packet to arrive at the dock's data destination
197 or for a value to be presented by the ship. When an instruction
198 executes it may consume this data and may present a data value to the
199 ship or transmit a packet.
201 When an instruction sends a packet into the switch fabric, it may
202 specify that the payload of the packet is irrelevant. Such packets
203 are known as {\it tokens}, and consume less energy than data packets.
207 \epsfig{file=overview-new,width=2.5in}\\
208 {\it Overview of a Fleet processor; dark gray shading represents the
209 switch fabric, ships are shown in light gray, and docks are shown in blue.}
215 \section{The FleetTwo Dock}
217 The diagram below represents a conceptual view of the interface
218 between ships and the switch fabric; actual implementation circuitry
222 \epsfig{file=all,width=3.5in}\\
223 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
224 blue lines carry either tokens or data words, red lines carry either
225 instructions or torpedoes, and dashed lines carry only tokens.}
228 Each dock consists of a {\it data latch}, which is as wide as a single
229 machine word and a {\it pump}, which is a circular fifo of
230 instruction-width latches. The values in the pump control the data
231 latch. The dock also includes a {\it path latch}, which
232 stores the path along which outgoing packets will be sent.\color{black}
234 Note that the pump in each dock has a destination of its own; this is
235 the {\it instruction destination} mentioned in the previous section.
237 From any source to any dock's data destination there are
238 two distinct paths which differ by a single bit. This bit is known as
239 the ``signal'' bit, and the routing of a packet is not affected by it;
240 the signal bit is used to pass control values between docks. Note that paths
241 terminating at an {\it instruction} destination need not have a signal
245 \section{Instructions}
247 In order to cause an instruction to execute, the programmer must first
248 arrange for that instruction word to arrive in the data latch of some
249 output dock. For example, this might be the ``data read'' output dock
250 of the memory access ship or the output of a fifo ship. Once an
251 instruction has arrived at this output dock, it is {\it dispatched} by
252 sending it to the {\it instruction port} of the dock at which it is to
255 Each instruction is 26 bits long, which makes it possible for an
256 instruction and an 11-bit path to fit in a single word of memory.
257 This path is the path from the {\it dispatching} dock to the {\it
263 \setlength{\bitwidth}{3.5mm}
265 \begin{bytefield}{37}
266 \bitheader[b]{0,25,26,36}\\
267 \bitbox{11}{dispatch path}
268 \bitbox{26}{instruction}
273 Note that the 11 bit {\tt dispatch path} field is not the same width
274 as the 13 bit {\tt Immediate} path field in the {\tt move} instruction,
275 which in turn may not be the same width as the actual path latches in
278 The algorithm for expanding a path to a wider width is specific to the
279 switch fabric implementation, and is not specified by this
280 document.\footnote{\color{red}for the Marina experiment, the correct
281 algorithm is to sign-extend the path; the most significant bit of
282 the given path is used to fill all vacant bits of the latch} In
283 particular, because the {\tt dispatch path} field is always used to
284 specify a path which terminates at an instruction destination (never a
285 data destination), and because instruction destinations ignore the
286 signal bit, certain optimizations may be possible. \color{black}
289 \subsection{Life Cycle of an Instruction}
291 The diagram below shows an input dock for purposes of illustration:
294 \epsfig{file=in,width=4in}\\
301 \epsfig{file=out,width=4in}\\
305 \subsubsection{Torpedoes}
307 A token sent to an instruction destination is called a {\it torpedo}.
308 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
309 waiting area (not shown) rather than being enqueued into {\tt EF}.
311 \subsection{Format of an Instruction}
313 All instruction words have the following format:
315 \newcommand{\bitsHeader}{
320 \newcommand{\bitsHeaderNoI}{
326 \setlength{\bitwidth}{3.5mm}
328 \begin{bytefield}{37}
329 \bitheader[b]{0,10,11,31,32,34-36}\\
334 \bitbox{11}{dispatch path}
340 \item The {\tt I} bit stands for {\tt Immune},
341 and indicates if an instruction is
342 immune to torpedoes. This bit only appears
343 in {\tt move} instructions.
345 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
346 instruction can pass through the pump more than once. If set to
347 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
348 does not pass through the instruction fifo more than once.
350 \item The {\tt P} bits are a {\it predicate}; this
351 holds a code which indicates if the instruction should be executed or
352 ignored depending on the state of flags in the dock.
356 \subsection{Loop Counters}
358 A programmer can perform two types of loops: {\it inner} loops of only
359 one instruction and {\it outer} loops of multiple instructions. Inner
360 loops may be nested within an outer loop, but no other nesting of
363 The dock has two loop counters, one for each kind of loop:
366 \item {\tt OLC} is the Outer Loop Counter
367 \item {\tt ILC} is the Inner Loop Counter
370 The {\tt OLC} applies to all instructions and can hold integers {\tt
373 The {\tt ILC} applies only to {\tt move} instructions and can hold
374 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
375 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
376 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
377 executes until interrupted by a torpedo. After every {\tt move}
378 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
379 to {\tt 1}, {\it not to 0}).
382 \subsection{Flags and Predication}
384 The pump has four flags: {\tt A}, {\tt B},
385 {\tt C}, and {\tt Z}.
388 \item The {\tt A} and {\tt B} flags are general-purpose flags which
389 may be set and cleared by the programmer.
393 % The {\tt L} flag, known as the {\it last} flag, is set whenever
394 % the value in the outer counter ({\tt OLC}) is one,
397 % that the dock is in the midst of the last iteration of an
398 % outer loop. This flag can be used to perform certain
399 % operations (such as sending a completion token) only on the last
400 % iteration of an outer loop.
402 \item The {\tt C} flag is known as the {\it control} flag, and may be
403 set by the {\tt move} instruction based on information from the
404 ship or from an inbound packet. See the {\tt move} instruction
407 \item The {\tt Z} flag is known as the {\it zero} flag; it is set
408 whenever the {\tt OLC} is zero, and is cleared whenever the {\tt
415 The {\tt P} field specifies a three-bit {\it predicate}. The
416 predicate determines which conditions must be true in order for the
417 instruction to execute; if it is not executed, it is simply {\it
418 ignored}. The table below shows what conditions must be true in
419 order for an instruction to execute:
422 \begin{tabular}{|r|l|}\hline
423 Code & Execute if \\\hline
424 {\tt 000:} & {\tt Z=0}\ and {\tt A=0} \\
425 {\tt 001:} & {\tt Z=0}\ and {\tt A=1} \\
426 {\tt 010:} & {\tt Z=0}\ and {\tt B=0} \\
427 {\tt 011:} & {\tt Z=0}\ and {\tt B=1} \\
428 {\tt 100:} & Unused \\
429 {\tt 101:} & {\tt Z=1}\ \\
430 {\tt 110:} & {\tt Z=0}\ \\
431 {\tt 111:} & always \\
436 \subsection{The Hatch}
438 What follows is a conservative approximation of the actual behavior of
440 For complete details on the behavior of the hatch, see
441 \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50}.
443 For the purposes of this section, instructions will be
444 classified into three categories: one-shot instructions ({\tt OS=1}),
445 requeueable instructions ({\tt OS=0}), and {\tt tail} instructions.
447 To avoid deadlock, the programmer must ensure that:
451 \item A requeueable instruction is never followed immediately by a
454 \item A one-shot instruction is never followed immediately by a {\tt
457 \item No contiguous sequence of requeueable instructions is longer
458 than the length of the instruction fifo.
460 \item If a requeueable instruction is preceded by a one-shot
461 instruction or a {\tt tail}, then it must be the case that
462 {\tt Z=0} both before and after the first
463 time that instruction executes.
465 \item If {\tt Z=1}, only a one-shot instruction may set it to a
470 The dock guarantees that:
474 \item If a requeueable instruction is preceded by a one-shot
475 instruction or a {\tt tail}, then the {\it following}
476 instruction will not execute until a {\tt tail} has reached the
479 \item Once a {\tt tail} instruction reaches the hatch, no further
480 instructions will be enqueued until a requeueable instruction
481 reaches the execution stage and {\tt Z=1}.
489 When an instruction arrives on deck, two concurrent processes are
494 \item If the instruction on deck is a requeueable instruction
495 ({\tt OS=0}) and {\tt Z=0}, a copy of
496 the instruction is requeued.
502 If the instruction's predicate condition is not met (see
503 section on predicates), do nothing.
506 {\it Otherwise} if the instruction is interruptible ({\tt I=0})
507 and a torpedo is present in the waiting area: consume the
508 torpedo, set {\tt OLC=0}, {\tt Z=1} and
509 set the inner loop counter to one ({\tt ILC=1}).
512 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
513 not} a {\tt move}: execute the instruction.
522 \section{Instructions}
524 %The dock supports four instructions:
525 %{\tt move} (variants: {\tt moveto}, {\tt dispatch}),
532 \subsection{{\tt move}}
534 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
536 \begin{bytefield}{26}
537 \bitheader[b]{14-20}\\
551 \begin{bytefield}{26}
552 \bitheader[b]{0,12,13}\\
553 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
556 \bitbox{13}{\tt Immediate}
559 \begin{bytefield}{26}
560 \bitheader[b]{11,12,13}\\
561 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:\color{red}27\color{black}]\to Path}})\ \ }
570 \begin{bytefield}{26}
571 \bitheader[b]{11,12,13}\\
572 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
583 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
584 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
585 \item {\tt Dc} - Data Capture: pulse the data latch.
586 \item {\tt Do} - Data Output: fill the data successor.
587 \item {\tt To} - Token Output: fill the token successor.
590 The data successor and token successor must both be empty in order for
591 a {\tt move} instruction to attempt execution.
593 Every time the {\tt move} instruction executes, the {\tt C} flag may
597 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
598 of the incoming packet if {\tt Di} or {\tt Ti} is
599 set otherwise it takes on an unknown
602 \item At an {\it output} dock the {\tt C} flag is set to a value
603 provided by the ship if the {\tt Dc} bit is set. If
604 the {\tt Dc} bit is not set and the {\tt Ti} bit is set, it is
605 set to the signal bit of the incoming packet. If the {\tt Dc}
606 bit and {\tt Ti} bits are both cleared, it takes on an unknown
611 The {\tt flush} instruction is a variant of {\tt move} which is valid
612 only at input docks. It has the same effect as {\tt deliver}, except
613 that it sets a special ``flushing'' indicator along with the data
616 \newcommand{\bitsFlush}{\setlength{\bitwidth}{5mm}
618 \begin{bytefield}{26}
619 \bitheader[b]{14-18}\\
620 \bitbox[r]{7}{\raggedleft{\tt flush\ \ }}
632 When a ship fires, it must examine the ``flushing'' indicators on the
633 input docks whose fullness was part of the firing condition. If all
634 of the input docks' flushing indicators are set, the ship must drain
635 all of their data successors and take no action. If some, but not
636 all, of the indicators are set, the ship must drain {\it only the data
637 successors of the docks whose indicators were {\bf not} set}, and
638 take no action. If none of the flushing indicators was set, the ship
645 \subsection{{\tt set}}
647 The {\tt set} command is used to set or decrement the inner loop
648 counter, outer loop counter, and data latch.
650 \newcommand{\bitsSet}{
651 \setlength{\bitwidth}{5mm}
653 \begin{bytefield}{26}
654 \bitheader[b]{19-25}\\
664 \begin{bytefield}{26}
665 \bitheader[b]{0,5,12-18}\\
666 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
668 \bitbox{4}{\tt 1000\color{black}}
671 \bitbox{6}{\tt Immediate}
674 \begin{bytefield}{26}
675 \bitheader[b]{12-18}\\
676 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
678 \bitbox{4}{\tt 1000\color{black}}
683 \begin{bytefield}{26}
684 \bitheader[b]{12-18}\\
685 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
687 \bitbox{4}{\tt 1000\color{black}}
692 \begin{bytefield}{26}
693 \bitheader[b]{0,5,6,12-18}\\
694 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
696 \bitbox{4}{\tt 0100\color{black}}
700 \bitbox{6}{\tt Immediate}
703 \begin{bytefield}{26}
704 \bitheader[b]{6,12-18}\\
705 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
707 \bitbox{4}{\tt 0100\color{black}}
714 \begin{bytefield}{26}
715 \bitheader[b]{12-18}\\
716 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
718 \bitbox{4}{\tt 0100\color{black}}
723 \begin{bytefield}{26}
724 \bitheader[b]{0,13-18}\\
725 \bitbox[1]{6}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}\to{\tt Data Latch}}
727 \bitbox{4}{\tt 0010\color{black}}
728 \bitbox{1}{\begin{minipage}{0.5cm}{
735 \bitbox{14}{\tt Immediate}
738 \begin{bytefield}{26}
739 \bitheader[b]{0,5,6,11,15-18}\\
740 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
742 \bitbox{4}{\tt 0001\color{black}}
744 \bitbox{6}{\tt nextA}
745 \bitbox{6}{\tt nextB}
754 The FleetTwo implementation is likely to have an unarchitected
755 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
756 with the possibly-extended literal {\it at the time that the {\tt set}
757 instruction comes on deck}. This latch is then copied into the data
758 latch when a {\tt set Data Latch} instruction
761 The {\tt Sign-Extended Immediate} instruction copies the {\tt
762 Immediate} field into the least significant bits of the data latch.
763 All other bits of the data latch are filled with a copy of the
764 bit marked ``{\tt Sign}.''
767 Each of the {\tt nextA} and {\tt nextB} fields has the following
768 structure, and indicates which old flag values should be logically
769 {\tt OR}ed together to produce the new flag value:
775 \bitbox{1}{${\text{\tt A}}$}
776 \bitbox{1}{$\overline{\text{\tt A}}$}
777 \bitbox{1}{${\text{\tt B}}$}
778 \bitbox{1}{$\overline{\text{\tt B}}$}
779 \bitbox{1}{${\text{{\tt C}\ }}$}
780 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
784 Each bit corresponds to one possible input; all inputs whose bits are
785 set are {\tt OR}ed together, and the resulting value is assigned to
786 the flag. Note that if none of the bits are set, the value assigned
787 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
788 OR}ing any flag with its complement, and that {\tt set Flags} can
789 be used to create a {\tt nop} (no-op) by setting each flag to itself.
795 \subsection{{\tt shift}}
797 \newcommand{\shiftImmediateSize}{19}
799 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
800 bits. When a {\tt shift} instruction is executed, this immediate is copied
801 into the least significant \shiftImmediateSize\ bits of the data latch,
802 and the remaining most significant bits of the data latch are loaded
803 with the value formerly in the least significant bits of the data latch.
804 In this manner, large literals can be built up by ``shifting'' them
805 into the data latch \shiftImmediateSize\ bits at a time.
807 \newcommand{\bitsShift}{
808 \setlength{\bitwidth}{5mm}
810 \begin{bytefield}{26}
811 \bitheader[b]{0,18-20}\\
818 \bitbox{\shiftImmediateSize}{Immediate}
823 The FleetTwo implementation is likely to have an unarchitected
824 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
825 with the literal {\it at the time that the {\tt shift} instruction
826 comes on deck}. This latch is then copied into the data latch when
827 the instruction executes.
831 \subsection{{\tt tail}}
833 \newcommand{\bitsTail}{
834 \setlength{\bitwidth}{5mm}
836 \begin{bytefield}{26}
837 \bitheader[b]{19-20}\\
848 When a {\tt tail} instruction reaches the hatch and the hatch is open,
849 it seals the hatch. The {\tt tail} instruction does not enter the
854 %\subsection{{\tt takeOuterLoopCounter}}
856 %\setlength{\bitwidth}{5mm}
858 %\begin{bytefield}{26}
859 % \bitheader[b]{16-19,21}\\
873 %This instruction copies the value in the outer loop counter {\tt OLC}
874 %into the least significant bits of the data latch and leaves all other
875 %bits of the data latch unchanged.
877 %\subsection{{\tt takeInnerLoopCounter}}
879 %\setlength{\bitwidth}{5mm}
881 %\begin{bytefield}{26}
882 % \bitheader[b]{16-19,21}\\
896 %This instruction copies the value in the inner loop counter {\tt ILC}
897 %into the least significant bits of the data latch and leaves all other
898 %bits of the data latch unchanged.
903 %%\subsection{{\tt interrupt}}
905 %%\setlength{\bitwidth}{5mm}
907 %\begin{bytefield}{26}
908 % \bitheader[b]{0,5,16-19,21}\\
919 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
920 %there for the {\tt OD} stage to be full with an instruction that has
921 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
922 %{\it will not execute}, but {\it may reloop} if the conditions for
924 %\footnote{The ability to interrupt an instruction yet have it reloop is very
925 %useful for processing chunks of data with a fixed size header and/or
926 %footer and a variable length body.}
929 %\subsection{{\tt massacre}}
931 %\setlength{\bitwidth}{5mm}
933 %\begin{bytefield}{26}
934 % \bitheader[b]{16-19,21}\\
946 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
947 %for the {\tt OD} stage to be full with an instruction that has the
948 %{\tt IM} bit set. When this occurs, all instructions in the
949 %instruction fifo (including {\tt OD}) are retired.
951 %\subsection{{\tt clog}}
953 %\setlength{\bitwidth}{5mm}
955 %\begin{bytefield}{26}
956 % \bitheader[b]{16-19,21}\\
968 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
969 %no more instructions will be executed until an {\tt unclog} is
972 %\subsection{{\tt unclog}}
974 %\setlength{\bitwidth}{5mm}
976 %\begin{bytefield}{26}
977 % \bitheader[b]{16-19,21}\\
983 % \bitbox[lrtb]{2}{11}
989 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
990 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
991 %instructions retire.
993 %Note that issuing an {\tt unclog} instruction to a dock which is not
994 %clogged and whose instruction fifo contains no {\tt clog} instructions
995 %will cause the dock to deadlock.
1000 \section*{Instruction Encoding Map\color{black}}
1002 \hspace{-1cm}{\tt shift}\\
1005 \hspace{-1cm}{\tt set}\\
1008 \hspace{-1cm}{\tt move}\\
1013 \hspace{-1cm}{\tt tail}\\
1020 \epsfig{file=all,height=5in,angle=90}
1023 \subsection*{Input Dock}
1024 \epsfig{file=in,width=8in,angle=90}
1027 \subsection*{Output Dock}
1028 \epsfig{file=out,width=8in,angle=90}
1032 %\epsfig{file=ports,height=5in,angle=90}
1035 %\epsfig{file=best,height=5in,angle=90}