3 == Ports ===========================================================
12 == Constants ========================================================
18 == TeX ==============================================================
19 == Fleeterpreter ====================================================
20 public void service() {
21 if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip() && box_out.readyForDataFromShip()) {
22 long data = box_in.removeDataForShip();
23 long opcode = box_inOp.removeDataForShip();
25 case 0: box_out.addDataFromShip(-1 * data); // NEG
27 case 1: box_out.addDataFromShip(data+1); // INC
29 case 2: box_out.addDataFromShip(data-1); // DEC
31 case 3: box_out.addDataFromShip(Math.abs(data)); // ABS
33 default: box_out.addDataFromShip(0);
39 == FleetSim ==============================================================
40 == FPGA ==============================================================
42 reg [(`PACKET_WIDTH-1):0] reg_a;
44 reg [(`PACKET_WIDTH-1):0] reg_op;
45 reg [(`PACKET_WIDTH-1):0] extrabits;
47 always @(posedge clk) begin
49 `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
52 `onread(inOp_r, inOp_a)
54 reg_op = inOp_d[(`DATAWIDTH-1):0];
55 extrabits = inOp_d[(`PACKET_WIDTH-1):`DATAWIDTH];
59 if (have_a && have_op) begin
64 3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
65 4: out_d = 37'b1111111111111111111111111111111111111;
69 `onwrite(out_r, out_a)
77 == Contributors =========================================================
78 Adam Megacz <megacz@cs.berkeley.edu>