3 == Ports ===========================================================
10 == Constants ========================================================
11 ADD: add the two arguments; treat link as carry
12 SUB: subtract the two arguments; treat link as carry
16 == TeX ==============================================================
17 This ship is a two-input arithmetic unit. It features several
18 opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
21 FIXME: implement all the link bit stuff
23 Use carry-in bit to create a selector? Perhaps a waste of an ALU.
25 Flags: zero, negative, overflow, ?
32 == Fleeterpreter ====================================================
33 public long resolveLiteral(String literal) {
34 if (literal.equals("ADD")) return 0;
35 if (literal.equals("SUB")) return 1;
36 if (literal.equals("MAX")) return 2;
37 if (literal.equals("MIN")) return 3;
38 return super.resolveLiteral(literal);
40 public void service() {
41 if (box_in1.dataReadyForShip() &&
42 box_in2.dataReadyForShip() &&
43 box_inOp.dataReadyForShip() &&
44 box_out.readyForDataFromShip()) {
45 long a = box_in1.removeDataForShip();
46 long b = box_in2.removeDataForShip();
47 long op = box_inOp.removeDataForShip();
49 case 0: box_out.addDataFromShip(a+b); // ADD
51 case 1: box_out.addDataFromShip(a-b); // SUB
53 case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
55 case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
57 default: box_out.addDataFromShip(0);
63 == FleetSim ==============================================================
65 == FPGA ==============================================================
68 reg [(`DATAWIDTH-1):0] reg_a;
70 reg [(`DATAWIDTH-1):0] reg_b;
72 reg [(`DATAWIDTH-1):0] reg_op;
74 always @(posedge clk) begin
76 `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
79 `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
82 `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
85 if (have_a && have_b && have_op) begin
87 0: out_d = reg_a + reg_b;
88 1: out_d = reg_a - reg_b;
89 2: out_d = reg_a > reg_b ? reg_a : reg_b;
90 3: out_d = reg_a > reg_b ? reg_b : reg_a;
93 `onwrite(out_r, out_a)
104 == Contributors =========================================================
105 Adam Megacz <megacz@cs.berkeley.edu>