ships/DDR2.ship

   1 ship: DDR2
   2
   3 == Ports ===========================================================
   4 data  in:    inAddrRead
   5 data  in:    inAddrWrite
   6 data  in:    inDataWrite
   7
   8 data  out:   out
   9
  10 percolate up:    gpio_led_0   1
  11 percolate up:    gpio_led_1   1
  12 percolate up:    gpio_led_2   1
  13 percolate up:    gpio_led_3   1
  14
  15 percolate inout: ddr2_dq       64
  16 percolate up:    ddr2_a        13
  17 percolate up:    ddr2_ba       2
  18 percolate up:    ddr2_ras_n    1
  19 percolate up:    ddr2_cas_n    1
  20 percolate up:    ddr2_we_n     1
  21 percolate up:    ddr2_cs_n     1
  22 percolate up:    ddr2_odt      1
  23 percolate up:    ddr2_cke      1
  24 percolate up:    ddr2_dm       8
  25 percolate up:    phy_init_done 1
  26 percolate inout: ddr2_dqs      8
  27 percolate inout: ddr2_dqs_n    8
  28 percolate up:    ddr2_ck       2
  29 percolate up:    ddr2_ck_n     2
  30
  31 == TeX ==============================================================
  32
  33 == Fleeterpreter ====================================================
  34     public void service() { }
  35 == FleetSim ==============================================================
  36
  37 == FPGA ==============================================================
  38
  39 /*
  40 percolate inout: ddr2_dq       8
  41 percolate up:    ddr2_a        15
  42 percolate up:    ddr2_ba       3
  43 percolate up:    ddr2_ras_n    1
  44 percolate up:    ddr2_cas_n    1
  45 percolate up:    ddr2_we_n     1
  46 percolate up:    ddr2_cs_n     1
  47 percolate up:    ddr2_odt      1
  48 percolate up:    ddr2_cke      1
  49 percolate up:    ddr2_dm       1
  50 percolate up:    phy_init_done 1
  51 percolate inout: ddr2_dqs      1
  52 percolate inout: ddr2_dqs_n    1
  53 percolate up:    ddr2_ck       1
  54 percolate up:    ddr2_ck_n     1
  55 */
  56
  57 //NET  "sys_clk_p"   LOC = "H17" ;            #Bank 3
  58 //NET  "sys_clk_n"   LOC = "H18" ;            #Bank 3
  59 //NET  "clk200_p"    LOC = "K17" ;            #Bank 3
  60 //NET  "clk200_n"    LOC = "L18" ;            #Bank 3
  61 //NET  "sys_rst_n"   LOC = "L24" ;            #Bank 19
  62
  63 /*******************************************************************************
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  66 *     design files limited to Xilinx devices or technologies. Use              *
  67 *     with non-Xilinx devices or technologies is expressly prohibited          *
  68 *     and immediately terminates your license.                                 *
  69 *                                                                              *
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  71 *     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
  72 *     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
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  85 *     appliances, devices, or systems. Use in such applications are            *
  86 *     expressly prohibited.                                                    *
  87 *                                                                              *
  88 *     (c) Copyright 1995-2006 Xilinx, Inc.                                     *
  89 *     All rights reserved.                                                     *
  90 *******************************************************************************/
  91 // The following must be inserted into your Verilog file for this
  92 // core to be instantiated. Change the instance name and port connections
  93 // (in parentheses) to your own signal names.
  94
  95 //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
  96
  97 wire clk200_p;
  98 wire clk200_n;
  99 wire clk_rebuffered;
 100
 101  ddr2_sdram # (
 102     .BANK_WIDTH(2),                    // # of memory bank addr bits.
 103     .CKE_WIDTH(1),                     // # of memory clock enable outputs.
 104     .CLK_WIDTH(2),                     // # of clock outputs.
 105     .COL_WIDTH(10),                    // # of memory column bits.
 106     .CS_NUM(1),                        // # of separate memory chip selects.
 107     .CS_WIDTH(1),                      // # of total memory chip selects.
 108     .CS_BITS(0),                       // set to log2(CS_NUM) (rounded up).
 109     .DM_WIDTH(8),                      // # of data mask bits.
 110     .DQ_WIDTH(64),                     // # of data width.
 111     .DQ_PER_DQS(8),                    // # of DQ data bits per strobe.
 112     .DQS_WIDTH(8),                     // # of DQS strobes.
 113     .DQ_BITS(6),                       // set to log2(DQS_WIDTH*DQ_PER_DQS).
 114     .DQS_BITS(3),                      // set to log2(DQS_WIDTH).
 115     .ODT_WIDTH(1),                     // # of memory on-die term enables.
 116     .ROW_WIDTH(13),                    // # of memory row and # of addr bits.
 117     .ADDITIVE_LAT(0),                  // additive write latency.
 118     .BURST_LEN(4),                     // burst length (in double words).
 119     .BURST_TYPE(0),                    // burst type (=0 seq; =1 interleaved).
 120     .CAS_LAT(4),                       // CAS latency.
 121     .ECC_ENABLE(0),                    // enable ECC (=1 enable).
 122     .APPDATA_WIDTH(128),               // # of usr read/write data bus bits.
 123     .MULTI_BANK_EN(1),                 // Keeps multiple banks open. (= 1 enable).
 124     .TWO_T_TIME_EN(1),                 // 2t timing for unbuffered dimms.
 125     .ODT_TYPE(1),                      // ODT (=0(none),=1(75),=2(150),=3(50)).
 126     .REDUCE_DRV(0),                    // reduced strength mem I/O (=1 yes).
 127     .REG_ENABLE(0),                    // registered addr/ctrl (=1 yes).
 128     .TREFI_NS(7800),                   // auto refresh interval (ns).
 129     .TRAS(40000),                      // active->precharge delay.
 130     .TRCD(15000),                      // active->read/write delay.
 131     .TRFC(127500),                     // refresh->refresh, refresh->active delay.
 132     .TRP(15000),                       // precharge->command delay.
 133     .TRTP(7500),                       // read->precharge delay.
 134     .TWR(15000),                       // used to determine write->precharge.
 135     .TWTR(7500),                       // write->read delay.
 136     .HIGH_PERFORMANCE_MODE("TRUE"),    // # = TRUE, the IODELAY performance mode is set to high.
 137                                        // # = FALSE, the IODELAY performance mode is set to low.
 138     .SIM_ONLY(0),                      // = 1 to skip SDRAM power up delay.
 139     .DEBUG_EN(0),                      // Enable debug signals/controls.
 140                                        // When this parameter is changed from 0 to 1,
 141                                        // make sure to uncomment the coregen commands
 142                                        // in ise_flow.bat or create_ise.bat files in
 143                                        // par folder.
 144     .CLK_PERIOD(5000),                 // Core/Memory clock period (in ps).
 145     .DQS_IO_COL(16'b0000000000000000), // I/O column location of DQS groups
 146                                        // (=0, left; =1 center, =2 right).
 147     //.DQ_IO_MS(64'b10100101_10100101_10100101_10100101_10100101_10100101_10100101_10100101),
 148     .DQ_IO_MS(64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100),
 149                                        // Master/Slave location of DQ I/O (=0 slave).
 150     .CLK_TYPE("SINGLE_ENDED"),         // # = "DIFFERENTIAL " ->; Differential input clocks ,
 151                                        // # = "SINGLE_ENDED" -> Single ended input clocks.
 152     .DLL_FREQ_MODE("HIGH"),            // DCM Frequency range.
 153     .RST_ACT_LOW(1)                    // =1 for active low reset, =0 for active high.
 154 )
 155 ddr2_sdram (
 156     .sys_clk                   (clk),
 157     .idly_clk_200              (clk200_p),
 158     .sys_rst_n                 (!rst),
 159
 160     .ddr2_dq                   (ddr2_dq),
 161     .ddr2_a                    (ddr2_a),
 162     .ddr2_ba                   (ddr2_ba),
 163     .ddr2_ras_n                (ddr2_ras_n),
 164     .ddr2_cas_n                (ddr2_cas_n),
 165     .ddr2_we_n                 (ddr2_we_n),
 166     .ddr2_cs_n                 (ddr2_cs_n),
 167     .ddr2_odt                  (ddr2_odt),
 168     .ddr2_cke                  (ddr2_cke),
 169     .ddr2_dm                   (ddr2_dm),
 170     .ddr2_dqs                  (ddr2_dqs),
 171     .ddr2_dqs_n                (ddr2_dqs_n),
 172     .ddr2_ck                   (ddr2_ck),
 173     .ddr2_ck_n                 (ddr2_ck_n),
 174
 175     .phy_init_done             (gpio_led_0),
 176
 177     .app_wdf_afull             (gpio_led_1),
 178     .app_af_afull              (gpio_led_2),
 179     .rd_data_valid             (gpio_led_3),
 180
 181     .app_wdf_wren              (1'b1),
 182     .app_af_wren               (app_af_wren),
 183     .app_af_addr               (app_af_addr),
 184     .app_af_cmd                (app_af_cmd),
 185
 186     .rd_data_fifo_out          (rd_data_fifo_out),
 187     .app_wdf_data              (app_wdf_data),
 188     .app_wdf_mask_data         (app_wdf_mask_data)
 189 );
 190
 191   wire clk200_p_fb;
 192   DCM  // 200Mhz DDR clock
 193    #(
 194       .CLKFX_MULTIPLY(2),
 195       .CLKFX_DIVIDE(1),
 196       .CLKIN_PERIOD("10 ns")
 197     ) vgadcm (
 198       .CLKIN    (clk),
 199       .CLKFB    (clk200_p_fb),
 200       .CLKFX    (clk200_n),
 201       .CLKFX180 (clk200_p),
 202       .CLK0     (clk200_p_fb)
 203     );
 204
 205 /*
 206   always @(posedge clk) begin
 207
 208     if (rst) begin
 209       `reset
 210       CommandValid <= 0;
 211       DataOutReady <= 0;
 212     end else begin
 213       `cleanup
 214
 215       CommandValid <= 0;
 216       DataInValid  <= 0;
 217
 218       if (`out_empty) begin
 219           DataOutReady <= 1;
 220       end
 221
 222       if (DataOutReady && DataOutValid && `out_empty) begin
 223           out_d <= { 1'b0, DataOut[`WORDWIDTH-1:0] };
 224           `fill_out
 225           DataOutReady <= 0;
 226
 227       end else if (DataOutReady && CommandReady && DataInReady && `out_empty) begin
 228           if (`inAddrWrite_full && `inDataWrite_full) begin
 229             `drain_inDataWrite
 230             `drain_inAddrWrite
 231             CommandAddress <= inAddrWrite_d;
 232             Command        <= 3'b000;
 233             CommandValid   <= 1;
 234             DataInValid    <= 1;
 235             out_d <= { 1'b1, 37'b0 };
 236             `fill_out
 237             DataOutReady <= 0;
 238           end else if (`inAddrRead_full) begin
 239             `drain_inAddrRead
 240             CommandAddress <= inAddrRead_d;
 241             CommandValid   <= 1;
 242             Command        <= 3'b001;
 243             DataInValid    <= 0;
 244             DataOutReady   <= 1;
 245           end
 246       end
 247     end
 248   end
 249 */
 250
 251 == Test ==============================================================
 252
 253 #skip
 254 #expect 0
 255
 256 #ship debug : Debug
 257 #ship ddr   : DDR2
 258
 259 debug.in:
 260   recv, deliver;
 261
 262 ddr.out:
 263   collect;
 264   set flags a=!c,b=b;
 265   send to debug.in;
 266   collect;
 267   set flags a=!c,b=b;
 268   send to debug.in;
 269 ddr.inAddrWrite:
 270   set word=0;
 271   deliver;
 272   deliver;
 273 ddr.inDataWrite:
 274   set word=1;
 275   deliver;
 276   deliver;
 277
 278
 279
 280
 281 == Constants ========================================================
 282
 283 == Contributors =========================================================
 284 Adam Megacz <megacz@cs.berkeley.edu>