ships/DRAM.ship

   1 ship: DRAM
   2
   3 == Ports ===========================================================
   4 data  in:    inAddrRead
   5 data  in:    inAddrWrite
   6 data  in:    inDataWrite
   7
   8 data  out:   out
   9
  10 percolate up:     dram_addr_                32
  11 percolate up:     dram_addr_r_              1
  12 percolate down:   dram_addr_a               1
  13 percolate up:     dram_isread_              1
  14 percolate up:     dram_write_data_          64
  15 percolate up:     dram_write_data_push_     1
  16 percolate down:   dram_write_data_full      1
  17 percolate down:   dram_read_data            64
  18 percolate up:     dram_read_data_pop_       1
  19 percolate down:   dram_read_data_empty      1
  20 percolate down:   dram_read_data_latency    2
  21
  22 == TeX ==============================================================
  23
  24 == Fleeterpreter ====================================================
  25     public void service() { }
  26 == FleetSim ==============================================================
  27
  28 == FPGA ==============================================================
  29
  30   reg         dram_addr_r;
  31   reg         dram_isread;
  32   reg         dram_write_data_push;
  33   reg         dram_read_data_pop;
  34   reg  [`WORDWIDTH:0]  out_d;
  35   wire [31:0] dram_addr__;
  36
  37   assign dram_addr_r_ = dram_addr_r;
  38   assign dram_isread_ = dram_isread;
  39   assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
  40   assign dram_addr_  = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
  41   assign dram_write_data_push_ = dram_write_data_push;
  42   assign dram_read_data_pop_ = dram_read_data_pop;
  43   assign dram_write_data_ = inDataWrite_d;
  44 //  assign dram_write_data_ = inDataWrite_d[(`WORDWIDTH-1):0];
  45   assign out_d_ = out_d;
  46
  47   always @(posedge clk) begin
  48
  49     if (!rst) begin
  50       `reset
  51       dram_isread <= 0;
  52       dram_addr_r <= 0;
  53       dram_read_data_pop <= 0;
  54
  55     end else begin
  56       `flush
  57       `cleanup
  58
  59       if (dram_addr_r && !dram_addr_a) begin
  60          // busy
  61       end else if (dram_addr_r &&  dram_addr_a && !dram_isread) begin
  62           dram_addr_r <= 0;
  63           `drain_inDataWrite
  64           `drain_inAddrWrite
  65           `fill_out
  66           out_d <= { 1'b1, 37'b0 };
  67       end else if (dram_addr_r &&  dram_addr_a && dram_isread) begin
  68           dram_addr_r <= 0;
  69           `drain_inAddrRead
  70           `fill_out
  71           out_d <= { 1'b0, dram_read_data[36:0] };
  72       end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full && !dram_addr_r && !dram_addr_a) begin
  73           dram_addr_r <= 1;
  74           dram_isread <= 0;
  75       end else if (`out_empty && `inAddrRead_full && !dram_addr_r && !dram_addr_a) begin
  76           dram_addr_r <= 1;
  77           dram_isread <= 1;
  78       end
  79     end
  80   end
  81
  82
  83 == Test ========================================================
  84 #skip
  85
  86 == Constants ========================================================
  87
  88 == Contributors =========================================================
  89 Adam Megacz <megacz@cs.berkeley.edu>