3 == Ports:Interpreter ===========================================================
7 == Ports:Bee2 ===========================================================
11 percolate down: Clkin_p 1
12 percolate down: Clkin_m 1
13 percolate up: clk_out 1
15 percolate down: RDWR_B 1
16 percolate down: CS_B 1
18 percolate up: INIT_B 1
20 percolate up: rst_out 1
21 percolate down: rst_in 1
23 == Ports:ML509 ===========================================================
27 percolate down: uart_in 1
28 percolate up: uart_out 1
29 percolate up: rst_out 1
30 percolate down: rst_in 1
31 percolate down: clk_pin 1
32 percolate up: clk_out 1
34 == TeX ==============================================================
36 This ship is used for debugging. It has only one port, {\tt in}.
37 Programmers should send debug report values to this port. How such
38 values are reported back to the programmer doing the debugging is left
43 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
44 effectively allow multiple independent ``debug streams''
46 Provide a way to programmatically read back the output of the debug
49 == Fleeterpreter ====================================================
50 public void service() {
51 if (box_in.dataReadyForShip())
52 ((Interpreter)getFleet()).debug(new BitVector(37).set(box_in.removeDataForShip()));
55 == FPGA:Bee2 ==============================================================
65 wire [7:0] write_data;
74 OBUF obuf_cclk( .I( CCLK_int ), .O( CCLK ) );
75 IOBUF iobuf_d0( .I( D_O[0] ), .IO( D[0] ), .O( D_I[0] ), .T( D_T[0] ) );
76 IOBUF iobuf_d1( .I( D_O[1] ), .IO( D[1] ), .O( D_I[1] ), .T( D_T[1] ) );
77 IOBUF iobuf_d2( .I( D_O[2] ), .IO( D[2] ), .O( D_I[2] ), .T( D_T[2] ) );
78 IOBUF iobuf_d3( .I( D_O[3] ), .IO( D[3] ), .O( D_I[3] ), .T( D_T[3] ) );
79 IOBUF iobuf_d4( .I( D_O[4] ), .IO( D[4] ), .O( D_I[4] ), .T( D_T[4] ) );
80 IOBUF iobuf_d5( .I( D_O[5] ), .IO( D[5] ), .O( D_I[5] ), .T( D_T[5] ) );
81 IOBUF iobuf_d6( .I( D_O[6] ), .IO( D[6] ), .O( D_I[6] ), .T( D_T[6] ) );
82 IOBUF iobuf_d7( .I( D_O[7] ), .IO( D[7] ), .O( D_I[7] ), .T( D_T[7] ) );
84 // Clock buffer and reset
88 IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ), .IB( Clkin_m ), .O( clk_fast ) );
90 wire clkdiv0_unbuffered;
93 // BUFG bufg1 (.I(clkdiv0_unbuffered), .O(clk_out));
94 // BUFG bufg1 (.I(clk_fast), .O(clk_out));
95 // BUFG bufg1 (.I(clk0_unbuffered), .O(clk_out));
96 BUFG bufg2 (.I(clk0_unbuffered), .O(clk0_fb));
101 BUFG bufg1 (.I(foo2), .O(clk_out));
103 always @(posedge clk_fast) begin
111 .CLKIN_PERIOD (10.0),
112 .DUTY_CYCLE_CORRECTION ("TRUE"),
113 .DLL_FREQUENCY_MODE ("LOW"),
114 .STARTUP_WAIT ("FALSE")
118 .CLK0 (clk0_unbuffered),
122 // BUFG GBUF_FOR_MUX_CLOCK (.I(clk_half), .O(clk_out));
123 // BUFG GBUF_FOR_MUX_CLOCK (.I(clk_fast), .O(clk_out));
127 FD rstr0( .D( 1'b0 ), .Q( rstr[0] ), .C( clk ) ); defparam rstr0.INIT = 1'b1;
128 FD rstr1( .D( rstr[0] ), .Q( rstr[1] ), .C( clk ) ); defparam rstr1.INIT = 1'b1;
129 FD rstr2( .D( rstr[1] ), .Q( rstr[2] ), .C( clk ) ); defparam rstr2.INIT = 1'b1;
130 FD rstr3( .D( rstr[2] ), .Q( rstr[3] ), .C( clk ) ); defparam rstr3.INIT = 1'b1;
131 assign User_Rst = |rstr;
134 .WrFifo_Din( write_data ),
135 .WrFifo_WrEn( write_enable ),
136 .WrFifo_Full( write_full ),
138 .RdFifo_Dout( read_data ),
139 .RdFifo_RdEn( read_enable ),
140 .RdFifo_Empty( read_empty ),
142 .User_Rst( User_Rst ),
144 .Sys_Rst( User_Rst ),
145 .Sys_Clk( clk_fast ),
155 wire data_to_host_full;
156 reg [7:0] data_to_host;
157 wire data_to_fleet_empty;
158 wire [7:0] data_to_fleet;
159 reg data_to_host_write_enable;
160 reg data_to_fleet_read_enable;
162 assign data_to_fleet = read_data;
163 assign read_enable = data_to_fleet_read_enable;
164 assign write_enable = data_to_host_write_enable;
165 assign write_data = data_to_host;
166 assign data_to_fleet_empty = read_empty;
167 assign data_to_host_full = write_full;
169 initial data_to_fleet_read_enable = 1;
170 initial data_to_host_write_enable = 0;
172 reg [7:0] force_reset;
173 assign rst_out = User_Rst || (force_reset!=0);
175 /// Common //////////////////////////////////////////////////////////////////////////////
180 reg [`WORDWIDTH-1:0] data_to_host_full_word;
184 assign out_d_ = out_d;
189 always @(posedge clk) begin
190 if (/*rst_in*/User_Rst) begin
201 data_to_host_write_enable <= 0;
202 if (force_reset == 1) begin
204 data_to_host_write_enable <= 1;
209 end else if (force_reset != 0) begin
210 force_reset <= force_reset-1;
211 end else if (count_out==0 && `in_full) begin
213 data_to_host_full_word <= in_d;
215 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
216 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
217 data_to_host_full_word <= (data_to_host_full_word >> 6);
218 data_to_host_write_enable <= 1;
219 count_out <= count_out-1;
220 credits = credits - 1;
224 data_to_fleet_read_enable <= 0;
225 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
227 // Note: if the switch fabric refuses to accept a new item,
228 // we can get deadlocked in a state where sending a reset
229 // code (2'b11) won't have any effect. Probably need to go
230 // back to using the break signal.
233 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
234 data_to_fleet_read_enable <= 1;
235 out_d <= { out_d[43:0], data_to_fleet[5:0] };
236 if (count_in==9) begin
240 count_in <= count_in+1;
243 // command 1: flow control credit
244 end else if (data_to_fleet[7:6] == 2'b01) begin
245 data_to_fleet_read_enable <= 1;
246 credits = credits + data_to_fleet[5:0];
248 // command 3: reset (and echo back reset code)
249 end else if (data_to_fleet[7:6] == 2'b11) begin
250 data_to_fleet_read_enable <= 1;
251 data_to_host <= data_to_fleet;
262 == UCF:Bee2 =================================================================
264 ######################################
266 ######################################
268 NET Clkin_p LOC = AP21 | IOSTANDARD = LVDS_25;
269 NET Clkin_m LOC = AN21 | IOSTANDARD = LVDS_25;
271 NET rst_in LOC = H4 | IOSTANDARD = LVCMOS18;
273 NET clk_out PERIOD=50MHz;
274 //NET clk_out PERIOD=100MHz;
275 //NET clk_fast PERIOD=100MHz;
276 NET Clkin_p PERIOD=100MHz;
277 NET Clkin_m PERIOD=100MHz;
279 ######################################
280 ## SelectMAP interface pins
281 ######################################
283 NET D<0> LOC = AU9 | IOSTANDARD = LVCMOS25;
284 NET D<1> LOC = AV9 | IOSTANDARD = LVCMOS25;
285 NET D<2> LOC = AY9 | IOSTANDARD = LVCMOS25;
286 NET D<3> LOC = AW9 | IOSTANDARD = LVCMOS25;
287 NET D<4> LOC = AW34 | IOSTANDARD = LVCMOS25;
288 NET D<5> LOC = AY34 | IOSTANDARD = LVCMOS25;
289 NET D<6> LOC = AV34 | IOSTANDARD = LVCMOS25;
290 NET D<7> LOC = AU34 | IOSTANDARD = LVCMOS25;
292 NET RDWR_B LOC = AR34 | IOSTANDARD = LVCMOS25;
293 NET CS_B LOC = AT34 | IOSTANDARD = LVCMOS25;
294 NET INIT_B LOC = AR9 | IOSTANDARD = LVCMOS25;
295 NET CCLK LOC = C14 | IOSTANDARD = LVCMOS25;
301 == FPGA:ML509 ==============================================================
307 reg [`WORDWIDTH-1:0] data_to_host_full_word;
311 assign out_d_ = out_d;
313 wire data_to_host_full;
314 reg [7:0] data_to_host;
315 wire data_to_fleet_empty;
316 wire [7:0] data_to_fleet;
317 reg data_to_host_write_enable;
318 reg data_to_fleet_read_enable;
319 reg [7:0] force_reset;
321 assign clk_out = clk_pin;
329 assign rst_out = rst_in || (force_reset!=0) /* || break */;
331 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
332 // using a 33Mhz clock,
333 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
334 // using a 100Mhz clock,
335 // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
336 // using a 100Mhz clock, 115200baud
337 // 100Mhz / 115200hz * 4 = 217.013 => 215+2,1 => 215,1
338 // sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
339 sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
340 sasc_top sasc_top(clk, !rst_in,
349 data_to_fleet_read_enable,
350 data_to_host_write_enable,
359 always @(posedge clk) begin
360 if (rst_in /* || break */) begin
371 data_to_host_write_enable <= 0;
372 if (force_reset == 1) begin
374 data_to_host_write_enable <= 1;
379 end else if (force_reset != 0) begin
380 force_reset <= force_reset-1;
381 end else if (count_out==0 && `in_full) begin
383 data_to_host_full_word <= in_d;
385 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
386 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
387 data_to_host_full_word <= (data_to_host_full_word >> 6);
388 data_to_host_write_enable <= 1;
389 count_out <= count_out-1;
390 credits = credits - 1;
394 data_to_fleet_read_enable <= 0;
395 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
397 // Note: if the switch fabric refuses to accept a new item,
398 // we can get deadlocked in a state where sending a reset
399 // code (2'b11) won't have any effect. Probably need to go
400 // back to using the break signal.
403 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
404 data_to_fleet_read_enable <= 1;
405 out_d <= { out_d[43:0], data_to_fleet[5:0] };
406 if (count_in==9) begin
410 count_in <= count_in+1;
413 // command 1: flow control credit
414 end else if (data_to_fleet[7:6] == 2'b01) begin
415 data_to_fleet_read_enable <= 1;
416 credits = credits + data_to_fleet[5:0];
419 // uncommenting this requires changing data_to_host_write_enable
420 // to a blocking assignment, and seems to cause data loss whenever
421 // more than four items are in flight.
423 end else if (data_to_fleet[7:6] == 2'b10 && !data_to_host_full && !data_to_host_write_enable) begin
424 data_to_fleet_read_enable <= 1;
425 data_to_host <= data_to_fleet;
426 data_to_host_write_enable = 1;
429 // command 3: reset (and echo back reset code)
430 end else if (data_to_fleet[7:6] == 2'b11) begin
431 data_to_fleet_read_enable <= 1;
432 data_to_host <= data_to_fleet;
442 == UCF:ML509 =================================================================
444 Net clk_pin LOC=AH15;
445 Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
448 #Net clk_pin LOC=AH17;
449 #Net clk_pin TNM_NET = clk_pin;
450 #TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
456 #Net uart_cts LOC=G6;
457 #Net uart_cts IOSTANDARD = LVCMOS33;
460 #Net uart_rts LOC=F6;
461 #Net uart_rts IOSTANDARD = LVCMOS33;
464 Net uart_in LOC=AG15;
465 #Net uart_in IOSTANDARD = LVCMOS33;
469 Net uart_out LOC=AG20;
470 #Net uart_out IOSTANDARD = LVCMOS33;
477 == Test ================================================================
486 == Contributors =========================================================
487 Adam Megacz <megacz@cs.berkeley.edu>