3 == Ports ===========================================================
10 percolate up: dvi_d2 1
11 percolate up: dvi_d3 1
12 percolate up: dvi_d4 1
13 percolate up: dvi_d5 1
14 percolate up: dvi_d6 1
15 percolate up: dvi_d7 1
16 percolate up: dvi_d8 1
17 percolate up: dvi_d9 1
18 percolate up: dvi_d10 1
19 percolate up: dvi_d11 1
23 percolate up: dvi_xclk_n 1
24 percolate up: dvi_xclk_p 1
25 percolate up: dvi_de 1
26 percolate up: dvi_reset_b 1
28 percolate down: gpio_sw_c 1
30 percolate up: gpio_led_c 1
31 percolate up: gpio_led_e 1
32 percolate up: gpio_led_n 1
33 percolate up: gpio_led_s 1
34 percolate up: gpio_led_w 1
36 percolate up: gpio_led_4 1
37 percolate up: gpio_led_5 1
38 percolate up: gpio_led_6 1
39 percolate up: gpio_led_7 1
41 percolate up: dvi_iic_scl 1
42 percolate inout: dvi_iic_sda 1
44 == FPGA ==============================================================
55 assign dvi_reset_b = 1;
56 assign dvi_de = data_valid_ext;
71 ) my_vga_timing_generator (
79 .DATA_VALID_EXT(data_valid_ext),
84 .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
85 .INIT(1'b0), // Initial value for Q port ('1' or '0')
86 .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
88 .Q(dvi_xclk_p), // 1-bit DDR output
89 .C(pix_clk), // 1-bit clock input
90 .CE(1), // 1-bit clock enable input
91 .D1(1), // 1-bit data input (positive edge)
92 .D2(0), // 1-bit data input (negative edge)
93 .R(0), // 1-bit reset input
94 .S(0) // 1-bit set input
97 .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
98 .INIT(1'b0), // Initial value for Q port ('1' or '0')
99 .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
101 .Q(dvi_xclk_n), // 1-bit DDR output
102 .C(pix_clk), // 1-bit clock input
103 .CE(1), // 1-bit clock enable input
104 .D1(0), // 1-bit data input (positive edge)
105 .D2(1), // 1-bit data input (negative edge)
106 .R(0), // 1-bit reset input
107 .S(0) // 1-bit set input
110 i2c_video_programmer my_i2c_video_programmer_i (
113 .I2C_SDA(dvi_iic_sda),
114 .I2C_SCL(dvi_iic_scl));
117 .CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
118 .CLKFX_DIVIDE(16), // Can be any interger from 1 to 32
119 .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
120 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
121 .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
122 .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
123 .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
124 .DCM_AUTOCALIBRATION("TRUE"), // DCM calibrartion circuitry TRUE/FALSE
125 .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
126 .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
127 .DFS_FREQUENCY_MODE("HIGH"), // LOW or HIGH frequency mode for frequency synthesis
128 .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
129 .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
130 .FACTORY_JF(16'hF0F0), // FACTORY JF Values Suggested to be set to X"F0F0"
131 .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
132 .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
141 ODDR ODDR_dvi_d0 (dvi_d0, pix_clk, 1, dvi_green[4], dvi_blue[0], ~data_valid_ext, 0);
142 ODDR ODDR_dvi_d1 (dvi_d1, pix_clk, 1, dvi_green[5], dvi_blue[1], ~data_valid_ext, 0);
143 ODDR ODDR_dvi_d2 (dvi_d2, pix_clk, 1, dvi_green[6], dvi_blue[2], ~data_valid_ext, 0);
144 ODDR ODDR_dvi_d3 (dvi_d3, pix_clk, 1, dvi_green[7], dvi_blue[3], ~data_valid_ext, 0);
145 ODDR ODDR_dvi_d4 (dvi_d4, pix_clk, 1, dvi_red[0], dvi_blue[4], ~data_valid_ext, 0);
146 ODDR ODDR_dvi_d5 (dvi_d5, pix_clk, 1, dvi_red[1], dvi_blue[5], ~data_valid_ext, 0);
147 ODDR ODDR_dvi_d6 (dvi_d6, pix_clk, 1, dvi_red[2], dvi_blue[6], ~data_valid_ext, 0);
148 ODDR ODDR_dvi_d7 (dvi_d7, pix_clk, 1, dvi_red[3], dvi_blue[7], ~data_valid_ext, 0);
149 ODDR ODDR_dvi_d8 (dvi_d8, pix_clk, 1, dvi_red[4], dvi_green[0], ~data_valid_ext, 0);
150 ODDR ODDR_dvi_d9 (dvi_d9, pix_clk, 1, dvi_red[5], dvi_green[1], ~data_valid_ext, 0);
151 ODDR ODDR_dvi_d10 (dvi_d10, pix_clk, 1, dvi_red[6], dvi_green[2], ~data_valid_ext, 0);
152 ODDR ODDR_dvi_d11 (dvi_d11, pix_clk, 1, dvi_red[7], dvi_green[3], ~data_valid_ext, 0);
158 wire [18:0] vga_pixel_addr_;
159 reg [18:0] vga_pixel_addr;
161 assign inAddr = inX_d + { inY_d[8:0], 7'b0000000 } + { inY_d[8:0], 10'b0000000000 };
162 assign vga_pixel_addr_ = x_coord + { y_coord[8:0], 7'b0000000 } + { y_coord[8:0], 10'b0000000000 };
163 assign dvi_red = { mem_out[2], 7'b0 };
164 assign dvi_green = { mem_out[1], 7'b0 };
165 assign dvi_blue = { mem_out[0], 7'b0 };
167 vram vram(clk, ~rst, we,
173 always @(posedge pix_clk) begin
174 vga_pixel_addr <= vga_pixel_addr_;
177 always @(posedge clk) begin
184 if (`inX_full && `inY_full && `inData_full) begin
198 == UCF ===============================================================
200 #Net "dvi_0/dvi_xclk_p_unbuffered" PERIOD = 5 ns HIGH 50%;
202 NET dvi_d0 LOC="AB8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
203 NET dvi_d1 LOC="AC8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
204 NET dvi_d2 LOC="AN12" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
205 NET dvi_d3 LOC="AP12" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
206 NET dvi_d4 LOC="AA9" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
207 NET dvi_d5 LOC="AA8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
208 NET dvi_d6 LOC="AM13" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
209 NET dvi_d7 LOC="AN13" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
210 NET dvi_d8 LOC="AA10" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
211 NET dvi_d9 LOC="AB10" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
212 NET dvi_d10 LOC="AP14" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
213 NET dvi_d11 LOC="AN14" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
214 NET dvi_de LOC="AE8" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
215 NET dvi_reset_b LOC="AK6" | IOSTANDARD="LVCMOS33"; # Bank 18, Vcco=3.3V, No DCI
216 NET dvi_h LOC="AM12" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
217 NET dvi_v LOC="AM11" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
218 NET dvi_xclk_n LOC="AL10" | IOSTANDARD="LVCMOS33" | DRIVE=24 | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
219 NET dvi_xclk_p LOC="AL11" | IOSTANDARD="LVCMOS33" | DRIVE=24 | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
221 NET dvi_gpio1 LOC="N30" | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
222 NET dvi_iic_scl LOC="U27" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
223 NET dvi_iic_sda LOC="T29" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
225 NET gpio_sw_c LOC="AJ6" | IOSTANDARD="LVCMOS33"; # Bank 18, Vcco=3.3V, No DCI
227 NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
228 NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V
229 NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V
230 NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V
231 NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V
233 NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
234 NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
235 NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
236 NET gpio_led_3 LOC="AD26" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
237 NET gpio_led_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
238 NET gpio_led_5 LOC="AD25" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
239 NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
240 NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
242 == TeX ==============================================================
244 == Fleeterpreter ====================================================
246 public void service() { }
248 == FleetSim ==============================================================
250 == Constants =========================================================
252 == Test ==============================================================
264 send token to debug.in;
268 send token to debug.in;
272 send token to debug.in;
280 == Contributors =========================================================
281 Adam Megacz <megacz@cs.berkeley.edu>