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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_chipscope.v
50 // /___/ /\ Date Last Modified: $Data$
51 // \ \ / \ Date Created: 9/14/06
56 // Skeleton Chipscope module declarations - for simulation only
60 //*****************************************************************************
71 /* synthesis syn_black_box syn_noprune = 1 */;
72 output [35:0] control0;
73 output [35:0] control1;
74 output [35:0] control2;
75 output [35:0] control3;
78 module vio_async_in192
83 /* synthesis syn_black_box syn_noprune = 1 */;
85 input [191:0] async_in;
93 /* synthesis syn_black_box syn_noprune = 1 */;
95 input [95:0] async_in;
98 module vio_async_in100
103 /* synthesis syn_black_box syn_noprune = 1 */;
104 input [35:0] control;
105 input [99:0] async_in;
108 module vio_sync_out32
114 /* synthesis syn_black_box syn_noprune = 1 */;
115 input [35:0] control;
117 output [31:0] sync_out;