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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_sdram.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/09 12:33:12 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // Top-level module. Simple model for what the user might use
58 // Typically, the user will only instantiate MEM_INTERFACE_TOP in their
59 // code, and generate all backend logic (test bench) separately.
60 // In addition to the memory controller, the module instantiates:
61 // 1. Clock generation/distribution, reset logic
62 // 2. IDELAY control block
65 //*****************************************************************************
69 (* X_CORE_INFO = "mig_v2_3_ddr2_sdram_v5, Coregen 10.1.02" , CORE_GENERATION_INFO = "ddr2_sdram_v5,mig_v2_3,{component_name=ddr2_sdram, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=4, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=127500, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, DDR2_CLK_PERIOD=5000, RST_ACT_LOW=1}" *)
72 parameter BANK_WIDTH = 2,
73 // # of memory bank addr bits.
74 parameter CKE_WIDTH = 1,
75 // # of memory clock enable outputs.
76 parameter CLK_WIDTH = 2,
77 // # of clock outputs.
78 parameter COL_WIDTH = 10,
79 // # of memory column bits.
81 // # of separate memory chip selects.
82 parameter CS_WIDTH = 1,
83 // # of total memory chip selects.
84 parameter CS_BITS = 0,
85 // set to log2(CS_NUM) (rounded up).
86 parameter DM_WIDTH = 8,
87 // # of data mask bits.
88 parameter DQ_WIDTH = 64,
90 parameter DQ_PER_DQS = 8,
91 // # of DQ data bits per strobe.
92 parameter DQS_WIDTH = 8,
94 parameter DQ_BITS = 6,
95 // set to log2(DQS_WIDTH*DQ_PER_DQS).
96 parameter DQS_BITS = 3,
97 // set to log2(DQS_WIDTH).
98 parameter ODT_WIDTH = 1,
99 // # of memory on-die term enables.
100 parameter ROW_WIDTH = 13,
101 // # of memory row and # of addr bits.
102 parameter ADDITIVE_LAT = 0,
103 // additive write latency.
104 parameter BURST_LEN = 4,
105 // burst length (in double words).
106 parameter BURST_TYPE = 0,
107 // burst type (=0 seq; =1 interleaved).
108 parameter CAS_LAT = 4,
110 parameter ECC_ENABLE = 0,
111 // enable ECC (=1 enable).
112 parameter APPDATA_WIDTH = 128,
113 // # of usr read/write data bus bits.
114 parameter MULTI_BANK_EN = 1,
115 // Keeps multiple banks open. (= 1 enable).
116 parameter TWO_T_TIME_EN = 1,
117 // 2t timing for unbuffered dimms.
118 parameter ODT_TYPE = 1,
119 // ODT (=0(none),=1(75),=2(150),=3(50)).
120 parameter REDUCE_DRV = 0,
121 // reduced strength mem I/O (=1 yes).
122 parameter REG_ENABLE = 0,
123 // registered addr/ctrl (=1 yes).
124 parameter TREFI_NS = 7800,
125 // auto refresh interval (ns).
126 parameter TRAS = 40000,
127 // active->precharge delay.
128 parameter TRCD = 15000,
129 // active->read/write delay.
130 parameter TRFC = 127500,
131 // refresh->refresh, refresh->active delay.
132 parameter TRP = 15000,
133 // precharge->command delay.
134 parameter TRTP = 7500,
135 // read->precharge delay.
136 parameter TWR = 15000,
137 // used to determine write->precharge.
138 parameter TWTR = 7500,
139 // write->read delay.
140 parameter HIGH_PERFORMANCE_MODE = "TRUE",
141 // # = TRUE, the IODELAY performance mode is set
143 // # = FALSE, the IODELAY performance mode is set
145 parameter SIM_ONLY = 0,
146 // = 1 to skip SDRAM power up delay.
147 parameter DEBUG_EN = 0,
148 // Enable debug signals/controls.
149 // When this parameter is changed from 0 to 1,
150 // make sure to uncomment the coregen commands
151 // in ise_flow.bat or create_ise.bat files in
153 parameter CLK_PERIOD = 5000,
154 // Core/Memory clock period (in ps).
155 parameter DQS_IO_COL = 16'b0000000000000000,
156 // I/O column location of DQS groups
157 // (=0, left; =1 center, =2 right).
159 //parameter DQ_IO_MS = 64'b10100101_10100101_10100101_10100101_10100101_10100101_10100101_10100101,
160 parameter DQ_IO_MS = 64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100,
161 // Master/Slave location of DQ I/O (=0 slave).
162 parameter CLK_TYPE = "SINGLE_ENDED",
163 // # = "DIFFERENTIAL " ->; Differential input clocks ,
164 // # = "SINGLE_ENDED" -> Single ended input clocks.
165 parameter DLL_FREQ_MODE = "HIGH",
166 // DCM Frequency range.
167 parameter RST_ACT_LOW = 1
168 // =1 for active low reset, =0 for active high.
171 inout [DQ_WIDTH-1:0] ddr2_dq,
172 output [ROW_WIDTH-1:0] ddr2_a,
173 output [BANK_WIDTH-1:0] ddr2_ba,
177 output [CS_WIDTH-1:0] ddr2_cs_n,
178 output [ODT_WIDTH-1:0] ddr2_odt,
179 output [CKE_WIDTH-1:0] ddr2_cke,
180 output [DM_WIDTH-1:0] ddr2_dm,
184 output phy_init_done,
187 output app_wdf_afull,
189 output rd_data_valid,
192 input [30:0] app_af_addr,
193 input [2:0] app_af_cmd,
194 output [(APPDATA_WIDTH)-1:0] rd_data_fifo_out,
195 input [(APPDATA_WIDTH)-1:0] app_wdf_data,
196 input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
197 inout [DQS_WIDTH-1:0] ddr2_dqs,
198 inout [DQS_WIDTH-1:0] ddr2_dqs_n,
199 output [CLK_WIDTH-1:0] ddr2_ck,
200 output [CLK_WIDTH-1:0] ddr2_ck_n
203 /////////////////////////////////////////////////////////////////////////////
204 // The following parameter "IDELAYCTRL_NUM" indicates the number of
205 // IDELAYCTRLs that are LOCed for the design. The IDELAYCTRL LOCs are
206 // provided in the UCF file of par folder. MIG provides the parameter value
207 // and the LOCs in the UCF file based on the selected Data Read banks for
208 // the design. You must not alter this value unless it is needed. If you
209 // modify this value, you should make sure that the value of "IDELAYCTRL_NUM"
210 // and IDELAYCTRL LOCs in UCF file are same and are relavent to the Data Read
212 /////////////////////////////////////////////////////////////////////////////
214 localparam IDELAYCTRL_NUM = 3;
232 wire idelay_ctrl_rdy;
238 wire [3:0] dbg_calib_done;
239 wire [3:0] dbg_calib_err;
240 wire [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt;
241 wire [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt;
242 wire [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt;
243 wire [DQS_WIDTH-1:0] dbg_calib_rd_data_sel;
244 wire [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly;
245 wire [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly;
246 wire dbg_idel_up_all;
247 wire dbg_idel_down_all;
249 wire dbg_idel_down_dq;
250 wire dbg_idel_up_dqs;
251 wire dbg_idel_down_dqs;
252 wire dbg_idel_up_gate;
253 wire dbg_idel_down_gate;
254 wire [DQ_BITS-1:0] dbg_sel_idel_dq;
255 wire dbg_sel_all_idel_dq;
256 wire [DQS_BITS:0] dbg_sel_idel_dqs;
257 wire dbg_sel_all_idel_dqs;
258 wire [DQS_BITS:0] dbg_sel_idel_gate;
259 wire dbg_sel_all_idel_gate;
262 // Debug signals (optional use)
264 //***********************************
265 // PHY Debug Port demo
266 //***********************************
267 wire [35:0] cs_control0;
268 wire [35:0] cs_control1;
269 wire [35:0] cs_control2;
270 wire [35:0] cs_control3;
271 wire [191:0] vio0_in;
274 wire [31:0] vio3_out;
278 //***************************************************************************
280 assign rst0_tb = rst0;
281 assign clk0_tb = clk0;
282 assign sys_clk_p = 1'b1;
283 assign sys_clk_n = 1'b0;
284 assign clk200_p = 1'b1;
285 assign clk200_n = 1'b0;
289 .IDELAYCTRL_NUM (IDELAYCTRL_NUM)
295 .idelay_ctrl_rdy (idelay_ctrl_rdy)
298 ddr2_infrastructure #
300 .CLK_PERIOD (CLK_PERIOD),
301 .CLK_TYPE (CLK_TYPE),
302 .DLL_FREQ_MODE (DLL_FREQ_MODE),
303 .RST_ACT_LOW (RST_ACT_LOW)
305 u_ddr2_infrastructure
307 .sys_clk_p (sys_clk_p),
308 .sys_clk_n (sys_clk_n),
310 .clk200_p (clk200_p),
311 .clk200_n (clk200_n),
312 .idly_clk_200 (idly_clk_200),
313 .sys_rst_n (sys_rst_n),
322 .idelay_ctrl_rdy (idelay_ctrl_rdy)
327 .BANK_WIDTH (BANK_WIDTH),
328 .CKE_WIDTH (CKE_WIDTH),
329 .CLK_WIDTH (CLK_WIDTH),
330 .COL_WIDTH (COL_WIDTH),
332 .CS_WIDTH (CS_WIDTH),
334 .DM_WIDTH (DM_WIDTH),
335 .DQ_WIDTH (DQ_WIDTH),
336 .DQ_PER_DQS (DQ_PER_DQS),
337 .DQS_WIDTH (DQS_WIDTH),
339 .DQS_BITS (DQS_BITS),
340 .ODT_WIDTH (ODT_WIDTH),
341 .ROW_WIDTH (ROW_WIDTH),
342 .ADDITIVE_LAT (ADDITIVE_LAT),
343 .BURST_LEN (BURST_LEN),
344 .BURST_TYPE (BURST_TYPE),
346 .ECC_ENABLE (ECC_ENABLE),
347 .APPDATA_WIDTH (APPDATA_WIDTH),
348 .MULTI_BANK_EN (MULTI_BANK_EN),
349 .TWO_T_TIME_EN (TWO_T_TIME_EN),
350 .ODT_TYPE (ODT_TYPE),
351 .REDUCE_DRV (REDUCE_DRV),
352 .REG_ENABLE (REG_ENABLE),
353 .TREFI_NS (TREFI_NS),
361 .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
362 .SIM_ONLY (SIM_ONLY),
363 .DEBUG_EN (DEBUG_EN),
364 .CLK_PERIOD (CLK_PERIOD),
365 .DQS_IO_COL (DQS_IO_COL),
366 .DQ_IO_MS (DQ_IO_MS),
374 .ddr2_ras_n (ddr2_ras_n),
375 .ddr2_cas_n (ddr2_cas_n),
376 .ddr2_we_n (ddr2_we_n),
377 .ddr2_cs_n (ddr2_cs_n),
378 .ddr2_odt (ddr2_odt),
379 .ddr2_cke (ddr2_cke),
381 .phy_init_done (phy_init_done),
388 .app_wdf_afull (app_wdf_afull),
389 .app_af_afull (app_af_afull),
390 .rd_data_valid (rd_data_valid),
391 .app_wdf_wren (app_wdf_wren),
392 .app_af_wren (app_af_wren),
393 .app_af_addr (app_af_addr),
394 .app_af_cmd (app_af_cmd),
395 .rd_data_fifo_out (rd_data_fifo_out),
396 .app_wdf_data (app_wdf_data),
397 .app_wdf_mask_data (app_wdf_mask_data),
398 .ddr2_dqs (ddr2_dqs),
399 .ddr2_dqs_n (ddr2_dqs_n),
402 .ddr2_ck_n (ddr2_ck_n),
404 .dbg_calib_done (dbg_calib_done),
405 .dbg_calib_err (dbg_calib_err),
406 .dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
407 .dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
408 .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
409 .dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
410 .dbg_calib_rden_dly (dbg_calib_rden_dly),
411 .dbg_calib_gate_dly (dbg_calib_gate_dly),
412 .dbg_idel_up_all (dbg_idel_up_all),
413 .dbg_idel_down_all (dbg_idel_down_all),
414 .dbg_idel_up_dq (dbg_idel_up_dq),
415 .dbg_idel_down_dq (dbg_idel_down_dq),
416 .dbg_idel_up_dqs (dbg_idel_up_dqs),
417 .dbg_idel_down_dqs (dbg_idel_down_dqs),
418 .dbg_idel_up_gate (dbg_idel_up_gate),
419 .dbg_idel_down_gate (dbg_idel_down_gate),
420 .dbg_sel_idel_dq (dbg_sel_idel_dq),
421 .dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
422 .dbg_sel_idel_dqs (dbg_sel_idel_dqs),
423 .dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
424 .dbg_sel_idel_gate (dbg_sel_idel_gate),
425 .dbg_sel_all_idel_gate (dbg_sel_all_idel_gate)
429 //*****************************************************************
430 // Hooks to prevent sim/syn compilation errors (mainly for VHDL - but
431 // keep it also in Verilog version of code) w/ floating inputs if
433 //*****************************************************************
436 if (DEBUG_EN == 0) begin: gen_dbg_tie_off
437 assign dbg_idel_up_all = 'b0;
438 assign dbg_idel_down_all = 'b0;
439 assign dbg_idel_up_dq = 'b0;
440 assign dbg_idel_down_dq = 'b0;
441 assign dbg_idel_up_dqs = 'b0;
442 assign dbg_idel_down_dqs = 'b0;
443 assign dbg_idel_up_gate = 'b0;
444 assign dbg_idel_down_gate = 'b0;
445 assign dbg_sel_idel_dq = 'b0;
446 assign dbg_sel_all_idel_dq = 'b0;
447 assign dbg_sel_idel_dqs = 'b0;
448 assign dbg_sel_all_idel_dqs = 'b0;
449 assign dbg_sel_idel_gate = 'b0;
450 assign dbg_sel_all_idel_gate = 'b0;
451 end else begin: gen_dbg_enable
453 //*****************************************************************
454 // PHY Debug Port example - see MIG User's Guide, XAPP858 or
455 // Answer Record 29443
456 // This logic supports up to 32 DQ and 8 DQS I/O
458 // 1. PHY Debug Port demo connects to 4 VIO modules:
459 // - 3 VIO modules with only asynchronous inputs
460 // * Monitor IDELAY taps for DQ, DQS, DQS Gate
461 // * Calibration status
462 // - 1 VIO module with synchronous outputs
463 // * Allow dynamic adjustment o f IDELAY taps
464 // 2. User may need to modify this code to incorporate other
465 // chipscope-related modules in their larger design (e.g.
466 // if they have other ILA/VIO modules, they will need to
467 // for example instantiate a larger ICON module). In addition
468 // user may want to instantiate more VIO modules to control
469 // IDELAY for more DQ, DQS than is shown here
470 //*****************************************************************
474 .control0 (cs_control0),
475 .control1 (cs_control1),
476 .control2 (cs_control2),
477 .control3 (cs_control3)
480 //*****************************************************************
481 // VIO ASYNC input: Display current IDELAY setting for up to 32
482 // DQ taps (32x6) = 192
483 //*****************************************************************
485 vio_async_in192 u_vio0
487 .control (cs_control0),
491 //*****************************************************************
492 // VIO ASYNC input: Display current IDELAY setting for up to 8 DQS
493 // and DQS Gate taps (8x6x2) = 96
494 //*****************************************************************
496 vio_async_in96 u_vio1
498 .control (cs_control1),
502 //*****************************************************************
503 // VIO ASYNC input: Display other calibration results
504 //*****************************************************************
506 vio_async_in100 u_vio2
508 .control (cs_control2),
512 //*****************************************************************
513 // VIO SYNC output: Dynamically change IDELAY taps
514 //*****************************************************************
516 vio_sync_out32 u_vio3
518 .control (cs_control3),
523 //*****************************************************************
525 // NOTE: Not all VIO, ILA inputs/outputs may be used - these will
526 // be dependent on the user's particular bit width
527 //*****************************************************************
529 if (DQ_WIDTH <= 32) begin: gen_dq_le_32
530 assign vio0_in[(6*DQ_WIDTH)-1:0]
531 = dbg_calib_dq_tap_cnt[(6*DQ_WIDTH)-1:0];
532 end else begin: gen_dq_gt_32
533 assign vio0_in = dbg_calib_dq_tap_cnt[191:0];
536 if (DQS_WIDTH <= 8) begin: gen_dqs_le_8
537 assign vio1_in[(6*DQS_WIDTH)-1:0]
538 = dbg_calib_dqs_tap_cnt[(6*DQS_WIDTH)-1:0];
539 assign vio1_in[(12*DQS_WIDTH)-1:(6*DQS_WIDTH)]
540 = dbg_calib_gate_tap_cnt[(6*DQS_WIDTH)-1:0];
541 end else begin: gen_dqs_gt_32
542 assign vio1_in[47:0] = dbg_calib_dqs_tap_cnt[47:0];
543 assign vio1_in[95:48] = dbg_calib_gate_tap_cnt[47:0];
546 //dbg_calib_rd_data_sel
548 if (DQS_WIDTH <= 8) begin: gen_rdsel_le_8
549 assign vio2_in[(DQS_WIDTH)+7:8]
550 = dbg_calib_rd_data_sel[(DQS_WIDTH)-1:0];
551 end else begin: gen_rdsel_gt_32
553 = dbg_calib_rd_data_sel[7:0];
558 if (DQS_WIDTH <= 8) begin: gen_calrd_le_8
559 assign vio2_in[(5*DQS_WIDTH)+19:20]
560 = dbg_calib_rden_dly[(5*DQS_WIDTH)-1:0];
561 end else begin: gen_calrd_gt_32
562 assign vio2_in[59:20]
563 = dbg_calib_rden_dly[39:0];
568 if (DQS_WIDTH <= 8) begin: gen_calgt_le_8
569 assign vio2_in[(5*DQS_WIDTH)+59:60]
570 = dbg_calib_gate_dly[(5*DQS_WIDTH)-1:0];
571 end else begin: gen_calgt_gt_32
572 assign vio2_in[99:60]
573 = dbg_calib_gate_dly[39:0];
578 if (DQ_BITS <= 5) begin: gen_selid_le_5
579 assign dbg_sel_idel_dq[DQ_BITS-1:0]
580 = vio3_out[DQ_BITS+7:8];
581 end else begin: gen_selid_gt_32
582 assign dbg_sel_idel_dq[4:0]
588 if (DQS_BITS <= 3) begin: gen_seldqs_le_3
589 assign dbg_sel_idel_dqs[DQS_BITS:0]
590 = vio3_out[(DQS_BITS+16):16];
591 end else begin: gen_seldqs_gt_32
592 assign dbg_sel_idel_dqs[3:0]
598 if (DQS_BITS <= 3) begin: gen_gtdqs_le_3
599 assign dbg_sel_idel_gate[DQS_BITS:0]
600 = vio3_out[(DQS_BITS+21):21];
601 end else begin: gen_gtdqs_gt_32
602 assign dbg_sel_idel_gate[3:0]
607 assign vio2_in[3:0] = dbg_calib_done;
608 assign vio2_in[7:4] = dbg_calib_err;
610 assign dbg_idel_up_all = vio3_out[0];
611 assign dbg_idel_down_all = vio3_out[1];
612 assign dbg_idel_up_dq = vio3_out[2];
613 assign dbg_idel_down_dq = vio3_out[3];
614 assign dbg_idel_up_dqs = vio3_out[4];
615 assign dbg_idel_down_dqs = vio3_out[5];
616 assign dbg_idel_up_gate = vio3_out[6];
617 assign dbg_idel_down_gate = vio3_out[7];
618 assign dbg_sel_all_idel_dq = vio3_out[15];
619 assign dbg_sel_all_idel_dqs = vio3_out[20];
620 assign dbg_sel_all_idel_gate = vio3_out[25];