src/edu/berkeley/fleet/fpga/ddr2/ddr2_top.v

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  44 //   ____  ____
  45 //  /   /\/   /
  46 // /___/  \  /    Vendor: Xilinx
  47 // \   \   \/     Version: 2.3
  48 //  \   \         Application: MIG
  49 //  /   /         Filename: ddr2_top.v
  50 // /___/   /\     Date Last Modified: $Date: 2008/07/29 15:24:03 $
  51 // \   \  /  \    Date Created: Wed Aug 16 2006
  52 //  \___\/\___\
  53 //
  54 //Device: Virtex-5
  55 //Design Name: DDR2
  56 //Purpose:
  57 //   System level module. This level contains just the memory controller.
  58 //   This level will be intiantated when the user wants to remove the
  59 //   synthesizable test bench, IDELAY control block and the clock
  60 //   generation modules.
  61 //Reference:
  62 //Revision History:
  63 //*****************************************************************************
  64
  65 `timescale 1ns/1ps
  66
  67 module ddr2_top #
  68   (
  69    // Following parameters are for 72-bit RDIMM design (for ML561 Reference
  70    // board design). Actual values may be different. Actual parameters values
  71    // are passed from design top module ddr2_sdram module. Please refer to
  72    // the ddr2_sdram module for actual values.
  73    parameter BANK_WIDTH            = 2,      // # of memory bank addr bits
  74    parameter CKE_WIDTH             = 1,      // # of memory clock enable outputs
  75    parameter CLK_WIDTH             = 1,      // # of clock outputs
  76    parameter COL_WIDTH             = 10,     // # of memory column bits
  77    parameter CS_NUM                = 1,      // # of separate memory chip selects
  78    parameter CS_BITS               = 0,      // set to log2(CS_NUM) (rounded up)
  79    parameter CS_WIDTH              = 1,      // # of total memory chip selects
  80    parameter USE_DM_PORT           = 1,      // enable Data Mask (=1 enable)
  81    parameter DM_WIDTH              = 9,      // # of data mask bits
  82    parameter DQ_WIDTH              = 72,     // # of data width
  83    parameter DQ_BITS               = 7,      // set to log2(DQS_WIDTH*DQ_PER_DQS)
  84    parameter DQ_PER_DQS            = 8,      // # of DQ data bits per strobe
  85    parameter DQS_WIDTH             = 9,      // # of DQS strobes
  86    parameter DQS_BITS              = 4,      // set to log2(DQS_WIDTH)
  87    parameter HIGH_PERFORMANCE_MODE = "TRUE", // IODELAY Performance Mode
  88    parameter ODT_WIDTH             = 1,      // # of memory on-die term enables
  89    parameter ROW_WIDTH             = 14,     // # of memory row & # of addr bits
  90    parameter APPDATA_WIDTH         = 144,    // # of usr read/write data bus bits
  91    parameter ADDITIVE_LAT          = 0,      // additive write latency
  92    parameter BURST_LEN             = 4,      // burst length (in double words)
  93    parameter BURST_TYPE            = 0,      // burst type (=0 seq; =1 interlved)
  94    parameter CAS_LAT               = 5,      // CAS latency
  95    parameter ECC_ENABLE            = 0,      // enable ECC (=1 enable)
  96    parameter ODT_TYPE              = 1,      // ODT (=0(none),=1(75),=2(150),=3(50))
  97    parameter MULTI_BANK_EN         = 1,      // enable bank management
  98    parameter TWO_T_TIME_EN         = 0,      // 2t timing for unbuffered dimms
  99    parameter REDUCE_DRV            = 0,      // reduced strength mem I/O (=1 yes)
 100    parameter REG_ENABLE            = 1,      // registered addr/ctrl (=1 yes)
 101    parameter TREFI_NS              = 7800,   // auto refresh interval (ns)
 102    parameter TRAS                  = 40000,  // active->precharge delay
 103    parameter TRCD                  = 15000,  // active->read/write delay
 104    parameter TRFC                  = 105000, // ref->ref, ref->active delay
 105    parameter TRP                   = 15000,  // precharge->command delay
 106    parameter TRTP                  = 7500,   // read->precharge delay
 107    parameter TWR                   = 15000,  // used to determine wr->prech
 108    parameter TWTR                  = 10000,  // write->read delay
 109    parameter CLK_PERIOD            = 3000,   // Core/Mem clk period (in ps)
 110    parameter SIM_ONLY              = 0,      // = 1 to skip power up delay
 111    parameter DEBUG_EN              = 0,      // Enable debug signals/controls
 112    parameter DQS_IO_COL            = 0,      // I/O column location of DQS groups
 113    parameter DQ_IO_MS              = 0       // Master/Slave location of DQ I/O
 114    )
 115   (
 116    input                                    clk0,
 117    input                                    clk90,
 118    input                                    clkdiv0,
 119    input                                    rst0,
 120    input                                    rst90,
 121    input                                    rstdiv0,
 122    input [2:0]                              app_af_cmd,
 123    input [30:0]                             app_af_addr,
 124    input                                    app_af_wren,
 125    input                                    app_wdf_wren,
 126    input [APPDATA_WIDTH-1:0]                app_wdf_data,
 127    input [(APPDATA_WIDTH/8)-1:0]            app_wdf_mask_data,
 128    output                                   app_af_afull,
 129    output                                   app_wdf_afull,
 130    output                                   rd_data_valid,
 131    output [APPDATA_WIDTH-1:0]               rd_data_fifo_out,
 132    output [1:0]                             rd_ecc_error,
 133    output                                   phy_init_done,
 134    output [CLK_WIDTH-1:0]                   ddr2_ck,
 135    output [CLK_WIDTH-1:0]                   ddr2_ck_n,
 136    output [ROW_WIDTH-1:0]                   ddr2_a,
 137    output [BANK_WIDTH-1:0]                  ddr2_ba,
 138    output                                   ddr2_ras_n,
 139    output                                   ddr2_cas_n,
 140    output                                   ddr2_we_n,
 141    output [CS_WIDTH-1:0]                    ddr2_cs_n,
 142    output [CKE_WIDTH-1:0]                   ddr2_cke,
 143    output [ODT_WIDTH-1:0]                   ddr2_odt,
 144    output [DM_WIDTH-1:0]                    ddr2_dm,
 145    inout [DQS_WIDTH-1:0]                    ddr2_dqs,
 146    inout [DQS_WIDTH-1:0]                    ddr2_dqs_n,
 147    inout [DQ_WIDTH-1:0]                     ddr2_dq,
 148    // Debug signals (optional use)
 149    input                                    dbg_idel_up_all,
 150    input                                    dbg_idel_down_all,
 151    input                                    dbg_idel_up_dq,
 152    input                                    dbg_idel_down_dq,
 153    input                                    dbg_idel_up_dqs,
 154    input                                    dbg_idel_down_dqs,
 155    input                                    dbg_idel_up_gate,
 156    input                                    dbg_idel_down_gate,
 157    input [DQ_BITS-1:0]                      dbg_sel_idel_dq,
 158    input                                    dbg_sel_all_idel_dq,
 159    input [DQS_BITS:0]                       dbg_sel_idel_dqs,
 160    input                                    dbg_sel_all_idel_dqs,
 161    input [DQS_BITS:0]                       dbg_sel_idel_gate,
 162    input                                    dbg_sel_all_idel_gate,
 163    output [3:0]                             dbg_calib_done,
 164    output [3:0]                             dbg_calib_err,
 165    output [(6*DQ_WIDTH)-1:0]                dbg_calib_dq_tap_cnt,
 166    output [(6*DQS_WIDTH)-1:0]               dbg_calib_dqs_tap_cnt,
 167    output [(6*DQS_WIDTH)-1:0]               dbg_calib_gate_tap_cnt,
 168    output [DQS_WIDTH-1:0]                   dbg_calib_rd_data_sel,
 169    output [(5*DQS_WIDTH)-1:0]               dbg_calib_rden_dly,
 170    output [(5*DQS_WIDTH)-1:0]               dbg_calib_gate_dly
 171    );
 172
 173   // memory initialization/control logic
 174   ddr2_mem_if_top #
 175     (
 176      .BANK_WIDTH            (BANK_WIDTH),
 177      .CKE_WIDTH             (CKE_WIDTH),
 178      .CLK_WIDTH             (CLK_WIDTH),
 179      .COL_WIDTH             (COL_WIDTH),
 180      .CS_BITS               (CS_BITS),
 181      .CS_NUM                (CS_NUM),
 182      .CS_WIDTH              (CS_WIDTH),
 183      .USE_DM_PORT           (USE_DM_PORT),
 184      .DM_WIDTH              (DM_WIDTH),
 185      .DQ_WIDTH              (DQ_WIDTH),
 186      .DQ_BITS               (DQ_BITS),
 187      .DQ_PER_DQS            (DQ_PER_DQS),
 188      .DQS_BITS              (DQS_BITS),
 189      .DQS_WIDTH             (DQS_WIDTH),
 190      .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
 191      .ODT_WIDTH             (ODT_WIDTH),
 192      .ROW_WIDTH             (ROW_WIDTH),
 193      .APPDATA_WIDTH         (APPDATA_WIDTH),
 194      .ADDITIVE_LAT          (ADDITIVE_LAT),
 195      .BURST_LEN             (BURST_LEN),
 196      .BURST_TYPE            (BURST_TYPE),
 197      .CAS_LAT               (CAS_LAT),
 198      .ECC_ENABLE            (ECC_ENABLE),
 199      .MULTI_BANK_EN         (MULTI_BANK_EN),
 200      .TWO_T_TIME_EN         (TWO_T_TIME_EN),
 201      .ODT_TYPE              (ODT_TYPE),
 202      .DDR_TYPE              (1),
 203      .REDUCE_DRV            (REDUCE_DRV),
 204      .REG_ENABLE            (REG_ENABLE),
 205      .TREFI_NS              (TREFI_NS),
 206      .TRAS                  (TRAS),
 207      .TRCD                  (TRCD),
 208      .TRFC                  (TRFC),
 209      .TRP                   (TRP),
 210      .TRTP                  (TRTP),
 211      .TWR                   (TWR),
 212      .TWTR                  (TWTR),
 213      .CLK_PERIOD            (CLK_PERIOD),
 214      .SIM_ONLY              (SIM_ONLY),
 215      .DEBUG_EN              (DEBUG_EN),
 216      .DQS_IO_COL            (DQS_IO_COL),
 217      .DQ_IO_MS              (DQ_IO_MS)
 218      )
 219     u_mem_if_top
 220       (
 221        .clk0                   (clk0),
 222        .clk90                  (clk90),
 223        .clkdiv0                (clkdiv0),
 224        .rst0                   (rst0),
 225        .rst90                  (rst90),
 226        .rstdiv0                (rstdiv0),
 227        .app_af_cmd             (app_af_cmd),
 228        .app_af_addr            (app_af_addr),
 229        .app_af_wren            (app_af_wren),
 230        .app_wdf_wren           (app_wdf_wren),
 231        .app_wdf_data           (app_wdf_data),
 232        .app_wdf_mask_data      (app_wdf_mask_data),
 233        .app_af_afull           (app_af_afull),
 234        .app_wdf_afull          (app_wdf_afull),
 235        .rd_data_valid          (rd_data_valid),
 236        .rd_data_fifo_out       (rd_data_fifo_out),
 237        .rd_ecc_error           (rd_ecc_error),
 238        .phy_init_done          (phy_init_done),
 239        .ddr_ck                 (ddr2_ck),
 240        .ddr_ck_n               (ddr2_ck_n),
 241        .ddr_addr               (ddr2_a),
 242        .ddr_ba                 (ddr2_ba),
 243        .ddr_ras_n              (ddr2_ras_n),
 244        .ddr_cas_n              (ddr2_cas_n),
 245        .ddr_we_n               (ddr2_we_n),
 246        .ddr_cs_n               (ddr2_cs_n),
 247        .ddr_cke                (ddr2_cke),
 248        .ddr_odt                (ddr2_odt),
 249        .ddr_dm                 (ddr2_dm),
 250        .ddr_dqs                (ddr2_dqs),
 251        .ddr_dqs_n              (ddr2_dqs_n),
 252        .ddr_dq                 (ddr2_dq),
 253        .dbg_idel_up_all        (dbg_idel_up_all),
 254        .dbg_idel_down_all      (dbg_idel_down_all),
 255        .dbg_idel_up_dq         (dbg_idel_up_dq),
 256        .dbg_idel_down_dq       (dbg_idel_down_dq),
 257        .dbg_idel_up_dqs        (dbg_idel_up_dqs),
 258        .dbg_idel_down_dqs      (dbg_idel_down_dqs),
 259        .dbg_idel_up_gate       (dbg_idel_up_gate),
 260        .dbg_idel_down_gate     (dbg_idel_down_gate),
 261        .dbg_sel_idel_dq        (dbg_sel_idel_dq),
 262        .dbg_sel_all_idel_dq    (dbg_sel_all_idel_dq),
 263        .dbg_sel_idel_dqs       (dbg_sel_idel_dqs),
 264        .dbg_sel_all_idel_dqs   (dbg_sel_all_idel_dqs),
 265        .dbg_sel_idel_gate      (dbg_sel_idel_gate),
 266        .dbg_sel_all_idel_gate  (dbg_sel_all_idel_gate),
 267        .dbg_calib_done         (dbg_calib_done),
 268        .dbg_calib_err          (dbg_calib_err),
 269        .dbg_calib_dq_tap_cnt   (dbg_calib_dq_tap_cnt),
 270        .dbg_calib_dqs_tap_cnt  (dbg_calib_dqs_tap_cnt),
 271        .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
 272        .dbg_calib_rd_data_sel  (dbg_calib_rd_data_sel),
 273        .dbg_calib_rden_dly     (dbg_calib_rden_dly),
 274        .dbg_calib_gate_dly     (dbg_calib_gate_dly)
 275        );
 276
 277 endmodule