src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* I think this is 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin
   9  );
  10
  11   input  sys_clk_pin;
  12   input  sys_rst_pin;
  13   input  fpga_0_RS232_Uart_1_ctsN_pin;
  14   output fpga_0_RS232_Uart_1_rtsN_pin;
  15   input  fpga_0_RS232_Uart_1_sin_pin;
  16   output fpga_0_RS232_Uart_1_sout_pin;
  17
  18   wire clk;
  19   assign clk = sys_clk_pin;
  20   wire rst;
  21   assign rst = sys_rst_pin;
  22
  23   wire       data_to_host_full;
  24   wire       data_to_host_write_enable;
  25   wire [7:0] data_to_host;
  26
  27   wire       data_to_fleet_empty;
  28   wire       data_to_fleet_read_enable;
  29   wire [7:0] data_to_fleet;
  30
  31   reg we;
  32   reg re;
  33   reg [7:0] data_to_host_r;
  34
  35 /*
  36   assign data_to_host              = data_to_host_r;
  37   assign data_to_host_write_enable = we;
  38   assign data_to_fleet_read_enable = re;
  39
  40   reg [7:0] count;
  41   initial count = 0;
  42   initial we = 0;
  43   initial re = 0;
  44   initial data_to_host_r = 107;
  45   always @(posedge clk) begin
  46     if (re && !data_to_fleet_empty) begin
  47       data_to_host_r <= data_to_fleet;
  48       we <= 1;
  49     end else begin
  50       we <= 0;
  51     end
  52     if (data_to_host_full || data_to_fleet_empty) begin
  53       re <= 0;
  54     end else begin
  55       re <= 1;
  56     end
  57   end
  58 */
  59
  60   wire ser_rst;
  61   reg ser_rst_r;
  62   initial ser_rst_r = 0;
  63   assign ser_rst = rst & ser_rst_r;
  64
  65   wire sio_ce;
  66   wire sio_ce_x4;
  67   sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
  68   sasc_top sasc_top(clk, ser_rst,
  69                     fpga_0_RS232_Uart_1_sin_pin,
  70                     fpga_0_RS232_Uart_1_sout_pin,
  71                     fpga_0_RS232_Uart_1_ctsN_pin,
  72                     fpga_0_RS232_Uart_1_rtsN_pin,
  73                     sio_ce,
  74                     sio_ce_x4,
  75                     data_to_host,
  76                     data_to_fleet,
  77                     data_to_fleet_read_enable,
  78                     data_to_host_write_enable,
  79                     data_to_host_full,
  80                     data_to_fleet_empty);
  81
  82    reg data_to_host_write_enable_reg;
  83    reg data_to_fleet_read_enable_reg;
  84
  85    reg root_out_a_reg;
  86    reg root_in_r_reg;
  87    reg [7:0] root_in_d_reg;
  88    wire root_in_a;
  89    wire root_in_r;
  90    wire root_out_a;
  91    wire root_out_r;
  92    wire [7:0] root_in_d;
  93
  94    root my_root(clk, rst,
  95                 root_in_r,  root_in_a,  root_in_d,
  96                 root_out_r, root_out_a, data_to_host);
  97 /*
  98    fifo4 my_root(clk,
  99                 root_in_r,  root_in_a,  root_in_d,
 100                 root_out_r, root_out_a, data_to_host);
 101 */
 102    assign root_out_a                = root_out_a_reg;
 103    assign root_in_r                 = root_in_r_reg;
 104    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
 105    assign data_to_host_write_enable = data_to_host_write_enable_reg;
 106    assign root_in_d                 = root_in_d_reg;
 107
 108    // fpga -> host
 109    always @(posedge clk)
 110    begin
 111      data_to_host_write_enable_reg = 0;
 112      if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
 113        data_to_host_write_enable_reg = 1;
 114        root_out_a_reg = 1;
 115      end else if (root_out_a_reg && !root_out_r) begin
 116        root_out_a_reg = 0;
 117      end
 118    end
 119
 120    // awful hack to flush the superfluous null byte that seems to appear on bootup
 121    reg [15:0] boot_counter;
 122
 123    // host -> fpga
 124    always @(posedge clk)
 125    begin
 126      ser_rst_r <= 1;
 127 /*
 128      if (boot_counter != 500) begin
 129        data_to_fleet_read_enable_reg = 1;
 130        if (sio_ce) begin
 131          boot_counter <= boot_counter + 1;
 132        end
 133      end else begin
 134 */
 135        data_to_fleet_read_enable_reg = 0;
 136        if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 137           root_in_r_reg = 1;
 138           root_in_d_reg = data_to_fleet;
 139           data_to_fleet_read_enable_reg = 1;
 140        end else begin
 141           if (root_in_a) begin
 142             root_in_r_reg = 0;
 143           end
 144        end
 145 /*
 146      end
 147 */
 148    end
 149
 150    initial
 151    begin
 152      boot_counter = 0;
 153      root_in_r_reg = 0;
 154      root_in_d_reg = 0;
 155      root_out_a_reg = 0;
 156      data_to_fleet_read_enable_reg = 0;
 157      data_to_host_write_enable_reg = 0;
 158    end
 159 endmodule
 160
 161