3 module execute (clk, command_r, command_a_, command_d,
4 ihorn_r_, ihorn_a, ihorn_d_,
5 dhorn_r_, dhorn_a, dhorn_d_
9 `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d)
10 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
11 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
12 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
13 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
18 always @(posedge clk) begin
20 `onwrite(ihorn_r, ihorn_a)
23 end else if (dhorn_full) begin
24 `onwrite(dhorn_r, dhorn_a)
28 `onread(command_r, command_a)
29 case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
37 `packet_data(dhorn_d) = command_d[23:0];
38 `packet_dest(dhorn_d) = command_d[34:24];