build/main.bit: build/fabric.v $(verilog_files)
make fleet.jar
+ for A in `find ships -name \*.ship`;\
+ do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
+ done
rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}'
scp ${host}:${remote_dir}/build/main.bit build/
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+
+module alu1 (clk,
+ a_r, a_a_, a_d,
+ op_r, op_a_, op_d,
+ out_r_, out_a, out_d_);
+
+ input clk;
+ `input(a_r, a_a, a_a_, [(`DATAWIDTH-1):0], a_d)
+ `input(op_r, op_a, op_a_, [(`DATAWIDTH-1):0], op_d)
+ `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+ `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+
+ reg have_a;
+ reg [(`DATAWIDTH-1):0] reg_a;
+ reg have_op;
+ reg [(`DATAWIDTH-1):0] reg_op;
+
+ always @(posedge clk) begin
+ if (!have_a) begin
+ `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+ end
+ if (!have_op) begin
+ `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+ end
+
+ if (have_a && have_op) begin
+ case (reg_op)
+ 0: out_d = -reg_a;
+ 1: out_d = reg_a+1;
+ 2: out_d = reg_a-1;
+ 3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
+ default: out_d = 0;
+ endcase
+ `onwrite(out_r, out_a)
+ have_a = 0;
+ have_op = 0;
+ end
+ end
+ end
+
+endmodule
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+
+module alu2 (clk,
+ a_r, a_a_, a_d,
+ b_r, b_a_, b_d,
+ op_r, op_a_, op_d,
+ out_r_, out_a, out_d_);
+
+ input clk;
+ `input(a_r, a_a, a_a_, [(`DATAWIDTH-1):0], a_d)
+ `input(b_r, b_a, b_a_, [(`DATAWIDTH-1):0], b_d)
+ `input(op_r, op_a, op_a_, [(`DATAWIDTH-1):0], op_d)
+ `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+ `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+
+ reg have_a;
+ reg [(`DATAWIDTH-1):0] reg_a;
+ reg have_b;
+ reg [(`DATAWIDTH-1):0] reg_b;
+ reg have_op;
+ reg [(`DATAWIDTH-1):0] reg_op;
+
+ always @(posedge clk) begin
+ if (!have_a) begin
+ `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+ end
+ if (!have_b) begin
+ `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
+ end
+ if (!have_op) begin
+ `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+ end
+
+ if (have_a && have_b && have_op) begin
+ case (reg_op)
+ 0: out_d = reg_a + reg_b;
+ 1: out_d = reg_a - reg_b;
+ //2: out_d = reg_a * reg_b; // will not synthesize --AM
+ //3: out_d = reg_a / reg_b; // will not synthesize --AM
+ //4: out_d = reg_a % reg_b; // will not synthesize --AM
+ default: out_d = 0;
+ endcase
+ `onwrite(out_r, out_a)
+ have_a = 0;
+ have_b = 0;
+ have_op = 0;
+ end
+ end
+ end
+
+endmodule
+
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+
+module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data,
+ data_debug_out_r, data_debug_out_a, data_debug_out );
+ input clk;
+
+ input data_debug_data_r;
+ output data_debug_data_a;
+ input [`DATAWIDTH:0] data_debug_data;
+
+ output data_debug_out_r;
+ input data_debug_out_a;
+ output [`DATAWIDTH:0] data_debug_out;
+
+ assign data_debug_out_r = data_debug_data_r;
+ assign data_debug_data_a = data_debug_out_a;
+ assign data_debug_out = data_debug_data;
+
+endmodule
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
}
== ArchSim ==============================================================
+
== FPGA ==============================================================
+`include "macros.v"
+`define BRAM_ADDR_WIDTH 14
+`define BRAM_DATA_WIDTH `DATAWIDTH
+`define BRAM_NAME dscratch_bram
+`include "bram.inc"
+
+module dscratch (clk,
+ read_addr_r, read_addr_a_, read_addr_d,
+ read_data_r_, read_data_a, read_data_d_,
+ write_addr_r, write_addr_a_, write_addr_d,
+ write_data_r, write_data_a_, write_data_d,
+ write_done_r_, write_done_a, write_done_d_
+ );
+
+ input clk;
+ `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d)
+ `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_)
+ `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d)
+
+ `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
+ `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
+ `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
+ `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
+
+ reg bram_we;
+ wire bram_we_;
+ assign bram_we_ = bram_we;
+ wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
+ reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
+ wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
+ reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
+ wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
+ assign bram_write_data_ = bram_write_data;
+ `BRAM_NAME mybram(clk,
+ bram_we_, bram_write_address,
+ bram_read_address, bram_write_data_,
+ not_connected, bram_read_data);
+
+ reg send_done;
+
+ reg have_read; initial have_read = 0;
+ reg read_pending; initial read_pending = 0;
+ assign bram_read_address = read_addr_d;
+
+ always @(posedge clk) begin
+ bram_we = 0;
+ if (send_done) begin
+ `onwrite(write_done_r, write_done_a)
+ send_done = 0;
+ end
+ end else begin
+ if (!write_addr_r && write_addr_a) write_addr_a = 0;
+ if (!write_data_r && write_data_a) write_data_a = 0;
+ if (write_addr_r && write_data_r) begin
+ write_addr_a = 1;
+ write_data_a = 1;
+ bram_we = 1;
+ send_done = 1;
+ bram_write_address = write_addr_d;
+ bram_write_data = write_data_d;
+ end
+ end
+
+ if (read_pending) begin
+ read_pending <= 0;
+ have_read <= 1;
+ read_data_d <= bram_read_data;
+ end else if (have_read) begin
+ `onwrite(read_data_r, read_data_a)
+ have_read <= 0;
+ end
+ end else begin
+ `onread(read_addr_r, read_addr_a)
+ // ======= Careful with the timing here! =====================
+ // We MUST capture bram_read_data on the very next clock since
+ // read_addr_d is free to change after the next clock
+ // ===========================================================
+ read_pending <= 1;
+ end
+ end
+
+ end
+
+endmodule
+
+
== Constants ========================================================
== TeX ==============================================================
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+
+module execute (clk, command_r, command_a_, command_d,
+ ihorn_r_, ihorn_a, ihorn_d_,
+ dhorn_r_, dhorn_a, dhorn_d_
+ );
+ input clk;
+
+ `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+ `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
+
+ reg ihorn_full;
+ reg dhorn_full;
+
+ always @(posedge clk) begin
+ if (ihorn_full) begin
+ `onwrite(ihorn_r, ihorn_a)
+ ihorn_full = 0;
+ end
+ end else if (dhorn_full) begin
+ `onwrite(dhorn_r, dhorn_a)
+ dhorn_full = 0;
+ end
+ end else begin
+ `onread(command_r, command_a)
+ case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+ 0: begin
+ ihorn_full = 1;
+ ihorn_d = command_d;
+ end
+ //01:
+ 2: begin
+ dhorn_full = 1;
+ `packet_data(dhorn_d) = command_d[23:0];
+ `packet_dest(dhorn_d) = command_d[34:24];
+ end
+ //11:
+ endcase
+ end
+ end
+ end
+
+
+endmodule
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+
+// fifo *ship*: a 16-deep word-wide fifo
+module fifo (clk,
+ in_r, in_a, in_d,
+ out_r, out_a, out_d);
+
+ input clk;
+ input in_r;
+ input out_a;
+ output in_a;
+ output out_r;
+ input [(`DATAWIDTH-1):0] in_d;
+ output [(`DATAWIDTH-1):0] out_d;
+
+ wire [(`DATAWIDTH-1):0] d12;
+ wire [(`DATAWIDTH-1):0] d23;
+ wire [(`DATAWIDTH-1):0] d34;
+
+ fifo4 s1(clk, in_r, in_a, in_d, r12, a12, d12);
+ fifo4 s2(clk, r12, a12, d12, r23, a23, d23);
+ fifo4 s3(clk, r23, a23, d23, r34, a34, d34);
+ fifo4 s4(clk, r34, a34, d34, out_r, out_a, out_d);
+
+endmodule
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== ArchSim ==============================================================
== FPGA ==============================================================
+// not implemented FIXME
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== TeX ==============================================================
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+`define BRAM_ADDR_WIDTH 14
+`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
+`define BRAM_NAME iscratch_bram
+`include "bram.inc"
+
+module iscratch (clk,
+ write_addr_r, write_addr_a_, write_addr_d,
+ write_data_r, write_data_a_, write_data_d,
+ write_done_r_, write_done_a, write_done_d_,
+ cbd_r, cbd_a_, cbd_d,
+ preload_r, preload_a_, preload_d,
+ ihorn_r_, ihorn_a, ihorn_d_,
+ dhorn_r_, dhorn_a, dhorn_d_
+ );
+
+ input clk;
+ `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
+ `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
+ `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
+ `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
+
+ `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
+ `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+ `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
+
+ reg ihorn_full;
+ initial ihorn_full = 0;
+ reg dhorn_full;
+ initial dhorn_full = 0;
+ reg command_valid;
+ initial command_valid = 0;
+
+ reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
+ reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
+ initial preload_size = 0;
+
+ reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
+ reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
+ reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
+ reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
+ reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
+ reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
+ reg [(`INSTRUCTION_WIDTH-1):0] command;
+ reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
+ reg send_done;
+
+ reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
+ reg [(`DATAWIDTH-1):0] data;
+
+ reg write_flag;
+ reg [(`BRAM_ADDR_WIDTH-1):0] write_addr;
+ reg [(`BRAM_DATA_WIDTH-1):0] write_data;
+
+ wire [(`BRAM_DATA_WIDTH-1):0] ramread;
+
+ reg command_valid_read;
+ initial command_valid_read = 0;
+
+ reg launched;
+ initial launched = 0;
+
+ iscratch_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
+
+ always @(posedge clk) begin
+
+ write_flag <= 0;
+
+ if (!write_addr_r && write_addr_a) write_addr_a = 0;
+ if (!write_data_r && write_data_a) write_data_a = 0;
+
+ if (command_valid_read) begin
+ command_valid_read <= 0;
+ command_valid <= 1;
+
+ end else if (send_done) begin
+ `onwrite(write_done_r, write_done_a)
+ send_done <= 0;
+ end
+
+ end else if (write_addr_r && write_data_r) begin
+ write_addr_a = 1;
+ write_data_a = 1;
+ send_done <= 1;
+ write_flag <= 1;
+ write_addr <= write_addr_d;
+ write_data <= write_data_d;
+
+ end else if (ihorn_full && launched) begin
+ `onwrite(ihorn_r, ihorn_a)
+ ihorn_full <= 0;
+ end
+
+ end else if (dhorn_full) begin
+ `onwrite(dhorn_r, dhorn_a)
+ dhorn_full <= 0;
+ end
+
+ end else if (command_valid) begin
+ command_valid <= 0;
+ command = ramread;
+ case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+ 0: begin
+ ihorn_full <= 1;
+ ihorn_d <= command;
+ end
+ 1: begin
+ dhorn_full <= 1;
+ temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
+ temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
+ data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
+ data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
+ `packet_data(dhorn_d) <= temp;
+ `packet_dest(dhorn_d) <=
+ command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
+ end
+ 2: begin
+ dhorn_full <= 1;
+ `packet_data(dhorn_d) <= command[23:0];
+ `packet_dest(dhorn_d) <= command[34:24];
+ end
+ 3: begin
+ dhorn_full <= 1;
+ `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
+ `packet_dest(dhorn_d) <= command[34:24];
+ end
+ endcase
+
+ end else if (cbd_pos < cbd_size) begin
+ current_instruction_read_from <= cbd_base+cbd_pos;
+ command_valid_read <= 1;
+ cbd_pos <= cbd_pos + 1;
+
+ end else begin
+ `onread(cbd_r, cbd_a)
+ cbd_pos <= 0;
+ cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
+ cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
+
+ end else begin
+ `onread(preload_r, preload_a)
+ if (preload_size == 0) begin
+ preload_size <= preload_d;
+ end else if (!launched) begin
+ write_flag <= 1;
+ write_data <= preload_d;
+ write_addr <= preload_pos;
+ if (preload_pos == 0) begin
+ temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
+ temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
+ end
+ if ((preload_pos+1) == preload_size) begin
+ cbd_pos <= 0;
+ cbd_base <= temp_base;
+ cbd_size <= temp_size;
+ launched <= 1;
+ end
+ preload_pos <= preload_pos + 1;
+ end
+ end
+ end
+ end
+ end
+endmodule
+
+
+
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== ArchSim ==============================================================
== FPGA ==============================================================
+// not implemented FIXME
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== ArchSim ==============================================================
== FPGA ==============================================================
+// not implemented FIXME!
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
package edu.berkeley.fleet.slipway;
import edu.berkeley.fleet.interpreter.*;
+import edu.berkeley.fleet.doc.*;
import edu.berkeley.fleet.api.*;
import edu.berkeley.fleet.ies44.*;
import edu.berkeley.fleet.*;
return ship.getType() + ship.getOrdinal();
}
+ public void expand(ShipDescription sd) {
+ try {
+ String filename = sd.name.toLowerCase();
+ File outf = new File("src/edu/berkeley/fleet/slipway/"+filename+".v");
+ new File(outf.getParent()).mkdirs();
+ System.err.println("writing to " + outf);
+ FileOutputStream out = new FileOutputStream(outf);
+ PrintWriter pw = new PrintWriter(out);
+
+ pw.println(sd.sections.get("fpga"));
+ pw.flush();
+ pw.close();
+ } catch (Exception e) { throw new RuntimeException(e); }
+ }
+
}
\ No newline at end of file
+++ /dev/null
-`include "macros.v"
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `DATAWIDTH
-`define BRAM_NAME dcache_bram
-`include "bram.inc"
-
-module dcache (clk,
- read_addr_r, read_addr_a_, read_addr_d,
- read_data_r_, read_data_a, read_data_d_,
- write_addr_r, write_addr_a_, write_addr_d,
- write_data_r, write_data_a_, write_data_d,
- write_done_r_, write_done_a, write_done_d_
- );
-
- input clk;
- `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d)
- `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_)
- `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d)
-
- `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
- `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
- `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
- `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
-
- reg bram_we;
- wire bram_we_;
- assign bram_we_ = bram_we;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
- reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
- wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
- reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
- assign bram_write_data_ = bram_write_data;
- `BRAM_NAME mybram(clk,
- bram_we_, bram_write_address,
- bram_read_address, bram_write_data_,
- not_connected, bram_read_data);
-
- reg send_done;
-
- reg have_read; initial have_read = 0;
- reg read_pending; initial read_pending = 0;
- assign bram_read_address = read_addr_d;
-
- always @(posedge clk) begin
- bram_we = 0;
- if (send_done) begin
- `onwrite(write_done_r, write_done_a)
- send_done = 0;
- end
- end else begin
- if (!write_addr_r && write_addr_a) write_addr_a = 0;
- if (!write_data_r && write_data_a) write_data_a = 0;
- if (write_addr_r && write_data_r) begin
- write_addr_a = 1;
- write_data_a = 1;
- bram_we = 1;
- send_done = 1;
- bram_write_address = write_addr_d;
- bram_write_data = write_data_d;
- end
- end
-
- if (read_pending) begin
- read_pending <= 0;
- have_read <= 1;
- read_data_d <= bram_read_data;
- end else if (have_read) begin
- `onwrite(read_data_r, read_data_a)
- have_read <= 0;
- end
- end else begin
- `onread(read_addr_r, read_addr_a)
- // ======= Careful with the timing here! =====================
- // We MUST capture bram_read_data on the very next clock since
- // read_addr_d is free to change after the next clock
- // ===========================================================
- read_pending <= 1;
- end
- end
-
- end
-
-endmodule
assign data_debug_out = data_debug_data;
endmodule
+
+
+++ /dev/null
- `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d)
- `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
- `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
- `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
- `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
-
- reg ihorn_full;
- reg dhorn_full;
-
- always @(posedge clk) begin
- if (ihorn_full) begin
- `onwrite(ihorn_r, ihorn_a)
- ihorn_full = 0;
- end
- end else if (dhorn_full) begin
- `onwrite(dhorn_r, dhorn_a)
- dhorn_full = 0;
- end
- end else begin
- `onread(command_r, command_a)
- case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
- 0: begin
- ihorn_full = 1;
- ihorn_d = command_d;
- end
- //01:
- 2: begin
- dhorn_full = 1;
- `packet_data(dhorn_d) = command_d[23:0];
- `packet_dest(dhorn_d) = command_d[34:24];
- end
- //11:
- endcase
- end
- end
- end
);
input clk;
- `include "execute.inc"
+ `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+ `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
+
+ reg ihorn_full;
+ reg dhorn_full;
+
+ always @(posedge clk) begin
+ if (ihorn_full) begin
+ `onwrite(ihorn_r, ihorn_a)
+ ihorn_full = 0;
+ end
+ end else if (dhorn_full) begin
+ `onwrite(dhorn_r, dhorn_a)
+ dhorn_full = 0;
+ end
+ end else begin
+ `onread(command_r, command_a)
+ case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+ 0: begin
+ ihorn_full = 1;
+ ihorn_d = command_d;
+ end
+ //01:
+ 2: begin
+ dhorn_full = 1;
+ `packet_data(dhorn_d) = command_d[23:0];
+ `packet_dest(dhorn_d) = command_d[34:24];
+ end
+ //11:
+ endcase
+ end
+ end
+ end
+
endmodule
+
+
fifo4 s4(clk, r34, a34, d34, out_r, out_a, out_d);
endmodule
+
+
+++ /dev/null
-`include "macros.v"
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
-`define BRAM_NAME icache_bram
-`include "bram.inc"
-
-module icache (clk,
- write_addr_r, write_addr_a_, write_addr_d,
- write_data_r, write_data_a_, write_data_d,
- write_done_r_, write_done_a, write_done_d_,
- cbd_r, cbd_a_, cbd_d,
- preload_r, preload_a_, preload_d,
- ihorn_r_, ihorn_a, ihorn_d_,
- dhorn_r_, dhorn_a, dhorn_d_
- );
-
- input clk;
- `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
- `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
- `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
- `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
-
- `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
- `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
- `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
- `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
- `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
- `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
-
- reg ihorn_full;
- initial ihorn_full = 0;
- reg dhorn_full;
- initial dhorn_full = 0;
- reg command_valid;
- initial command_valid = 0;
-
- reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
- reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
- initial preload_size = 0;
-
- reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
- reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
- reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
- reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
- reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
- reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
- reg [(`INSTRUCTION_WIDTH-1):0] command;
- reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
- reg send_done;
-
- reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
- reg [(`DATAWIDTH-1):0] data;
-
- reg write_flag;
- reg [(`BRAM_ADDR_WIDTH-1):0] write_addr;
- reg [(`BRAM_DATA_WIDTH-1):0] write_data;
-
- wire [(`BRAM_DATA_WIDTH-1):0] ramread;
-
- reg command_valid_read;
- initial command_valid_read = 0;
-
- reg launched;
- initial launched = 0;
-
- icache_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
-
- always @(posedge clk) begin
-
- write_flag <= 0;
-
- if (!write_addr_r && write_addr_a) write_addr_a = 0;
- if (!write_data_r && write_data_a) write_data_a = 0;
-
- if (command_valid_read) begin
- command_valid_read <= 0;
- command_valid <= 1;
-
- end else if (send_done) begin
- `onwrite(write_done_r, write_done_a)
- send_done <= 0;
- end
-
- end else if (write_addr_r && write_data_r) begin
- write_addr_a = 1;
- write_data_a = 1;
- send_done <= 1;
- write_flag <= 1;
- write_addr <= write_addr_d;
- write_data <= write_data_d;
-
- end else if (ihorn_full && launched) begin
- `onwrite(ihorn_r, ihorn_a)
- ihorn_full <= 0;
- end
-
- end else if (dhorn_full) begin
- `onwrite(dhorn_r, dhorn_a)
- dhorn_full <= 0;
- end
-
- end else if (command_valid) begin
- command_valid <= 0;
- command = ramread;
- case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
- 0: begin
- ihorn_full <= 1;
- ihorn_d <= command;
- end
- 1: begin
- dhorn_full <= 1;
- temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
- temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
- data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
- data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
- `packet_data(dhorn_d) <= temp;
- `packet_dest(dhorn_d) <=
- command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
- end
- 2: begin
- dhorn_full <= 1;
- `packet_data(dhorn_d) <= command[23:0];
- `packet_dest(dhorn_d) <= command[34:24];
- end
- 3: begin
- dhorn_full <= 1;
- `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
- `packet_dest(dhorn_d) <= command[34:24];
- end
- endcase
-
- end else if (cbd_pos < cbd_size) begin
- current_instruction_read_from <= cbd_base+cbd_pos;
- command_valid_read <= 1;
- cbd_pos <= cbd_pos + 1;
-
- end else begin
- `onread(cbd_r, cbd_a)
- cbd_pos <= 0;
- cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
- cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
-
- end else begin
- `onread(preload_r, preload_a)
- if (preload_size == 0) begin
- preload_size <= preload_d;
- end else if (!launched) begin
- write_flag <= 1;
- write_data <= preload_d;
- write_addr <= preload_pos;
- if (preload_pos == 0) begin
- temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
- temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
- end
- if ((preload_pos+1) == preload_size) begin
- cbd_pos <= 0;
- cbd_base <= temp_base;
- cbd_size <= temp_size;
- launched <= 1;
- end
- preload_pos <= preload_pos + 1;
- end
- end
- end
- end
- end
-endmodule
-
-
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