ships/Iscratch.ship

   1 ship: Iscratch
   2
   3 == Ports ===========================================================
   4 data  in:    write_addr
   5 data  in:    write_data
   6 token out:   write_done
   7
   8 data  in:    cbd
   9
  10 == Fleeterpreter ====================================================
  11
  12     private long[] mem = new long[0];
  13     public long readMem(int addr) { return mem[addr]; }
  14     public void writeMem(int addr, long val) {
  15         if (addr >= mem.length) {
  16             long[] newmem = new long[addr * 2 + 1];
  17             System.arraycopy(mem, 0, newmem, 0, mem.length);
  18             mem = newmem;
  19         }
  20         mem[addr] = val;
  21     }
  22
  23     public void dispatch(int addr, int size) {
  24         for(int i=addr; i<addr+size; i++) {
  25             Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
  26             ((Interpreter)getFleet()).dispatch(instr, i);
  27         }
  28     }
  29
  30     public void service() {
  31         if (box_cbd.dataReadyForShip()) {
  32             int val = box_cbd.removeDataForShip();
  33             int addr = val >> 6;
  34             int size = val & 0x3f;
  35             dispatch(addr, size);
  36         }
  37
  38         if (box_write_addr.dataReadyForShip() &&
  39             box_write_data.dataReadyForShip() &&
  40             box_write_done.readyForItemFromShip()) {
  41             Interpreter f = (Interpreter)getFleet();
  42             f.writeMem(box_write_addr.removeDataForShip(),
  43                        box_write_data.removeDataForShip());
  44             box_write_done.addTokenFromShip();
  45         }
  46     }
  47
  48     public void boot(byte[] instructions) {
  49         Interpreter fleet = (Interpreter)getFleet();
  50         // load the iscratch and take note of the 0-address CBD
  51         long launch = 0;
  52         for(int i=0; i<instructions.length; i+=6) {
  53             long word = 0;
  54             for(int j=0; j<6; j++)
  55                 word = (word << 8) | (instructions[i+j] & 0xff);
  56             writeMem(i/6, word);
  57             if (i==0) launch = word;
  58         }
  59
  60         // dispatch the 0-address CBD
  61         int base = (int)(launch >> 6);
  62         base = base & ~(0xffffffff << 18);
  63         int size = (int)launch;
  64         size = size & ~(0xffffffff <<  6);
  65         dispatch(base, size);
  66     }
  67
  68 == Constants ========================================================
  69 == TeX ==============================================================
  70 == ArchSim ==============================================================
  71 == FPGA ==============================================================
  72 `include "macros.v"
  73 `define BRAM_ADDR_WIDTH 14
  74 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
  75 `define BRAM_NAME iscratch_bram
  76 `include "bram.inc"
  77
  78 module iscratch (clk,
  79                write_addr_r,   write_addr_a_,  write_addr_d,
  80                write_data_r,   write_data_a_,  write_data_d,
  81                write_done_r_,  write_done_a,   write_done_d_,
  82                cbd_r,          cbd_a_,         cbd_d,
  83                preload_r,      preload_a_,     preload_d,
  84                ihorn_r_,       ihorn_a,        ihorn_d_,
  85                dhorn_r_,       dhorn_a,        dhorn_d_
  86            );
  87
  88   input  clk;
  89   `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(`DATAWIDTH-1):0],         write_addr_d)
  90   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
  91   `output(write_done_r,  write_done_r_, write_done_a,   [(`DATAWIDTH-1):0],         write_done_d_)
  92   `defreg(write_done_d_,                                [(`DATAWIDTH-1):0],         write_done_d)
  93
  94   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
  95   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
  96   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
  97   `defreg(ihorn_d_,                                     [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
  98   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
  99   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
 100
 101   reg ihorn_full;
 102   initial ihorn_full = 0;
 103   reg dhorn_full;
 104   initial dhorn_full = 0;
 105   reg command_valid;
 106   initial command_valid = 0;
 107
 108   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
 109   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
 110   initial preload_size = 0;
 111
 112   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
 113   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
 114   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
 115   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
 116   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
 117   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
 118   reg [(`INSTRUCTION_WIDTH-1):0]  command;
 119   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 120   reg                             send_done;
 121
 122   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
 123   reg [(`DATAWIDTH-1):0]                                     data;
 124
 125   reg                             write_flag;
 126   reg [(`BRAM_ADDR_WIDTH-1):0]    write_addr;
 127   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
 128
 129   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
 130
 131   reg command_valid_read;
 132   initial command_valid_read = 0;
 133
 134   reg launched;
 135   initial launched = 0;
 136
 137   iscratch_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
 138
 139   always @(posedge clk) begin
 140
 141     write_flag <= 0;
 142
 143     if (!write_addr_r && write_addr_a) write_addr_a = 0;
 144     if (!write_data_r && write_data_a) write_data_a = 0;
 145
 146     if (command_valid_read) begin
 147       command_valid_read  <= 0;
 148       command_valid       <= 1;
 149
 150     end else  if (send_done) begin
 151       `onwrite(write_done_r, write_done_a)
 152         send_done <= 0;
 153       end
 154
 155     end else if (write_addr_r && write_data_r) begin
 156       write_addr_a       = 1;
 157       write_data_a       = 1;
 158       send_done         <= 1;
 159       write_flag        <= 1;
 160       write_addr        <= write_addr_d;
 161       write_data        <= write_data_d;
 162
 163     end else if (ihorn_full && launched) begin
 164       `onwrite(ihorn_r, ihorn_a)
 165         ihorn_full <= 0;
 166       end
 167
 168     end else if (dhorn_full) begin
 169       `onwrite(dhorn_r, dhorn_a)
 170         dhorn_full <= 0;
 171       end
 172
 173     end else if (command_valid) begin
 174       command_valid <= 0;
 175       command = ramread;
 176       case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
 177         0: begin
 178             ihorn_full  <= 1;
 179             ihorn_d     <= command;
 180            end
 181         1: begin
 182             dhorn_full  <= 1;
 183             temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
 184             temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
 185             data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
 186             data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
 187             `packet_data(dhorn_d) <= temp;
 188             `packet_dest(dhorn_d) <=
 189                   command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
 190            end
 191         2: begin
 192             dhorn_full            <= 1;
 193             `packet_data(dhorn_d) <= command[23:0];
 194             `packet_dest(dhorn_d) <= command[34:24];
 195            end
 196         3: begin
 197             dhorn_full            <= 1;
 198             `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
 199             `packet_dest(dhorn_d) <= command[34:24];
 200            end
 201       endcase
 202
 203     end else if (cbd_pos < cbd_size) begin
 204       current_instruction_read_from <= cbd_base+cbd_pos;
 205       command_valid_read            <= 1;
 206       cbd_pos                       <= cbd_pos + 1;
 207
 208     end else begin
 209       `onread(cbd_r, cbd_a)
 210         cbd_pos       <= 0;
 211         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 212         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 213
 214       end else begin
 215         `onread(preload_r, preload_a)
 216           if (preload_size == 0) begin
 217             preload_size     <= preload_d;
 218           end else if (!launched) begin
 219             write_flag <= 1;
 220             write_data <= preload_d;
 221             write_addr <= preload_pos;
 222             if (preload_pos == 0) begin
 223               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 224               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 225             end
 226             if ((preload_pos+1) == preload_size) begin
 227               cbd_pos  <= 0;
 228               cbd_base <= temp_base;
 229               cbd_size <= temp_size;
 230               launched <= 1;
 231             end
 232             preload_pos      <= preload_pos + 1;
 233           end
 234         end
 235       end
 236     end
 237   end
 238 endmodule
 239
 240
 241
 242
 243
 244 == Contributors =========================================================
 245 Adam Megacz <megacz@cs.berkeley.edu>