- assign clk0 = clk0_bufg;
- assign clk90 = clk90_bufg;
- assign clk200 = clk200_bufg;
- assign clkdiv0 = clkdiv0_bufg;
-
- generate
- if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
- //***************************************************************************
- // Differential input clock input buffers
- //***************************************************************************
-
- IBUFGDS_LVPECL_25 SYS_CLK_INST
- (
- .I (sys_clk_p),
- .IB (sys_clk_n),
- .O (sys_clk_ibufg)
- );
-
- IBUFGDS_LVPECL_25 IDLY_CLK_INST
- (
- .I (clk200_p),
- .IB (clk200_n),
- .O (clk200_ibufg)
- );
-
- end else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
- //**************************************************************************
- // Single ended input clock input buffers
- //**************************************************************************
-
- // AM -- edits: changed IBUFG to BUF
-
- BUF SYS_CLK_INST
- (
- .I (sys_clk),
- .O (sys_clk_ibufg)
- );
-
- BUF IDLY_CLK_INST
- (
- .I (idly_clk_200),
- .O (clk200_ibufg)
- );
-
- end
- endgenerate
-
- BUFG CLK_200_BUFG
- (
- .O (clk200_bufg),
- .I (clk200_ibufg)
- );
-
- //***************************************************************************
- // Global clock generation and distribution
- //***************************************************************************
-
- DCM_BASE #
- (
- .CLKIN_PERIOD (CLK_PERIOD_NS),
- .CLKDV_DIVIDE (2.0),
- .DLL_FREQUENCY_MODE (DLL_FREQ_MODE),
- .DUTY_CYCLE_CORRECTION ("TRUE"),
- .FACTORY_JF (16'hF0F0)
- )
- u_dcm_base
- (
- .CLK0 (dcm_clk0),
- .CLK180 (),
- .CLK270 (),
- .CLK2X (),
- .CLK2X180 (),
- .CLK90 (dcm_clk90),
- .CLKDV (dcm_clkdiv0),
- .CLKFX (),
- .CLKFX180 (),
- .LOCKED (dcm_lock),
- .CLKFB (clk0_bufg),
- .CLKIN (sys_clk_ibufg),
- .RST (sys_rst)
- );
-
- BUFG U_BUFG_CLK0
- (
- .O (clk0_bufg),
- .I (dcm_clk0)
- );
-
- BUFG U_BUFG_CLK90
- (
- .O (clk90_bufg),
- .I (dcm_clk90)
- );
-
- BUFG U_BUFG_CLKDIV0
- (
- .O (clkdiv0_bufg),
- .I (dcm_clkdiv0)
- );