data out: out
-percolate up: gpio_led_0 1
-percolate up: gpio_led_1 1
-percolate up: gpio_led_2 1
-percolate up: gpio_led_3 1
+percolate down: clk200_p 1
percolate inout: ddr2_dq 64
+percolate inout: ddr2_dqs 8
+percolate inout: ddr2_dqs_n 8
percolate up: ddr2_a 13
percolate up: ddr2_ba 2
percolate up: ddr2_ras_n 1
percolate up: ddr2_odt 1
percolate up: ddr2_cke 1
percolate up: ddr2_dm 8
-percolate up: phy_init_done 1
-percolate inout: ddr2_dqs 8
-percolate inout: ddr2_dqs_n 8
percolate up: ddr2_ck 2
percolate up: ddr2_ck_n 2
== FPGA ==============================================================
-/*
-percolate inout: ddr2_dq 8
-percolate up: ddr2_a 15
-percolate up: ddr2_ba 3
-percolate up: ddr2_ras_n 1
-percolate up: ddr2_cas_n 1
-percolate up: ddr2_we_n 1
-percolate up: ddr2_cs_n 1
-percolate up: ddr2_odt 1
-percolate up: ddr2_cke 1
-percolate up: ddr2_dm 1
-percolate up: phy_init_done 1
-percolate inout: ddr2_dqs 1
-percolate inout: ddr2_dqs_n 1
-percolate up: ddr2_ck 1
-percolate up: ddr2_ck_n 1
-*/
-
-//NET "sys_clk_p" LOC = "H17" ; #Bank 3
-//NET "sys_clk_n" LOC = "H18" ; #Bank 3
-//NET "clk200_p" LOC = "K17" ; #Bank 3
-//NET "clk200_n" LOC = "L18" ; #Bank 3
-//NET "sys_rst_n" LOC = "L24" ; #Bank 19
-
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2006 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-
-wire clk200_p;
-wire clk200_n;
-wire clk_rebuffered;
-
- ddr2_sdram # (
+// clocking //////////////////////////////////////////////////////////////////////////////
+
+wire clk0;
+wire clkdiv0;
+wire clk0_unbuffered;
+wire clkdiv0_unbuffered;
+wire dcm_lock;
+
+BUFG clk200_p_buf (.I(clk200_p), .O(clk200_p_buffered));
+BUFG clk0_fb_buf (.I(clk0_unbuffered), .O(clk0_fb));
+BUFG clk0_fb_buf2 (.I(clk0_unbuffered), .O(clk0));
+BUFG clkdiv0_bufg (.I(clkdiv0_unbuffered), .O(clkdiv0));
+
+DCM
+ #(
+ .CLKIN_PERIOD (10.0),
+ .DLL_FREQUENCY_MODE ("LOW"),
+ .DUTY_CYCLE_CORRECTION ("TRUE"),
+ .CLKDV_DIVIDE (2),
+ .FACTORY_JF (16'hF0F0)
+ ) ddr2_dcm (
+ .CLKIN (clk),
+ .CLKFB (clk0_fb),
+ .CLKDV (clkdiv0_unbuffered),
+ .CLK0 (clk0_unbuffered),
+ .CLK90 (clk90),
+ .LOCKED (dcm_lock),
+ .RST (rst)
+ );
+
+// controller instance ////////////////////////////////////////////////////////////////////////
+
+wire phy_init_done;
+wire app_wdf_afull;
+wire app_af_afull;
+reg app_wdf_wren;
+reg [63:0] app_wdf_data;
+reg app_af_wren;
+reg [2:0] app_af_cmd;
+reg [30:0] app_af_addr;
+wire rd_data_valid;
+wire [63:0] rd_data_fifo_out;
+
+reg read_waiting;
+reg [7:0] mask;
+reg [6:0] burst_count;
+
+ddr2_sdram # (
.BANK_WIDTH(2), // # of memory bank addr bits.
.CKE_WIDTH(1), // # of memory clock enable outputs.
.CLK_WIDTH(2), // # of clock outputs.
.ADDITIVE_LAT(0), // additive write latency.
.BURST_LEN(4), // burst length (in double words).
.BURST_TYPE(0), // burst type (=0 seq; =1 interleaved).
- .CAS_LAT(4), // CAS latency.
+ .CAS_LAT(3), // CAS latency.
.ECC_ENABLE(0), // enable ECC (=1 enable).
.APPDATA_WIDTH(128), // # of usr read/write data bus bits.
.MULTI_BANK_EN(1), // Keeps multiple banks open. (= 1 enable).
.TREFI_NS(7800), // auto refresh interval (ns).
.TRAS(40000), // active->precharge delay.
.TRCD(15000), // active->read/write delay.
- .TRFC(127500), // refresh->refresh, refresh->active delay.
+ .TRFC(105000), // refresh->refresh, refresh->active delay.
.TRP(15000), // precharge->command delay.
.TRTP(7500), // read->precharge delay.
.TWR(15000), // used to determine write->precharge.
// make sure to uncomment the coregen commands
// in ise_flow.bat or create_ise.bat files in
// par folder.
- .CLK_PERIOD(5000), // Core/Memory clock period (in ps).
+ .CLK_PERIOD(10000), // Core/Memory clock period (in ps).
.DQS_IO_COL(16'b0000000000000000), // I/O column location of DQS groups
// (=0, left; =1 center, =2 right).
- //.DQ_IO_MS(64'b10100101_10100101_10100101_10100101_10100101_10100101_10100101_10100101),
.DQ_IO_MS(64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100),
// Master/Slave location of DQ I/O (=0 slave).
- .CLK_TYPE("SINGLE_ENDED"), // # = "DIFFERENTIAL " ->; Differential input clocks ,
- // # = "SINGLE_ENDED" -> Single ended input clocks.
- .DLL_FREQ_MODE("HIGH"), // DCM Frequency range.
.RST_ACT_LOW(1) // =1 for active low reset, =0 for active high.
-)
-ddr2_sdram (
- .sys_clk (clk),
- .idly_clk_200 (clk200_p),
+) ddr2_sdram (
.sys_rst_n (!rst),
.ddr2_dq (ddr2_dq),
.ddr2_ck (ddr2_ck),
.ddr2_ck_n (ddr2_ck_n),
- .phy_init_done (gpio_led_0),
+ .phy_init_done (phy_init_done),
- .app_wdf_afull (gpio_led_1),
- .app_af_afull (gpio_led_2),
- .rd_data_valid (gpio_led_3),
+ .app_wdf_afull (app_wdf_afull),
+ .app_af_afull (app_af_afull),
+ .rd_data_valid (rd_data_valid),
+ .rd_data_fifo_out (rd_data_fifo_out),
- .app_wdf_wren (1'b1),
- .app_af_wren (app_af_wren),
- .app_af_addr (app_af_addr),
+ .app_wdf_wren ((~phy_init_done) ? 0 : app_wdf_wren),
+ .app_wdf_data ((~phy_init_done) ? 0 : app_wdf_data),
+ .app_wdf_mask_data ((~phy_init_done) ? 0 : mask),
+
+ .app_af_wren ((~phy_init_done) ? 0 : app_af_wren),
.app_af_cmd (app_af_cmd),
+ .app_af_addr (app_af_addr),
- .rd_data_fifo_out (rd_data_fifo_out),
- .app_wdf_data (app_wdf_data),
- .app_wdf_mask_data (app_wdf_mask_data)
-);
-
- wire clk200_p_fb;
- DCM // 200Mhz DDR clock
- #(
- .CLKFX_MULTIPLY(2),
- .CLKFX_DIVIDE(1),
- .CLKIN_PERIOD("10 ns")
- ) vgadcm (
- .CLKIN (clk),
- .CLKFB (clk200_p_fb),
- .CLKFX (clk200_n),
- .CLKFX180 (clk200_p),
- .CLK0 (clk200_p_fb)
- );
-
-/*
- always @(posedge clk) begin
-
- if (rst) begin
- `reset
- CommandValid <= 0;
- DataOutReady <= 0;
- end else begin
- `cleanup
-
- CommandValid <= 0;
- DataInValid <= 0;
-
- if (`out_empty) begin
- DataOutReady <= 1;
- end
+ .dcm_lock (dcm_lock),
+ .clk0 (clk0),
+ .clk90 (clk90),
+ .clkdiv0 (clkdiv0),
+
+ .clk200 (clk200_p_buffered)
+ );
+
+// custom code //////////////////////////////////////////////////////////////////////////////
+
+reg [37:0] out_d;
+assign out_d_ = out_d;
+
+// grossly inefficient -- always uses only the first word of a burst!
+always @(posedge clk) begin
+ if (rst) begin
+ `reset
+ app_wdf_wren <= 0;
+ app_af_wren <= 0;
+ read_waiting <= 0;
+ burst_count <= 0;
+
+ end else begin
+ `cleanup
+
+ mask <= 8'b11111111;
+ if (burst_count == 0 || burst_count == 1) begin
+ app_wdf_wren <= 0;
+ app_af_wren <= 0;
+ end else if ((burst_count > 1) && (app_af_cmd == 3'b000)) begin
+ app_af_wren <= ~burst_count[0];
+ end
- if (DataOutReady && DataOutValid && `out_empty) begin
- out_d <= { 1'b0, DataOut[`WORDWIDTH-1:0] };
- `fill_out
- DataOutReady <= 0;
-
- end else if (DataOutReady && CommandReady && DataInReady && `out_empty) begin
- if (`inAddrWrite_full && `inDataWrite_full) begin
- `drain_inDataWrite
- `drain_inAddrWrite
- CommandAddress <= inAddrWrite_d;
- Command <= 3'b000;
- CommandValid <= 1;
- DataInValid <= 1;
- out_d <= { 1'b1, 37'b0 };
- `fill_out
- DataOutReady <= 0;
- end else if (`inAddrRead_full) begin
- `drain_inAddrRead
- CommandAddress <= inAddrRead_d;
- CommandValid <= 1;
- Command <= 3'b001;
- DataInValid <= 0;
- DataOutReady <= 1;
- end
+ if (burst_count > 0) begin
+ burst_count <= burst_count - 1;
+ end else if ((~read_waiting) && rd_data_valid) begin
+ /* wait */
+ end else if (read_waiting) begin
+ if (rd_data_valid) begin
+ read_waiting <= 0;
+ out_d <= { 1'b0, rd_data_fifo_out[36:0] };
+ `fill_out
end
+ end else if (app_wdf_afull || app_af_afull) begin
+ /* wait */
+ end else if (`inAddrWrite_full && `inDataWrite_full) begin
+ `drain_inDataWrite
+ `drain_inAddrWrite
+ app_wdf_data <= inDataWrite_d;
+ app_af_addr <= { inAddrWrite_d, 2'b00 };
+ app_af_cmd <= 3'b000;
+ app_af_wren <= 1;
+ app_wdf_wren <= 1;
+ burst_count <= 7;
+ out_d <= { phy_init_done /*1'b1*/, 37'b0 };
+ mask <= 8'b00000000;
+ `fill_out
+ end else if (`inAddrRead_full) begin
+ `drain_inAddrRead
+ app_af_addr <= { inAddrRead_d, 2'b00 };
+ app_af_cmd <= 3'b001;
+ app_af_wren <= 1;
+ burst_count <= 3;
+ read_waiting <= 1;
end
end
-*/
+end
+
+== UCF ==============================================================
+
+Net clk200_p PERIOD = 5 ns HIGH 50%; # 200Mhz
+
+#NET "*/u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET = "SYS_CLK";
+Net "ddr2_0/clk0" TNM_NET = "SYS_CLK";
+TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
+
+#NET "*/u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
+Net clk200_p TNM_NET = "SYS_CLK_200";
+TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
+
+# suggested by
+# http://www.xilinx.com/support/answers/31606.htm
+# NET "clk_0" TNM_NET = "SYS_clk_0";
+# TIMESPEC "TS_SYS_clk_0" = PERIOD "SYS_clk_0" 5 ns HIGH 50 %;
+# NET "clk_90" TNM_NET = "SYS_clk_90";
+# TIMESPEC "TS_SYS_clk_90" = PERIOD "SYS_clk_90" "TS_SYS_clk_0" PHASE 1.25 ns HIGH 50 %;
+
+################################################################################
+# I/O STANDARDS
+################################################################################
+
+NET "ddr2_dq[*]" IOSTANDARD = SSTL18_II_DCI;
+NET "ddr2_a[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_ba[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_ras_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_cas_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_we_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_cs_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_odt" IOSTANDARD = SSTL18_II;
+NET "ddr2_cke" IOSTANDARD = SSTL18_II;
+NET "ddr2_dm[*]" IOSTANDARD = SSTL18_II;
+#NET "sys_clk_p" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "sys_clk_n" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "clk200_p" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "clk200_n" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "sys_rst_n" IOSTANDARD = LVCMOS18;
+#NET "phy_init_done" IOSTANDARD = LVCMOS18;
+#NET "error" IOSTANDARD = LVCMOS18;
+NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
+NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
+NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_II;
+NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_II;
+
+################################################################################
+# Location Constraints
+################################################################################
+
+NET "ddr2_dq[0]" LOC = "AF30" ; #Bank 17
+NET "ddr2_dq[1]" LOC = "AK31" ; #Bank 17
+NET "ddr2_dq[2]" LOC = "AF31" ; #Bank 17
+NET "ddr2_dq[3]" LOC = "AD30" ; #Bank 17
+NET "ddr2_dq[4]" LOC = "AJ30" ; #Bank 17
+NET "ddr2_dq[5]" LOC = "AF29" ; #Bank 17
+NET "ddr2_dq[6]" LOC = "AD29" ; #Bank 17
+NET "ddr2_dq[7]" LOC = "AE29" ; #Bank 17
+NET "ddr2_dq[8]" LOC = "AH27" ; #Bank 21
+NET "ddr2_dq[9]" LOC = "AF28" ; #Bank 21
+NET "ddr2_dq[10]" LOC = "AH28" ; #Bank 21
+NET "ddr2_dq[11]" LOC = "AA28" ; #Bank 21
+NET "ddr2_dq[12]" LOC = "AG25" ; #Bank 21
+NET "ddr2_dq[13]" LOC = "AJ26" ; #Bank 21
+NET "ddr2_dq[14]" LOC = "AG28" ; #Bank 21
+NET "ddr2_dq[15]" LOC = "AB28" ; #Bank 21
+NET "ddr2_dq[16]" LOC = "AC28" ; #Bank 21
+NET "ddr2_dq[17]" LOC = "AB25" ; #Bank 21
+NET "ddr2_dq[18]" LOC = "AC27" ; #Bank 21
+NET "ddr2_dq[19]" LOC = "AA26" ; #Bank 21
+NET "ddr2_dq[20]" LOC = "AB26" ; #Bank 21
+NET "ddr2_dq[21]" LOC = "AA24" ; #Bank 21
+NET "ddr2_dq[22]" LOC = "AB27" ; #Bank 21
+NET "ddr2_dq[23]" LOC = "AA25" ; #Bank 21
+NET "ddr2_dq[24]" LOC = "AC29" ; #Bank 17
+NET "ddr2_dq[25]" LOC = "AB30" ; #Bank 17
+NET "ddr2_dq[26]" LOC = "W31" ; #Bank 17
+NET "ddr2_dq[27]" LOC = "V30" ; #Bank 17
+NET "ddr2_dq[28]" LOC = "AC30" ; #Bank 17
+NET "ddr2_dq[29]" LOC = "W29" ; #Bank 17
+NET "ddr2_dq[30]" LOC = "V27" ; #Bank 17
+NET "ddr2_dq[31]" LOC = "W27" ; #Bank 17
+NET "ddr2_dq[32]" LOC = "V29" ; #Bank 17
+NET "ddr2_dq[33]" LOC = "Y27" ; #Bank 17
+NET "ddr2_dq[34]" LOC = "Y26" ; #Bank 17
+NET "ddr2_dq[35]" LOC = "W24" ; #Bank 17
+NET "ddr2_dq[36]" LOC = "V28" ; #Bank 17
+NET "ddr2_dq[37]" LOC = "W25" ; #Bank 17
+NET "ddr2_dq[38]" LOC = "W26" ; #Bank 17
+NET "ddr2_dq[39]" LOC = "V24" ; #Bank 17
+NET "ddr2_dq[40]" LOC = "R24" ; #Bank 19
+NET "ddr2_dq[41]" LOC = "P25" ; #Bank 19
+NET "ddr2_dq[42]" LOC = "N24" ; #Bank 19
+NET "ddr2_dq[43]" LOC = "P26" ; #Bank 19
+NET "ddr2_dq[44]" LOC = "T24" ; #Bank 19
+NET "ddr2_dq[45]" LOC = "N25" ; #Bank 19
+NET "ddr2_dq[46]" LOC = "P27" ; #Bank 19
+NET "ddr2_dq[47]" LOC = "N28" ; #Bank 19
+NET "ddr2_dq[48]" LOC = "M28" ; #Bank 19
+NET "ddr2_dq[49]" LOC = "L28" ; #Bank 19
+NET "ddr2_dq[50]" LOC = "F25" ; #Bank 19
+NET "ddr2_dq[51]" LOC = "H25" ; #Bank 19
+NET "ddr2_dq[52]" LOC = "K27" ; #Bank 19
+NET "ddr2_dq[53]" LOC = "K28" ; #Bank 19
+NET "ddr2_dq[54]" LOC = "H24" ; #Bank 19
+NET "ddr2_dq[55]" LOC = "G26" ; #Bank 19
+NET "ddr2_dq[56]" LOC = "G25" ; #Bank 19
+NET "ddr2_dq[57]" LOC = "M26" ; #Bank 19
+NET "ddr2_dq[58]" LOC = "J24" ; #Bank 19
+NET "ddr2_dq[59]" LOC = "L26" ; #Bank 19
+NET "ddr2_dq[60]" LOC = "J27" ; #Bank 19
+NET "ddr2_dq[61]" LOC = "M25" ; #Bank 19
+NET "ddr2_dq[62]" LOC = "L25" ; #Bank 19
+NET "ddr2_dq[63]" LOC = "L24" ; #Bank 19
+NET "ddr2_a[12]" LOC = "T31" ; #Bank 15
+NET "ddr2_a[11]" LOC = "R29" ; #Bank 15
+NET "ddr2_a[10]" LOC = "J31" ; #Bank 15
+NET "ddr2_a[9]" LOC = "R28" ; #Bank 15
+NET "ddr2_a[8]" LOC = "M31" ; #Bank 15
+NET "ddr2_a[7]" LOC = "P30" ; #Bank 15
+NET "ddr2_a[6]" LOC = "P31" ; #Bank 15
+NET "ddr2_a[5]" LOC = "L31" ; #Bank 15
+NET "ddr2_a[4]" LOC = "K31" ; #Bank 15
+NET "ddr2_a[3]" LOC = "P29" ; #Bank 15
+NET "ddr2_a[2]" LOC = "N29" ; #Bank 15
+NET "ddr2_a[1]" LOC = "M30" ; #Bank 15
+NET "ddr2_a[0]" LOC = "L30" ; #Bank 15
+NET "ddr2_ba[1]" LOC = "J30" ; #Bank 15
+NET "ddr2_ba[0]" LOC = "G31" ; #Bank 15
+NET "ddr2_ras_n" LOC = "H30" ; #Bank 15
+NET "ddr2_cas_n" LOC = "E31" ; #Bank 15
+NET "ddr2_we_n" LOC = "K29" ; #Bank 15
+NET "ddr2_cs_n" LOC = "L29" ; #Bank 15
+NET "ddr2_odt" LOC = "F31" ; #Bank 15
+NET "ddr2_cke" LOC = "T28" ; #Bank 15
+NET "ddr2_cke[1]" LOC = "U30" ;
+NET "ddr2_dm[0]" LOC = "AJ31" ; #Bank 17
+NET "ddr2_dm[1]" LOC = "AE28" ; #Bank 21
+NET "ddr2_dm[2]" LOC = "Y24" ; #Bank 21
+NET "ddr2_dm[3]" LOC = "Y31" ; #Bank 17
+NET "ddr2_dm[4]" LOC = "V25" ; #Bank 17
+NET "ddr2_dm[5]" LOC = "P24" ; #Bank 19
+NET "ddr2_dm[6]" LOC = "F26" ; #Bank 19
+NET "ddr2_dm[7]" LOC = "J25" ; #Bank 19
+NET "sys_clk_p" LOC = "H14" ; #Bank 3
+NET "sys_clk_n" LOC = "H15" ; #Bank 3
+NET "clk200_p" LOC = "L19" ; #Bank 3
+NET "clk200_n" LOC = "K19" ; #Bank 3
+NET "sys_rst_n" LOC = "E9"; #Bank 20
+#NET "phy_init_done" LOC = "H18" ; #Bank 3
+NET "error" LOC = "F6"; #Bank 12
+NET "ddr2_dqs[0]" LOC = "AA29" ; #Bank 17
+NET "ddr2_dqs_n[0]" LOC = "AA30" ; #Bank 17
+NET "ddr2_dqs[1]" LOC = "AK28" ; #Bank 21
+NET "ddr2_dqs_n[1]" LOC = "AK27" ; #Bank 21
+NET "ddr2_dqs[2]" LOC = "AK26" ; #Bank 21
+NET "ddr2_dqs_n[2]" LOC = "AJ27" ; #Bank 21
+NET "ddr2_dqs[3]" LOC = "AB31" ; #Bank 17
+NET "ddr2_dqs_n[3]" LOC = "AA31" ; #Bank 17
+NET "ddr2_dqs[4]" LOC = "Y28" ; #Bank 17
+NET "ddr2_dqs_n[4]" LOC = "Y29" ; #Bank 17
+NET "ddr2_dqs[5]" LOC = "E26" ; #Bank 19
+NET "ddr2_dqs_n[5]" LOC = "E27" ; #Bank 19
+NET "ddr2_dqs[6]" LOC = "H28" ; #Bank 19
+NET "ddr2_dqs_n[6]" LOC = "G28" ; #Bank 19
+NET "ddr2_dqs[7]" LOC = "G27" ; #Bank 19
+NET "ddr2_dqs_n[7]" LOC = "H27" ; #Bank 19
+NET "ddr2_ck[0]" LOC = "AK29" ; #Bank 21
+NET "ddr2_ck_n[0]" LOC = "AJ29" ; #Bank 21
+NET "ddr2_ck[1]" LOC = "E28" ; #Bank 19
+NET "ddr2_ck_n[1]" LOC = "F28" ; #Bank 19
+
+################################################################################
+#IDELAYCTRL Location Constraints
+################################################################################
+
+INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;
+INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y2;
+INST "*/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;
+
+###############################################################################
+# Define multicycle paths - these paths may take longer because additional
+# time allowed for logic to settle in calibration/initialization FSM
+###############################################################################
+
+# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
+# multicycle paths from originating flip-flop to ANY destination
+# flip-flop (or in some cases, it can also be a BRAM)
+# MUX Select for either rising/falling CLK0 for 2nd stage read capture
+INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
+TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
+"TS_SYS_CLK" * 4;
+# MUX select for read data - optional delay on data to account for byte skews
+#INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
+#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
+#"TS_SYS_CLK" * 4;
+# Calibration/Initialization complete status flag (for PHY logic only) - can
+# be used to drive both flip-flops and BRAMs
+INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
+TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
+"TS_SYS_CLK" * 4;
+TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
+"TS_SYS_CLK" * 4;
+# Select (address) bits for SRL32 shift registers used in stage3/stage4
+# calibration
+INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
+TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;
+#INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
+#TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;
+INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
+ TNM = "TNM_CAL_RDEN_DLY";
+TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
+ "TS_SYS_CLK" * 4;
+
+###############################################################################
+# DQS Read Post amble Glitch Squelch circuit related constraints
+###############################################################################
+
+###############################################################################
+# LOC placement of DQS-squelch related IDDR and IDELAY elements
+# Each circuit can be located at any of the following locations:
+# 1. Unused "N"-side of DQS differential pair I/O
+# 2. DM data mask (output only, input side is free for use)
+# 3. Any output-only site
+###############################################################################
+
+INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
+INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
+INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
+INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
+INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
+INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
+INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
+INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
+INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
+INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
+INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
+INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
+INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
+INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
+INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
+INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
+
+###############################################################################
+# LOC and timing constraints for flop driving DQS CE enable signal
+# from fabric logic. Even though the absolute delay on this path is
+# calibrated out (when synchronizing this output to DQS), the delay
+# should still be kept as low as possible to reduce post-calibration
+# voltage/temp variations - these are roughly proportional to the
+# absolute delay of the path
+###############################################################################
+
+INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
+INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
+INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
+INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
+INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
+INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
+INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
+INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;
+
+# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
+# two parts to this path: (1) from fabric flop to IDELAY, (2) from
+# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
+# This can be relaxed by the user for lower frequencies:
+# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
+# In general PAR should be able to route this
+# within 900ps over all speed grades.
+NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
+NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
+
+###############################################################################
+# "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
+# for DQS Read Post amble Glitch Squelch circuit
+###############################################################################
+
+# Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
+# where slack account for rise-time of DQS on board. For now assume slack =
+# 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
+# time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
+INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
+INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
+TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
+
+###############################################################################
+# MIG 2.2: Prevent unrelated logic from being packed into any slices used
+# by read data capture RPM's - if unrelated logic gets packed into
+# these slices, it could cause the DIRT strings that define the
+# IDDR -> fabric flop routing to become unroutable during PAR stage
+# (unrelated logic may require routing resources required by the
+# DIRT strings - MAP does not currently take into account DIRT
+# strings when placing logic
+###############################################################################
+
+AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
+
+###############################################################################
+# Location constraints for DQ read-data capture flops in fabric (for 2nd
+# stage capture)
+###############################################################################
+
+INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; # AF30 X0Y22 *
+INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43; # AK31 X0Y23
+INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45; # AF31 X0Y25
+INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; # AD30 X0Y26
+INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41; # AJ30 X0Y21
+INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; # AF29 X0Y22 ***
+INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; # AD29 X0Y24
+INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; # AE29 X0Y24
+INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; # AH27 X0Y8 ***
+INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32; # AF28 X0Y12
+INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; # AH28 X0Y13
+INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; # AA28 X0Y14
+INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26; # AG25 X0Y6
+INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; # AJ26 X0Y8 *
+INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; # AG28 X0Y13
+INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; # AB28 X0Y14
+INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35; # AC28 X0Y15
+INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; # AB25 X0Y16 ***
+INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; # AC27 X0Y18
+INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; # AA26 X0Y19
+INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; # AB26 X0Y16 *
+INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37; # AA24 X0Y17
+INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; # AB27 X0Y18
+INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; # AA25 X0Y19
+INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; # AC29 X0Y26
+INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; # AB30 X0Y29 ***
+INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53; # W31 X0Y33
+INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55; # V30 X0Y35
+INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; # AC30 X0Y29 *
+INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; # W29 X0Y32
+INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; # V27 X0Y34 ***
+INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; # W27 X0Y36
+INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; # V29 X0Y32
+INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; # Y27 X0Y36
+INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; # Y26 X0Y38
+INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; # W24 X0Y39
+INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; # V28 X0Y34 *
+INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57; # W25 X0Y37
+INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; # W26 X0Y38
+INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; # V24 X0Y39
+INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; # R24 X0Y100
+INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; # P25 X0Y101
+INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122; # N24 X0Y102
+INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; # P26 X0Y103
+INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; # T24 X0Y100
+INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; # N25 X0Y101
+INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; # P27 X0Y103
+INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; # N28 X0Y104
+INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; # M28 X0Y104
+INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; # L28 X0Y106
+INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132; # F25 X0Y112
+INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; # H25 X0Y113
+INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125; # K27 X0Y105
+INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; # K28 X0Y106
+INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; # H24 X0Y113
+INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; # G26 X0Y114
+INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; # G25 X0Y114
+INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; # M26 X0Y116
+INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137; # J24 X0Y117
+INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; # L26 X0Y118
+INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135; # J27 X0Y115
+INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; # M25 X0Y116
+INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; # L25 X0Y118
+INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139; # L24 X0Y119
-== Test ==============================================================
-#skip
-#expect 0
+== Test ==============================================================
+#expect 20
+#expect 16
+#expect 12
#ship debug : Debug
#ship ddr : DDR2
debug.in:
- recv, deliver;
+ set ilc=*; recv, deliver;
ddr.out:
- collect;
- set flags a=!c,b=b;
- send to debug.in;
- collect;
- set flags a=!c,b=b;
- send to debug.in;
-ddr.inAddrWrite:
- set word=0;
- deliver;
- deliver;
-ddr.inDataWrite:
- set word=1;
- deliver;
- deliver;
+ set ilc=3; collect;
+ send token to ddr.inAddrRead;
+ set ilc=3; collect, send to debug.in;
+ddr.inAddrWrite:
+ set word= 0x1; deliver;
+ set word= 0x10; deliver;
+ set word=0x100; deliver;
+ddr.inDataWrite:
+ set word=20; deliver;
+ set word=16; deliver;
+ set word=12; deliver;
+
+ddr.inAddrRead:
+ recv token;
+ set word= 0x1; deliver;
+ set word= 0x10; deliver;
+ set word=0x100; deliver;
== Constants ========================================================
//*****************************************************************************
// DISCLAIMER OF LIABILITY
-//
+//
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is distributed under license
// from Xilinx, Inc., and may be used, copied and/or
// disclosed only pursuant to the terms of a valid license
-// agreement with Xilinx, Inc. Xilinx hereby grants you a
-// license to use this text/file solely for design, simulation,
-// implementation and creation of design files limited
-// to Xilinx devices or technologies. Use with non-Xilinx
-// devices or technologies is expressly prohibited and
+// agreement with Xilinx, Inc. Xilinx hereby grants you a
+// license to use this text/file solely for design, simulation,
+// implementation and creation of design files limited
+// to Xilinx devices or technologies. Use with non-Xilinx
+// devices or technologies is expressly prohibited and
// immediately terminates your license unless covered by
// a separate agreement.
//
-// Xilinx is providing this design, code, or information
-// "as-is" solely for use in developing programs and
-// solutions for Xilinx devices, with no obligation on the
-// part of Xilinx to provide support. By providing this design,
-// code, or information as one possible implementation of
-// this feature, application or standard, Xilinx is making no
-// representation that this implementation is free from any
-// claims of infringement. You are responsible for
-// obtaining any rights you may require for your implementation.
-// Xilinx expressly disclaims any warranty whatsoever with
-// respect to the adequacy of the implementation, including
+// Xilinx is providing this design, code, or information
+// "as-is" solely for use in developing programs and
+// solutions for Xilinx devices, with no obligation on the
+// part of Xilinx to provide support. By providing this design,
+// code, or information as one possible implementation of
+// this feature, application or standard, Xilinx is making no
+// representation that this implementation is free from any
+// claims of infringement. You are responsible for
+// obtaining any rights you may require for your implementation.
+// Xilinx expressly disclaims any warranty whatsoever with
+// respect to the adequacy of the implementation, including
// but not limited to any warranties or representations that this
-// implementation is free from claims of infringement, implied
-// warranties of merchantability or fitness for a particular
+// implementation is free from claims of infringement, implied
+// warranties of merchantability or fitness for a particular
// purpose.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications is
// expressly prohibited.
//
-// Any modifications that are made to the Source Code are
+// Any modifications that are made to the Source Code are
// done at the users sole risk and will be unsupported.
//
// Copyright (c) 2006-2007 Xilinx, Inc. All rights reserved.
//
-// This copyright and support notice must be retained as part
-// of this text at all times.
+// This copyright and support notice must be retained as part
+// of this text at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// \ \ \/ Version: 2.3
// \ \ Application: MIG
// / / Filename: ddr2_infrastructure.v
-// /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
+// /___/ /\ Date Last Modified: $Date: 2008/05/08 15:20:47 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
-// Clock generation/distribution and reset synchronization
+// Clock distribution and reset synchronization
//Reference:
//Revision History:
-// Rev 1.1 - Parameter CLK_TYPE added and logic for DIFFERENTIAL and
-// SINGLE_ENDED added. PK. 20/6/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_infrastructure #
(
- // Following parameters are for 72-bit RDIMM design (for ML561 Reference
- // board design). Actual values may be different. Actual parameters values
- // are passed from design top module ddr2_sdram module. Please refer to
- // the ddr2_sdram module for actual values.
- parameter CLK_PERIOD = 3000,
- parameter CLK_TYPE = "DIFFERENTIAL",
- parameter DLL_FREQ_MODE = "HIGH",
parameter RST_ACT_LOW = 1
)
(
- input sys_clk_p,
- input sys_clk_n,
- input sys_clk,
- input clk200_p,
- input clk200_n,
- input idly_clk_200,
- output clk0,
- output clk90,
- output clk200,
- output clkdiv0,
+ input clk0,
+ input clk90,
+ input clk200,
+ input clkdiv0,
+ input dcm_lock,
input sys_rst_n,
input idelay_ctrl_rdy,
output rst0,
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
localparam RST_SYNC_NUM = 25;
- localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
- wire clk0_bufg;
- wire clk90_bufg;
- wire clk200_bufg;
- wire clk200_ibufg;
- wire clkdiv0_bufg;
- wire dcm_clk0;
- wire dcm_clk90;
- wire dcm_clkdiv0;
- wire dcm_lock;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;
assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
- assign clk0 = clk0_bufg;
- assign clk90 = clk90_bufg;
- assign clk200 = clk200_bufg;
- assign clkdiv0 = clkdiv0_bufg;
-
- generate
- if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
- //***************************************************************************
- // Differential input clock input buffers
- //***************************************************************************
-
- IBUFGDS_LVPECL_25 SYS_CLK_INST
- (
- .I (sys_clk_p),
- .IB (sys_clk_n),
- .O (sys_clk_ibufg)
- );
-
- IBUFGDS_LVPECL_25 IDLY_CLK_INST
- (
- .I (clk200_p),
- .IB (clk200_n),
- .O (clk200_ibufg)
- );
-
- end else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
- //**************************************************************************
- // Single ended input clock input buffers
- //**************************************************************************
-
- // AM -- edits: changed IBUFG to BUF
-
- BUF SYS_CLK_INST
- (
- .I (sys_clk),
- .O (sys_clk_ibufg)
- );
-
- BUF IDLY_CLK_INST
- (
- .I (idly_clk_200),
- .O (clk200_ibufg)
- );
-
- end
- endgenerate
-
- BUFG CLK_200_BUFG
- (
- .O (clk200_bufg),
- .I (clk200_ibufg)
- );
-
- //***************************************************************************
- // Global clock generation and distribution
- //***************************************************************************
-
- DCM_BASE #
- (
- .CLKIN_PERIOD (CLK_PERIOD_NS),
- .CLKDV_DIVIDE (2.0),
- .DLL_FREQUENCY_MODE (DLL_FREQ_MODE),
- .DUTY_CYCLE_CORRECTION ("TRUE"),
- .FACTORY_JF (16'hF0F0)
- )
- u_dcm_base
- (
- .CLK0 (dcm_clk0),
- .CLK180 (),
- .CLK270 (),
- .CLK2X (),
- .CLK2X180 (),
- .CLK90 (dcm_clk90),
- .CLKDV (dcm_clkdiv0),
- .CLKFX (),
- .CLKFX180 (),
- .LOCKED (dcm_lock),
- .CLKFB (clk0_bufg),
- .CLKIN (sys_clk_ibufg),
- .RST (sys_rst)
- );
-
- BUFG U_BUFG_CLK0
- (
- .O (clk0_bufg),
- .I (dcm_clk0)
- );
-
- BUFG U_BUFG_CLK90
- (
- .O (clk90_bufg),
- .I (dcm_clk90)
- );
-
- BUFG U_BUFG_CLKDIV0
- (
- .O (clkdiv0_bufg),
- .I (dcm_clkdiv0)
- );
//***************************************************************************
assign rst_tmp = sys_rst | ~dcm_lock | ~idelay_ctrl_rdy;
// synthesis attribute max_fanout of rst0_sync_r is 10
- always @(posedge clk0_bufg or posedge rst_tmp)
+ always @(posedge clk0 or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
rst0_sync_r <= rst0_sync_r << 1;
// synthesis attribute max_fanout of rstdiv0_sync_r is 10
- always @(posedge clkdiv0_bufg or posedge rst_tmp)
+ always @(posedge clkdiv0 or posedge rst_tmp)
if (rst_tmp)
rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
else
rstdiv0_sync_r <= rstdiv0_sync_r << 1;
// synthesis attribute max_fanout of rst90_sync_r is 10
- always @(posedge clk90_bufg or posedge rst_tmp)
+ always @(posedge clk90 or posedge rst_tmp)
if (rst_tmp)
rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
// synthesis attribute max_fanout of rst200_sync_r is 10
- always @(posedge clk200_bufg or negedge dcm_lock)
+ always @(posedge clk200 or negedge dcm_lock)
if (!dcm_lock)
rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
else
.D (stg1_out_fall_0m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg2a_rise
.D (stg1_out_rise_0m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
// Stage 3 falling -> rising edge translation
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_rise
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
//*********************************************************
// Slice #2 (posedge CLK): Used for:
.D (stg1_out_fall_0m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg1_out_rise_0m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
end else if ((DQ_MS == 0) && (DQ_COL == 0)) begin: gen_stg2_0s
.D (stg1_out_fall_0s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg2a_rise
.D (stg1_out_rise_0s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_rise
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg1_out_fall_0s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE_1 u_ff_stg2b_rise
.D (stg1_out_rise_0s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
end else if ((DQ_MS == 1) && (DQ_COL == 1)) begin: gen_stg2_1m
.D (stg1_out_fall_1m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg2a_rise
.D (stg1_out_rise_1m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_rise
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg1_out_fall_1m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "BFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE_1 u_ff_stg2b_rise
.D (stg1_out_rise_1m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
end else if ((DQ_MS == 0) && (DQ_COL == 1)) begin: gen_stg2_1s
.D (stg1_out_fall_1s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg2a_rise
.D (stg1_out_rise_1s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_rise
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg1_out_fall_1s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "BFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE_1 u_ff_stg2b_rise
.D (stg1_out_rise_1s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
end else if ((DQ_MS == 1) && (DQ_COL == 2)) begin: gen_stg2_2m
.D (stg1_out_fall_2m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg2a_rise
.D (stg1_out_rise_2m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "BFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_rise
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg1_out_fall_2m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE_1 u_ff_stg2b_rise
.D (stg1_out_rise_2m),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
end else if ((DQ_MS == 0) && (DQ_COL == 2)) begin: gen_stg2_2s
.D (stg1_out_fall_2s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg2a_rise
.D (stg1_out_rise_2s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_fall
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE u_ff_stg3b_rise
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "AFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
.D (stg1_out_fall_2s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
(* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
AREA_GROUP = "DDR_CAPTURE_FFS" *)
FDRSE_1 u_ff_stg2b_rise
.D (stg1_out_rise_2s),
.R (1'b0),
.S (1'b0)
- )/* */
- /* */;
+ )/* synthesis syn_preserve = 1 */
+ /* synthesis syn_replicate = 0 */;
end
endgenerate
projects / fleet.git / commitdiff