migrate verilog into ship files

[fleet.git] / Makefile

diff --git a/Makefile b/Makefile
index 40883fe..450e739 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -64,6 +64,9 @@ build/fabric.v: $(verilog_files) src/edu/berkeley/fleet/slipway/Slipway.java
 
 build/main.bit: build/fabric.v $(verilog_files)
        make fleet.jar
+       for A in `find ships -name \*.ship`;\
+         do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
+         done
        rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
        ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}'
        scp ${host}:${remote_dir}/build/main.bit build/