cleanup Alu1 and Alu2 FPGA code

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 1020acf..1a17432 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -13,15 +13,31 @@ data  out:  out
 
 
 == TeX ==============================================================
-This ship is a two-input arithmetic unit.  It features several
-opcodes, such as {\tt ADD} and {\tt SUB}.  In my opinion, it is
-niftycool.
 
-FIXME: implement all the link bit stuff
+{\tt Alu2} is a ``two-input'' arithmetic logic unit.  It includes
+logic for performing arithmetic operations on a pair of arguments.
+Currently this includes
+addition ({\sc add}),
+subtraction ({\sc sub}),
+maximum ({\sc max}), and
+minimum ({\sc min}).
 
-Use carry-in bit to create a selector?  Perhaps a waste of an ALU.
+\subsection*{Semantics}
 
-Flags: zero, negative, overflow, ?
+When a value is present at each of {\tt in1}, {\tt in2} and {\tt
+inOp}, these three values are consumed.  Based on the value consumed
+at {\tt inOp}, the requested operation is performed on the values
+consumed from {\tt in1} and {\tt in2}.  The result of this operation
+is then made available at {\tt out}.
+
+\subsection*{To Do}
+
+The {\it link bit} and other features of \cite{ies31} are not yet
+implemented.
+
+The carry-in, carry-out, zero-test, negative-test, and overflow-test
+flags typically present in a conventional processor ALU are also not
+yet implemented.
 
 == Fleeterpreter ====================================================
 public long resolveLiteral(String literal) {
@@ -58,36 +74,26 @@ public void service() {
 
 == FPGA ==============================================================
 
-  reg                    have_a;
-  reg [(`DATAWIDTH-1):0] reg_a;
-  reg                    have_b;
-  reg [(`DATAWIDTH-1):0] reg_b;
-  reg                    have_op;
-  reg [(`DATAWIDTH-1):0] reg_op;
-
   always @(posedge clk) begin
-    if (!have_a) begin
-      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
-      end
-    if (!have_b) begin
-      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
-      end
-    if (!have_op) begin
-      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
-      end
-  
-    if (have_a && have_b && have_op) begin
-      case (reg_op)
-        0: out_d = reg_a + reg_b;
-        1: out_d = reg_a - reg_b;
-        2: out_d = reg_a > reg_b ? reg_a : reg_b;
-        3: out_d = reg_a > reg_b ? reg_b : reg_a;
-        default: out_d = 0;
-      endcase        
-      `onwrite(out_r, out_a)
-        have_a  = 0;
-        have_b  = 0;
-        have_op = 0;
+    if (!rst) begin
+      `reset
+    end else begin
+      if (out_r    && out_a)    out_r    <= 0;
+      if (!in1_r   && in1_a)    in1_a    <= 0;
+      if (!in2_r   && in2_a)    in2_a    <= 0;
+      if (!inOp_r  && inOp_a)   inOp_a   <= 0;
+      if (!out_r && !out_a && in1_r && !in1_a && in2_r && !in2_a && inOp_r && !inOp_a) begin
+        out_r <= 1;
+        in1_a <= 1;
+        in2_a <= 1;
+        inOp_a <= 1;
+        case (inOp_d)
+          0: out_d <= in1_d + in2_d;
+          1: out_d <= in1_d - in2_d;
+          2: out_d <= in1_d > in2_d ? in1_d : in2_d;
+          3: out_d <= in1_d > in2_d ? in2_d : in1_d;
+          default: out_d <= 0;
+        endcase        
       end
     end
   end
@@ -104,10 +110,10 @@ public void service() {
 
 debug.in:   [*] take, deliver;
 alu.in1:
-  literal 9; [4] deliver;
+  literal 9; load repeat counter with 4; deliver;
 
 alu.in2:
-  literal 8; [4] deliver;
+  literal 8; load repeat counter with 4; deliver;
 
 alu.in1:    [*] take, deliver;
 alu.in2:    [*] take, deliver;