migrate verilog into ship files

[fleet.git] / ships / Alu2.ship

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 1314407..607a16e 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -45,6 +45,59 @@ public void service() {
 == ArchSim ==============================================================
 
 == FPGA ==============================================================
+`include "macros.v"
+
+module alu2 (clk, 
+             a_r,    a_a_,  a_d,
+             b_r,    b_a_,  b_d,
+             op_r,   op_a_, op_d,
+             out_r_, out_a, out_d_);
+
+  input  clk;
+  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
+  `input(b_r,    b_a,    b_a_,  [(`DATAWIDTH-1):0], b_d)
+  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
+  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+
+  reg                    have_a;
+  reg [(`DATAWIDTH-1):0] reg_a;
+  reg                    have_b;
+  reg [(`DATAWIDTH-1):0] reg_b;
+  reg                    have_op;
+  reg [(`DATAWIDTH-1):0] reg_op;
+
+  always @(posedge clk) begin
+    if (!have_a) begin
+      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      end
+    if (!have_b) begin
+      `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
+      end
+    if (!have_op) begin
+      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      end
+  
+    if (have_a && have_b && have_op) begin
+      case (reg_op)
+        0: out_d = reg_a + reg_b;
+        1: out_d = reg_a - reg_b;
+        //2: out_d = reg_a * reg_b; // will not synthesize --AM
+        //3: out_d = reg_a / reg_b; // will not synthesize --AM
+        //4: out_d = reg_a % reg_b; // will not synthesize --AM
+        default: out_d = 0;
+      endcase        
+      `onwrite(out_r, out_a)
+        have_a  = 0;
+        have_b  = 0;
+        have_op = 0;
+      end
+    end
+  end
+
+endmodule
+
+
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>