ship: Alu2
== Ports ===========================================================
-data in: a
-data in: b
-data in: op
+data in: in1
+data in: in2
+data in: inOp
data out: out
== Constants ========================================================
ADD: add the two arguments; treat link as carry
SUB: subtract the two arguments; treat link as carry
+MAX:
+MIN:
== TeX ==============================================================
This ship is a two-input arithmetic unit. It features several
opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
niftycool.
+FIXME: implement all the link bit stuff
+
+Use carry-in bit to create a selector? Perhaps a waste of an ALU.
+
+Flags: zero, negative, overflow, ?
+
+\begin{verbatim}
+move elsewhere:
+//MUL:
+//DIV:
+//MOD:
+\end{verbatim}
+
== Fleeterpreter ====================================================
+public long resolveLiteral(String literal) {
+ if (literal.equals("ADD")) return 0;
+ if (literal.equals("SUB")) return 1;
+ if (literal.equals("MAX")) return 2;
+ if (literal.equals("MIN")) return 3;
+ return super.resolveLiteral(literal);
+}
public void service() {
- if (box_a.dataReadyForShip() &&
- box_b.dataReadyForShip() &&
- box_op.dataReadyForShip() &&
- box_out.readyForItemFromShip()) {
- int a = box_a.removeDataForShip();
- int b = box_b.removeDataForShip();
- int op = box_op.removeDataForShip();
- switch(op) {
+ if (box_in1.dataReadyForShip() &&
+ box_in2.dataReadyForShip() &&
+ box_inOp.dataReadyForShip() &&
+ box_out.readyForDataFromShip()) {
+ long a = box_in1.removeDataForShip();
+ long b = box_in2.removeDataForShip();
+ long op = box_inOp.removeDataForShip();
+ switch((int)op) {
case 0: box_out.addDataFromShip(a+b); // ADD
break;
case 1: box_out.addDataFromShip(a-b); // SUB
break;
- case 2: box_out.addDataFromShip(a*b); // MUL
- break;
- case 3: box_out.addDataFromShip(a/b); // DIV
+ case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
break;
- case 4: box_out.addDataFromShip(a%b); // REM
+ case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
break;
default: box_out.addDataFromShip(0);
break;
}
}
-== ArchSim ==============================================================
+== FleetSim ==============================================================
== FPGA ==============================================================
+ reg have_a;
+ reg [(`DATAWIDTH-1):0] reg_a;
+ reg have_b;
+ reg [(`DATAWIDTH-1):0] reg_b;
+ reg have_op;
+ reg [(`DATAWIDTH-1):0] reg_op;
+
+ always @(posedge clk) begin
+ if (!have_a) begin
+ `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
+ end
+ if (!have_b) begin
+ `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
+ end
+ if (!have_op) begin
+ `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+ end
+
+ if (have_a && have_b && have_op) begin
+ case (reg_op)
+ 0: out_d = reg_a + reg_b;
+ 1: out_d = reg_a - reg_b;
+ 2: out_d = reg_a > reg_b ? reg_a : reg_b;
+ 3: out_d = reg_a > reg_b ? reg_b : reg_a;
+ default: out_d = 0;
+ endcase
+ `onwrite(out_r, out_a)
+ have_a = 0;
+ have_b = 0;
+ have_op = 0;
+ end
+ end
+ end
+
+== Test ==============================================================================
+// expected output
+#ship debug : Debug
+#ship alu : Alu2
+
+#expect 17
+#expect 1
+#expect 8
+#expect 9
+
+debug.in: [*] take, deliver;
+9: sendto alu.in1;
+9: sendto alu.in1;
+9: sendto alu.in1;
+9: sendto alu.in1;
+8: sendto alu.in2;
+8: sendto alu.in2;
+8: sendto alu.in2;
+8: sendto alu.in2;
+
+Alu2.ADD: sendto alu.inOp;
+Alu2.SUB: sendto alu.inOp;
+Alu2.MIN: sendto alu.inOp;
+Alu2.MAX: sendto alu.inOp;
+
+alu.in1: [*] take, deliver;
+alu.in2: [*] take, deliver;
+alu.inOp: [*] take, deliver;
+alu.out: [*] take, sendto debug.in;
+
+
+
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>