== TeX ==============================================================
-With judicious programming of its BenkoBoxes, this ship can be used to
+With judicious programming of its pumps, this ship can be used to
implement nearly all forms of selection and branching.
When data is available at the in port, it is examined. Which
`define BRAM_ADDR_WIDTH 14
`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
`define BRAM_NAME some_bram
-`include "bram.inc"
+
+/* bram.inc */
+module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
+ input clk;
+ input we;
+ input [(`BRAM_ADDR_WIDTH-1):0] a;
+ input [(`BRAM_ADDR_WIDTH-1):0] dpra;
+ input [(`BRAM_DATA_WIDTH-1):0] di;
+ output [(`BRAM_DATA_WIDTH-1):0] spo;
+ output [(`BRAM_DATA_WIDTH-1):0] dpo;
+ reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
+ reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
+ reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
+ always @(posedge clk) begin
+ if (we)
+ ram[a] <= di;
+ read_a <= a;
+ read_dpra <= dpra;
+ end
+ assign spo = ram[read_a];
+ assign dpo = ram[read_dpra];
+endmodule
+/* bram.inc */
module memory (clk,
cbd_r, cbd_a_, cbd_d,
String prefix = s[0];
PrintWriter pw;
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/bitfields.v")));
+ pw.println("`define DATAWIDTH "+WIDTH_WORD);
+ pw.println("`define CODEBAG_SIZE_BITS "+WIDTH_CODEBAG_SIZE);
+ pw.println("`define BENKOBOX_ADDRESS_BITS "+WIDTH_PUMP_ADDR);
+ pw.println("`define DESTINATION_ADDRESS_BITS "+WIDTH_DEST_ADDR);
+ pw.println("`define COUNT_BITS "+WIDTH_COUNT);
+ pw.println("`define COUNT_WIDTH "+WIDTH_COUNT);
+ pw.println("`define PACKET_WIDTH (`DATAWIDTH + `DESTINATION_ADDRESS_BITS)");
+ pw.println("`define INSTRUCTION_WIDTH "+WIDTH_WORD);
+ pw.println("`define packet_data(p) p[(`DESTINATION_ADDRESS_BITS+`DATAWIDTH-1):(`DESTINATION_ADDRESS_BITS)]");
+ pw.println("`define packet_dest(p) p[(`DESTINATION_ADDRESS_BITS-1):0]");
+ pw.flush();
+ pw.close();
+
mkfunnel("funnel", prefix);
mkhorn( "horn", prefix, WIDTH_PACKET-1, WIDTH_DEST_ADDR-1, 0, 0);
mkhorn( "ihorn", prefix, WIDTH_PACKET-1, 34, 24, 0);
);
PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
+ pw.println("`define INSTRUCTION_BENKOBOX_OFFSET (1+`COUNT_BITS+`DESTINATION_ADDRESS_BITS+5)");
+ pw.println("`define instruction_dest(i) i[(24+11-1):24]");
+ pw.println("`define packet_dest_steer(p) p[0]");
+ pw.println("`define instruction_dest_steer(i) i[24]");
+
+ pw.println("`define opcode_base (1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS)");
+ pw.println("`define instruction_bit_tokenout(instruction) instruction[`opcode_base+4]");
+ pw.println("`define instruction_bit_dataout(instruction) instruction[`opcode_base+3]");
+ pw.println("`define instruction_bit_latch(instruction) instruction[`opcode_base+2]");
+ pw.println("`define instruction_bit_datain(instruction) instruction[`opcode_base+1]");
+ pw.println("`define instruction_bit_tokenin(instruction) instruction[`opcode_base+0]");
+ pw.println("`define instruction_bit_dest(instruction) instruction[(`DESTINATION_ADDRESS_BITS):1]");
+ pw.println("`define instruction_bit_recycle(instruction) instruction[0]");
+ pw.println("`define instruction_is_kill(i) (`instruction_bit_latch(i) && (!(`instruction_bit_datain(i))))");
+ pw.println("`define instruction_bit_kill_only_standing(i) (`instruction_bit_tokenin(i))");
+ pw.println("`define instruction_count(instruction) instruction[(1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS-1):(1+`DESTINATION_ADDRESS_BITS)]");
+
+ pw.println("`define instruction_is_clog(instruction) (`instruction_count(instruction)==0 && !`instruction_bit_tokenin(instruction) && !`instruction_bit_datain(instruction) && !`instruction_bit_tokenout(instruction) && !`instruction_bit_dataout(instruction))");
+ pw.println("`define instruction_is_unclog(instruction) (`instruction_bit_kill_only_standing(instruction) && `instruction_is_kill(instruction))");
box.dump(pw);
pw.flush();
return box;
+++ /dev/null
-module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
- input clk;
- input we;
- input [(`BRAM_ADDR_WIDTH-1):0] a;
- input [(`BRAM_ADDR_WIDTH-1):0] dpra;
- input [(`BRAM_DATA_WIDTH-1):0] di;
- output [(`BRAM_DATA_WIDTH-1):0] spo;
- output [(`BRAM_DATA_WIDTH-1):0] dpo;
- reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
- reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
- reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
- always @(posedge clk) begin
- if (we)
- ram[a] <= di;
- read_a <= a;
- read_dpra <= dpra;
- end
- assign spo = ram[read_a];
- assign dpo = ram[read_dpra];
-endmodule
+++ /dev/null
- `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
- `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
- `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
- `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
-
- reg bram_we;
- wire bram_we_;
- assign bram_we_ = bram_we;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
- reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
- wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
- reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
- assign bram_write_data_ = bram_write_data;
- `BRAM_NAME mybram(clk,
- bram_we_, bram_write_address,
- bram_read_address, bram_write_data_,
- not_connected, bram_read_data);
-
- reg send_done;
+++ /dev/null
- bram_we = 0;
- if (send_done) begin
- `onwrite(write_done_r, write_done_a)
- send_done = 0;
- end
- end else begin
- if (!write_addr_r && write_addr_a) write_addr_a = 0;
- if (!write_data_r && write_data_a) write_data_a = 0;
- if (write_addr_r && write_data_r) begin
- write_addr_a = 1;
- write_data_a = 1;
- bram_we = 1;
- send_done = 1;
- bram_write_address = write_addr_d;
- bram_write_data = write_data_d;
- end
- end
-`define DATAWIDTH 37
-`define CODEBAG_SIZE_BITS 6
-`define BENKOBOX_ADDRESS_BITS 11
-`define DESTINATION_ADDRESS_BITS 11
-`define COUNT_BITS 7
-`define COUNT_WIDTH 7
-`define PACKET_WIDTH (`DATAWIDTH + `DESTINATION_ADDRESS_BITS)
-`define INSTRUCTION_WIDTH 37
-
-`define packet_data(p) p[(`DESTINATION_ADDRESS_BITS+`DATAWIDTH-1):(`DESTINATION_ADDRESS_BITS)]
-`define INSTRUCTION_BENKOBOX_OFFSET (1+`COUNT_BITS+`DESTINATION_ADDRESS_BITS+5)
-`define packet_dest(p) p[(`DESTINATION_ADDRESS_BITS-1):0]
-`define instruction_dest(i) i[(24+11-1):24]
-`define packet_dest_steer(p) p[0]
-`define instruction_dest_steer(i) i[24]
-
-`define opcode_base (1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS)
-`define instruction_bit_tokenout(instruction) instruction[`opcode_base+4]
-`define instruction_bit_dataout(instruction) instruction[`opcode_base+3]
-`define instruction_bit_latch(instruction) instruction[`opcode_base+2]
-`define instruction_bit_datain(instruction) instruction[`opcode_base+1]
-`define instruction_bit_tokenin(instruction) instruction[`opcode_base+0]
-`define instruction_bit_dest(instruction) instruction[(`DESTINATION_ADDRESS_BITS):1]
-`define instruction_bit_recycle(instruction) instruction[0]
-`define instruction_is_kill(i) (`instruction_bit_latch(i) && (!(`instruction_bit_datain(i))))
-`define instruction_bit_kill_only_standing(i) (`instruction_bit_tokenin(i))
-`define instruction_count(instruction) instruction[(1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS-1):(1+`DESTINATION_ADDRESS_BITS)]
-
-`define instruction_is_clog(instruction) (`instruction_count(instruction)==0 && !`instruction_bit_tokenin(instruction) && !`instruction_bit_datain(instruction) && !`instruction_bit_tokenout(instruction) && !`instruction_bit_dataout(instruction))
-`define instruction_is_unclog(instruction) (`instruction_bit_kill_only_standing(instruction) && `instruction_is_kill(instruction))
+`include "bitfields.v"
`define defreg(signame,width,regname) reg width regname; wire width signame; assign signame = regname; initial regname = 0;
`define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d; initial a=0;
+`timescale 1ps / 1ps
+
+// Copyright (c) 2005-2006, Regents of the University of California
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer
+// in the documentation and/or other materials provided with the
+// distribution.
+// - Neither the name of the University of California, Berkeley nor the
+// names of its contributors may be used to endorse or promote
+// products derived from this software without specific prior
+// written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
//----------------------------------------------------------------------------
-// user_fifo_test.v
+// user_fifo.v
//----------------------------------------------------------------------------
`timescale 1ps / 1ps
+module user_fifo
+ (
+ // FIFO interface ports
+ WrFifo_Din, // Write FIFO data-in
+ WrFifo_WrEn, // Write FIFO write enable
+ WrFifo_Full, // Write FIFO full
+ WrFifo_WrCnt, // Write FIFO write count
+ RdFifo_Dout, // Read FIFO data-out
+ RdFifo_RdEn, // Read FIFO read enable
+ RdFifo_Empty, // Read FIFO empty
+ RdFifo_RdCnt, // Read FIFO read count
+ User_Rst, // User reset
+ User_Clk, // User clock
+ Sys_Rst, // System clock reset
+ Sys_Clk, // 100MHz system clock for CCLK generation
+
+ // SelectMAP interface ports
+ D_I, // Data bus input
+ D_O, // Data bus output
+ D_T, // Data bus tristate enable
+ RDWR_B, // Read/write signal
+ CS_B, // Chip select
+ INIT_B, // Initialization/interrupt signal
+ CCLK // CCLK output
+ );
+
+ // FIFO interface ports
+ input [0:7] WrFifo_Din;
+ input WrFifo_WrEn;
+ output WrFifo_Full;
+ output [0:7] WrFifo_WrCnt;
+ output [0:7] RdFifo_Dout;
+ input RdFifo_RdEn;
+ output RdFifo_Empty;
+ output [0:7] RdFifo_RdCnt;
+ input User_Rst;
+ input User_Clk;
+ input Sys_Rst;
+ input Sys_Clk;
+
+ // SelectMAP protocol ports
+ input [0:7] D_I;
+ output [0:7] D_O;
+ output [0:7] D_T;
+ input RDWR_B;
+ input CS_B;
+ output INIT_B;
+ output CCLK;
+
+ // ____ __ _ _ _ _ //
+ // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
+ // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
+ // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
+ // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
+ // //
+
+ //----------------------------------------------------------------------------
+ // Signal definitions
+ //----------------------------------------------------------------------------
+ // Write FIFO signals
+ wire [0:7] WrFifo_Dout;
+ wire WrFifo_Empty;
+ wire WrFifo_RdEn;
+ wire [0:7] WrFifo_RdCnt;
+ wire [0:7] WrFifo_RdCnt_int;
+ wire [0:7] WrFifo_WrCnt_int;
+
+ // Read FIFO signals
+ wire [0:7] RdFifo_Din;
+ wire RdFifo_Full;
+ wire RdFifo_WrEn;
+ wire [0:7] RdFifo_WrCnt;
+ wire [0:7] RdFifo_WrCnt_int;
+ wire [0:7] RdFifo_RdCnt_int;
+
+ //----------------------------------------------------------------------------
+ // IO Registers
+ //----------------------------------------------------------------------------
+ reg CCLK;
+
+ reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
+ reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
+ reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
+ reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
+ reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
+
+ // Outputs
+ assign D_O = D_O_reg;
+ assign INIT_B = INIT_B_reg;
+
+ // Inputs
+ always @( posedge Sys_Clk )
+ begin
+ D_I_reg <= D_I;
+ RDWR_B_reg <= RDWR_B;
+ CS_B_reg <= CS_B;
+ end
+
+ //----------------------------------------------------------------------------
+ // Generate CCLK and associated reset
+ //----------------------------------------------------------------------------
+ reg SYNC_done;
+ reg SYNC_done_dly;
+ reg CS_B_reg_dly;
+
+ always @( posedge Sys_Clk )
+ begin
+ CS_B_reg_dly <= CS_B_reg;
+ end
+
+ always @( posedge Sys_Clk )
+ begin
+ if (Sys_Rst)
+ SYNC_done <= 1'b0;
+ else if (RDWR_B_reg && ~CS_B_reg)
+ SYNC_done <= 1'b1;
+ end
+
+ always @( posedge Sys_Clk )
+ begin
+ if (Sys_Rst)
+ SYNC_done_dly <= 1'b0;
+ else
+ SYNC_done_dly <= SYNC_done;
+ end
+
+ always @( posedge Sys_Clk )
+ begin
+ if (Sys_Rst)
+ CCLK <= 1'b0;
+ else if (~CS_B_reg && CS_B_reg_dly && CCLK)
+ CCLK <= 1'b1;
+ else
+ CCLK <= ~CCLK;
+ end
+
+ // _____ ___ _____ ___ //
+ // | ___|_ _| ___/ _ \ ___ //
+ // | |_ | || |_ | | | / __| //
+ // | _| | || _|| |_| \__ \ //
+ // |_| |___|_| \___/|___/ //
+ // //
+ // Write FIFO: The write is with respect to the user. The user writes data to this
+ // FIFO and the control side of SelectMAP reads the data.
+ //
+ // Read FIFO: The read is with respect to the user. The user reads data sent from the
+ // control side of SelectMAP.
+ //
+
+ //----------------------------------------------------------------------------
+ // Read FIFO
+ //----------------------------------------------------------------------------
+ assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
+ assign RdFifo_Din = D_I_reg;
+
+ async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
+ .dout( RdFifo_Dout ),
+ .rd_clk( User_Clk ),
+ .rd_en( RdFifo_RdEn ),
+ .wr_clk( Sys_Clk ),
+ .wr_en( RdFifo_WrEn ),
+ .rst( User_Rst ),
+ .empty( RdFifo_Empty ),
+ .full( RdFifo_Full ),
+ .rd_data_count( RdFifo_RdCnt_int ),
+ .wr_data_count( RdFifo_WrCnt_int ) );
+
+ assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
+ assign RdFifo_RdCnt = RdFifo_RdCnt_int;
+
+ //----------------------------------------------------------------------------
+ // Write FIFO
+ //----------------------------------------------------------------------------
+ assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
+
+ async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
+ .dout( WrFifo_Dout ),
+ .rd_clk( Sys_Clk ),
+ .rd_en( WrFifo_RdEn ),
+ .wr_clk( User_Clk ),
+ .wr_en( WrFifo_WrEn ),
+ .rst( User_Rst ),
+ .empty( WrFifo_Empty ),
+ .full( WrFifo_Full ),
+ .rd_data_count( WrFifo_RdCnt_int ),
+ .wr_data_count( WrFifo_WrCnt_int ) );
+
+ assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
+ assign WrFifo_RdCnt = WrFifo_RdCnt_int;
+
+ // ____ _ _ __ __ _ ____ //
+ // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
+ // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
+ // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
+ // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
+ // //
+
+ //----------------------------------------------------------------------------
+ // SelectMAP control outputs
+ //----------------------------------------------------------------------------
+ wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
+
+ assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
+
+ always @( posedge Sys_Clk )
+ begin
+ D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
+ INIT_B_reg <= WrFifo_Empty;
+ end
+
+ //----------------------------------------------------------------------------
+
+endmodule
+
+
module main
(
// User clock ports
+++ /dev/null
-// Copyright (c) 2005-2006, Regents of the University of California
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-// - Neither the name of the University of California, Berkeley nor the
-// names of its contributors may be used to endorse or promote
-// products derived from this software without specific prior
-// written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-//----------------------------------------------------------------------------
-// user_fifo.v
-//----------------------------------------------------------------------------
-
-`timescale 1ps / 1ps
-
-module user_fifo
- (
- // FIFO interface ports
- WrFifo_Din, // Write FIFO data-in
- WrFifo_WrEn, // Write FIFO write enable
- WrFifo_Full, // Write FIFO full
- WrFifo_WrCnt, // Write FIFO write count
- RdFifo_Dout, // Read FIFO data-out
- RdFifo_RdEn, // Read FIFO read enable
- RdFifo_Empty, // Read FIFO empty
- RdFifo_RdCnt, // Read FIFO read count
- User_Rst, // User reset
- User_Clk, // User clock
- Sys_Rst, // System clock reset
- Sys_Clk, // 100MHz system clock for CCLK generation
-
- // SelectMAP interface ports
- D_I, // Data bus input
- D_O, // Data bus output
- D_T, // Data bus tristate enable
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK // CCLK output
- );
-
- // FIFO interface ports
- input [0:7] WrFifo_Din;
- input WrFifo_WrEn;
- output WrFifo_Full;
- output [0:7] WrFifo_WrCnt;
- output [0:7] RdFifo_Dout;
- input RdFifo_RdEn;
- output RdFifo_Empty;
- output [0:7] RdFifo_RdCnt;
- input User_Rst;
- input User_Clk;
- input Sys_Rst;
- input Sys_Clk;
-
- // SelectMAP protocol ports
- input [0:7] D_I;
- output [0:7] D_O;
- output [0:7] D_T;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
-
- // ____ __ _ _ _ _ //
- // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
- // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
- // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
- // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
- // //
-
- //----------------------------------------------------------------------------
- // Signal definitions
- //----------------------------------------------------------------------------
- // Write FIFO signals
- wire [0:7] WrFifo_Dout;
- wire WrFifo_Empty;
- wire WrFifo_RdEn;
- wire [0:7] WrFifo_RdCnt;
- wire [0:7] WrFifo_RdCnt_int;
- wire [0:7] WrFifo_WrCnt_int;
-
- // Read FIFO signals
- wire [0:7] RdFifo_Din;
- wire RdFifo_Full;
- wire RdFifo_WrEn;
- wire [0:7] RdFifo_WrCnt;
- wire [0:7] RdFifo_WrCnt_int;
- wire [0:7] RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // IO Registers
- //----------------------------------------------------------------------------
- reg CCLK;
-
- reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
- reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
- reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
- reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
- reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
-
- // Outputs
- assign D_O = D_O_reg;
- assign INIT_B = INIT_B_reg;
-
- // Inputs
- always @( posedge Sys_Clk )
- begin
- D_I_reg <= D_I;
- RDWR_B_reg <= RDWR_B;
- CS_B_reg <= CS_B;
- end
-
- //----------------------------------------------------------------------------
- // Generate CCLK and associated reset
- //----------------------------------------------------------------------------
- reg SYNC_done;
- reg SYNC_done_dly;
- reg CS_B_reg_dly;
-
- always @( posedge Sys_Clk )
- begin
- CS_B_reg_dly <= CS_B_reg;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done <= 1'b0;
- else if (RDWR_B_reg && ~CS_B_reg)
- SYNC_done <= 1'b1;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done_dly <= 1'b0;
- else
- SYNC_done_dly <= SYNC_done;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- CCLK <= 1'b0;
- else if (~CS_B_reg && CS_B_reg_dly && CCLK)
- CCLK <= 1'b1;
- else
- CCLK <= ~CCLK;
- end
-
- // _____ ___ _____ ___ //
- // | ___|_ _| ___/ _ \ ___ //
- // | |_ | || |_ | | | / __| //
- // | _| | || _|| |_| \__ \ //
- // |_| |___|_| \___/|___/ //
- // //
- // Write FIFO: The write is with respect to the user. The user writes data to this
- // FIFO and the control side of SelectMAP reads the data.
- //
- // Read FIFO: The read is with respect to the user. The user reads data sent from the
- // control side of SelectMAP.
- //
-
- //----------------------------------------------------------------------------
- // Read FIFO
- //----------------------------------------------------------------------------
- assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
- assign RdFifo_Din = D_I_reg;
-
- async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
- .dout( RdFifo_Dout ),
- .rd_clk( User_Clk ),
- .rd_en( RdFifo_RdEn ),
- .wr_clk( Sys_Clk ),
- .wr_en( RdFifo_WrEn ),
- .rst( User_Rst ),
- .empty( RdFifo_Empty ),
- .full( RdFifo_Full ),
- .rd_data_count( RdFifo_RdCnt_int ),
- .wr_data_count( RdFifo_WrCnt_int ) );
-
- assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
- assign RdFifo_RdCnt = RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // Write FIFO
- //----------------------------------------------------------------------------
- assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
-
- async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
- .dout( WrFifo_Dout ),
- .rd_clk( Sys_Clk ),
- .rd_en( WrFifo_RdEn ),
- .wr_clk( User_Clk ),
- .wr_en( WrFifo_WrEn ),
- .rst( User_Rst ),
- .empty( WrFifo_Empty ),
- .full( WrFifo_Full ),
- .rd_data_count( WrFifo_RdCnt_int ),
- .wr_data_count( WrFifo_WrCnt_int ) );
-
- assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
- assign WrFifo_RdCnt = WrFifo_RdCnt_int;
-
- // ____ _ _ __ __ _ ____ //
- // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
- // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
- // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
- // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
- // //
-
- //----------------------------------------------------------------------------
- // SelectMAP control outputs
- //----------------------------------------------------------------------------
- wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
-
- assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
-
- always @( posedge Sys_Clk )
- begin
- D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
- INIT_B_reg <= WrFifo_Empty;
- end
-
- //----------------------------------------------------------------------------
-
-endmodule
projects / fleet.git / commitdiff