src/edu/berkeley/fleet/fpga/cache_write.inc

   1     bram_we = 0;
   2     if (send_done) begin
   3       `onwrite(write_done_r, write_done_a)
   4         send_done = 0;
   5       end
   6     end else begin
   7       if (!write_addr_r && write_addr_a) write_addr_a = 0;
   8       if (!write_data_r && write_data_a) write_data_a = 0;
   9       if (write_addr_r && write_data_r) begin
  10         write_addr_a = 1;
  11         write_data_a = 1;
  12         bram_we = 1;
  13         send_done = 1;
  14         bram_write_address = write_addr_d;
  15         bram_write_data = write_data_d;
  16       end
  17     end