reg [7:0] bitstorage_count; initial bitstorage_count = 0;
always @(posedge clk) begin
- if (bitstorage == 0) begin
+ if (bitstorage_count == 0) begin
`onread(inEnqueue_r, inEnqueue_a)
bitstorage <= inEnqueue_d;
bitstorage_count <= 37;
- outDequeue_d <= inEnqueue_d[0] ? 1'b1111111111111111111111111111111111111 : 0;
+ outDequeue_d <= (inEnqueue_d[0] ? 37'b1111111111111111111111111111111111111 : 0);
end
end else begin
`onwrite(outDequeue_r, outDequeue_a)
bitstorage_count <= bitstorage_count - 1;
- outDequeue_d <= bitstorage[1] ? 1'b1111111111111111111111111111111111111 : 0;
+ outDequeue_d <= (bitstorage[1] ? 37'b1111111111111111111111111111111111111 : 0);
bitstorage <= bitstorage >> 1;
end
end