data out: out
-percolate up: DDR2_CAS_B 1
-percolate up: DDR2_CKE 2
-percolate up: DDR2_RAS_B 1
-percolate up: DDR2_WE_B 1
-percolate up: DDR2_ODT 2
-percolate up: DDR2_CS0_B 2
-percolate up: DDR2_CLK_N 2
-percolate up: DDR2_CLK_P 2
-percolate up: DDR2_A 14
-percolate up: DDR2_BA 3
-percolate inout: DDR2_DQ 64
-percolate up: DDR2_DM 8
-percolate inout: DDR2_DQS_N 8
-percolate inout: DDR2_DQS_P 8
-
-percolate inout: I2C_DDR2_SCL 1
-percolate inout: I2C_DDR2_SDA 1
-
-percolate down: CLKBUF_Q1_N 1
-percolate down: CLKBUF_Q1_P 1
+percolate up: gpio_led_0 1
+percolate up: gpio_led_1 1
+percolate up: gpio_led_2 1
+percolate up: gpio_led_3 1
+
+percolate inout: ddr2_dq 64
+percolate up: ddr2_a 13
+percolate up: ddr2_ba 2
+percolate up: ddr2_ras_n 1
+percolate up: ddr2_cas_n 1
+percolate up: ddr2_we_n 1
+percolate up: ddr2_cs_n 1
+percolate up: ddr2_odt 1
+percolate up: ddr2_cke 1
+percolate up: ddr2_dm 8
+percolate up: phy_init_done 1
+percolate inout: ddr2_dqs 8
+percolate inout: ddr2_dqs_n 8
+percolate up: ddr2_ck 2
+percolate up: ddr2_ck_n 2
== TeX ==============================================================
== FPGA ==============================================================
-// Nearly all of this was copied from Greg Gibeling's work; copyright shown below:
-
-// Everything here was copied from
-// GateLib/Firmware/DRAM/Hardware/DDR2SDRAM/Test/FPGA_TOP_ML505_DDR2SDRAMTest.v
-
-//==============================================================================
-// Section: License
-//==============================================================================
-// Copyright (c) 2005-2008, Regents of the University of California
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-// - Neither the name of the University of California, Berkeley nor the
-// names of its contributors may be used to endorse or promote
-// products derived from this software without specific prior
-// written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//==============================================================================
-
-parameter
- ClockFreq = 200000000,
- BAWidth = 2,
- RAWidth = 13,
- CAWidth = 10,
- DWidth = 128, // 128b SDR internal transfers
- UWidth = 8, // This will almost ALWAYS be 8
- BurstLen = 2, // 256b total burst, 2 words DWidth words at SDR, or 4 external words at DDR
- EnableMask = 1,
- EnableECC = 0,
- Board = 0;
-
-localparam
- UCount = DWidth / UWidth,
- // 128b/8 = 16b per mask means per-byte masking
- MWidth = (EnableECC || (EnableMask == 0)) ? 0 : UCount,
- // Unused lower address bits, the -1 is to get a proper log2
- UAWidth = `log2(UCount-1),
- TAWidth = CAWidth + RAWidth + BAWidth,
- // Note that the components are in order according to where in the
- // address they appear, the -1 is to account for DDR
- AWidth = TAWidth + UAWidth - 1,
- ECheck = EnableECC ? 2 : 0,
- ECorrect = EnableECC ? 1 : 0,
- CWidth = 3,
- EHWidth = `max(`log2(ECheck), 1),
- ERWidth = `max(`log2(ECheck), 1);
-
-wire Reset;
-assign Reset = !rst;
-
-reg [AWidth-1:0] CommandAddress;
-reg [CWidth-1:0] Command;
-wire CommandReady;
-reg CommandValid;
-
-wire [DWidth-1:0] DataIn;
-wire [MWidth-1:0] DataInMask;
-reg DataInValid;
-wire DataInReady;
-
-wire [DWidth-1:0] DataOut;
-wire [EHWidth-1:0] DataOutErrorChecked;
-wire [ERWidth-1:0] DataOutErrorCorrected;
-wire DataOutValid;
-reg DataOutReady;
-
-wire Clock_IBUFG;
-wire Clock, ClockD2, ClockP90;
-wire Clock_DCM, ClockD2_DCM, ClockP90_DCM;
-wire Locked;
-
-reg [`WORDWIDTH:0] out_d;
-assign out_d_ = out_d;
-
-assign DDR2_BA[2] = 1'b0;
-assign DDR2_CS0_B[1] = 1'b1;
-assign DDR2_ODT[1] = 1'b0;
-assign DDR2_CKE[1] = 1'b0;
-
-IBUFGDS ClockIBufG(.I(CLKBUF_Q1_P), .IB(CLKBUF_Q1_N), .O(Clock_IBUFG));
-DCM_BASE
- #(
- .CLKIN_PERIOD(5.0),
- .CLKDV_DIVIDE(2.0),
- .DLL_FREQUENCY_MODE("HIGH"),
- .DUTY_CYCLE_CORRECTION("TRUE"),
- .FACTORY_JF(16'hF0F0)
- )
- DCMBase(
- .CLK0(Clock_DCM),
- .CLK180( ),
- .CLK270( ),
- .CLK2X( ),
- .CLK2X180( ),
- .CLK90(ClockP90_DCM),
- .CLKDV(ClockD2_DCM),
- .CLKFX( ),
- .CLKFX180( ),
- .LOCKED(Locked),
- .CLKFB(Clock),
- .CLKIN(Clock_IBUFG),
- .RST(Reset));
- // synthesis attribute CLKIN_PERIOD of DCMBase is "5.0"
- // synthesis attribute CLKDV_DIVIDE of DCMBase is "2.0"
- // synthesis attribute DLL_FREQUENCY_MODE of DCMBase is "HIGH"
- // synthesis attribute DUTY_CYCLE_CORRECTION of DCMBase is "TRUE"
- // synthesis attribute FACTORY_JF of DCMBase is "16'hF0F0"
- BUFG ClockBufG(.I(Clock_DCM), .O(Clock));
- BUFG ClockP90BufG(.I(ClockP90_DCM), .O(ClockP90));
- BUFG ClockD2BufG(.I(ClockD2_DCM), .O(ClockD2));
-
-DDR2SDRAM DDR2SDRAM(
- .Clock(Clock),
- .ClockD2(ClockD2),
- .ClockP90(ClockP90),
- .Reset(Reset),
- .Locked(Locked),
- .ClockF200(Clock),
- .Initialized( ),
- .PoweredUp( ),
-
- .CommandClock(clk),
- .DataInClock(clk),
- .DataOutClock(clk),
- .CommandReset(Reset),
- .DataInReset(Reset),
- .DataOutReset(Reset),
-
- .CommandAddress(CommandAddress),
- .Command(Command),
- .CommandValid(CommandValid),
- .CommandReady(CommandReady),
- .DataIn(DataIn),
- .DataInMask(DataInMask),
- .DataInValid(DataInValid),
- .DataInReady(DataInReady),
- .DataOut(DataOut),
- .DataOutErrorChecked(DataOutErrorChecked),
- .DataOutErrorCorrected(DataOutErrorCorrected),
- .DataOutValid(DataOutValid),
- .DataOutReady(DataOutReady),
- .DDR2_DQ(DDR2_DQ),
- .DDR2_A(DDR2_A),
- .DDR2_BA(DDR2_BA[1:0]),
- .DDR2_RAS_B(DDR2_RAS_B),
- .DDR2_CAS_B(DDR2_CAS_B),
- .DDR2_WE_B(DDR2_WE_B),
- .DDR2_CS0_B(DDR2_CS0_B[0]),
- .DDR2_ODT(DDR2_ODT[0]),
- .DDR2_CKE(DDR2_CKE[0]),
- .DDR2_DM(DDR2_DM),
- .DDR2_DQS_P(DDR2_DQS_P),
- .DDR2_DQS_N(DDR2_DQS_N),
- .DDR2_CLK_P(DDR2_CLK_P),
- .DDR2_CLK_N(DDR2_CLK_N));
- defparam DDR2SDRAM.UWidth = UWidth;
- defparam DDR2SDRAM.BAWidth = BAWidth;
- defparam DDR2SDRAM.RAWidth = RAWidth;
- defparam DDR2SDRAM.CAWidth = CAWidth;
- defparam DDR2SDRAM.DWidth = DWidth;
- defparam DDR2SDRAM.BurstLen = BurstLen;
- defparam DDR2SDRAM.EnableMask = EnableMask;
- defparam DDR2SDRAM.EnableECC = EnableECC;
- defparam DDR2SDRAM.Board = Board;
- defparam DDR2SDRAM.MultiClock = 1;
-
- assign DataIn = inDataWrite_d;
- assign DataInMask = 16'b1111111111111111;
-
+/*
+percolate inout: ddr2_dq 8
+percolate up: ddr2_a 15
+percolate up: ddr2_ba 3
+percolate up: ddr2_ras_n 1
+percolate up: ddr2_cas_n 1
+percolate up: ddr2_we_n 1
+percolate up: ddr2_cs_n 1
+percolate up: ddr2_odt 1
+percolate up: ddr2_cke 1
+percolate up: ddr2_dm 1
+percolate up: phy_init_done 1
+percolate inout: ddr2_dqs 1
+percolate inout: ddr2_dqs_n 1
+percolate up: ddr2_ck 1
+percolate up: ddr2_ck_n 1
+*/
+
+//NET "sys_clk_p" LOC = "H17" ; #Bank 3
+//NET "sys_clk_n" LOC = "H18" ; #Bank 3
+//NET "clk200_p" LOC = "K17" ; #Bank 3
+//NET "clk200_n" LOC = "L18" ; #Bank 3
+//NET "sys_rst_n" LOC = "L24" ; #Bank 19
+
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2006 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+wire clk200_p;
+wire clk200_n;
+wire clk_rebuffered;
+
+ ddr2_sdram # (
+ .BANK_WIDTH(2), // # of memory bank addr bits.
+ .CKE_WIDTH(1), // # of memory clock enable outputs.
+ .CLK_WIDTH(2), // # of clock outputs.
+ .COL_WIDTH(10), // # of memory column bits.
+ .CS_NUM(1), // # of separate memory chip selects.
+ .CS_WIDTH(1), // # of total memory chip selects.
+ .CS_BITS(0), // set to log2(CS_NUM) (rounded up).
+ .DM_WIDTH(8), // # of data mask bits.
+ .DQ_WIDTH(64), // # of data width.
+ .DQ_PER_DQS(8), // # of DQ data bits per strobe.
+ .DQS_WIDTH(8), // # of DQS strobes.
+ .DQ_BITS(6), // set to log2(DQS_WIDTH*DQ_PER_DQS).
+ .DQS_BITS(3), // set to log2(DQS_WIDTH).
+ .ODT_WIDTH(1), // # of memory on-die term enables.
+ .ROW_WIDTH(13), // # of memory row and # of addr bits.
+ .ADDITIVE_LAT(0), // additive write latency.
+ .BURST_LEN(4), // burst length (in double words).
+ .BURST_TYPE(0), // burst type (=0 seq; =1 interleaved).
+ .CAS_LAT(4), // CAS latency.
+ .ECC_ENABLE(0), // enable ECC (=1 enable).
+ .APPDATA_WIDTH(128), // # of usr read/write data bus bits.
+ .MULTI_BANK_EN(1), // Keeps multiple banks open. (= 1 enable).
+ .TWO_T_TIME_EN(1), // 2t timing for unbuffered dimms.
+ .ODT_TYPE(1), // ODT (=0(none),=1(75),=2(150),=3(50)).
+ .REDUCE_DRV(0), // reduced strength mem I/O (=1 yes).
+ .REG_ENABLE(0), // registered addr/ctrl (=1 yes).
+ .TREFI_NS(7800), // auto refresh interval (ns).
+ .TRAS(40000), // active->precharge delay.
+ .TRCD(15000), // active->read/write delay.
+ .TRFC(127500), // refresh->refresh, refresh->active delay.
+ .TRP(15000), // precharge->command delay.
+ .TRTP(7500), // read->precharge delay.
+ .TWR(15000), // used to determine write->precharge.
+ .TWTR(7500), // write->read delay.
+ .HIGH_PERFORMANCE_MODE("TRUE"), // # = TRUE, the IODELAY performance mode is set to high.
+ // # = FALSE, the IODELAY performance mode is set to low.
+ .SIM_ONLY(0), // = 1 to skip SDRAM power up delay.
+ .DEBUG_EN(0), // Enable debug signals/controls.
+ // When this parameter is changed from 0 to 1,
+ // make sure to uncomment the coregen commands
+ // in ise_flow.bat or create_ise.bat files in
+ // par folder.
+ .CLK_PERIOD(5000), // Core/Memory clock period (in ps).
+ .DQS_IO_COL(16'b0000000000000000), // I/O column location of DQS groups
+ // (=0, left; =1 center, =2 right).
+ //.DQ_IO_MS(64'b10100101_10100101_10100101_10100101_10100101_10100101_10100101_10100101),
+ .DQ_IO_MS(64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100),
+ // Master/Slave location of DQ I/O (=0 slave).
+ .CLK_TYPE("SINGLE_ENDED"), // # = "DIFFERENTIAL " ->; Differential input clocks ,
+ // # = "SINGLE_ENDED" -> Single ended input clocks.
+ .DLL_FREQ_MODE("HIGH"), // DCM Frequency range.
+ .RST_ACT_LOW(1) // =1 for active low reset, =0 for active high.
+)
+ddr2_sdram (
+ .sys_clk (clk),
+ .idly_clk_200 (clk200_p),
+ .sys_rst_n (!rst),
+
+ .ddr2_dq (ddr2_dq),
+ .ddr2_a (ddr2_a),
+ .ddr2_ba (ddr2_ba),
+ .ddr2_ras_n (ddr2_ras_n),
+ .ddr2_cas_n (ddr2_cas_n),
+ .ddr2_we_n (ddr2_we_n),
+ .ddr2_cs_n (ddr2_cs_n),
+ .ddr2_odt (ddr2_odt),
+ .ddr2_cke (ddr2_cke),
+ .ddr2_dm (ddr2_dm),
+ .ddr2_dqs (ddr2_dqs),
+ .ddr2_dqs_n (ddr2_dqs_n),
+ .ddr2_ck (ddr2_ck),
+ .ddr2_ck_n (ddr2_ck_n),
+
+ .phy_init_done (gpio_led_0),
+
+ .app_wdf_afull (gpio_led_1),
+ .app_af_afull (gpio_led_2),
+ .rd_data_valid (gpio_led_3),
+
+ .app_wdf_wren (1'b1),
+ .app_af_wren (app_af_wren),
+ .app_af_addr (app_af_addr),
+ .app_af_cmd (app_af_cmd),
+
+ .rd_data_fifo_out (rd_data_fifo_out),
+ .app_wdf_data (app_wdf_data),
+ .app_wdf_mask_data (app_wdf_mask_data)
+);
+
+ wire clk200_p_fb;
+ DCM // 200Mhz DDR clock
+ #(
+ .CLKFX_MULTIPLY(2),
+ .CLKFX_DIVIDE(1),
+ .CLKIN_PERIOD("10 ns")
+ ) vgadcm (
+ .CLKIN (clk),
+ .CLKFB (clk200_p_fb),
+ .CLKFX (clk200_n),
+ .CLKFX180 (clk200_p),
+ .CLK0 (clk200_p_fb)
+ );
+
+/*
always @(posedge clk) begin
if (rst) begin
end
end
end
+*/
== Test ==============================================================
projects / fleet.git / blobdiff