wire break;
wire uart_cts;
assign uart_cts = 0;
- assign rst_out = rst_in && !break;
+ assign rst_out = rst_in || break;
// fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
// using a 33Mhz clock,
// 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1
- sasc_brg sasc_brg(clk, rst_in, 215, 1, sio_ce, sio_ce_x4);
- sasc_top sasc_top(clk, rst_in,
+ sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
+ sasc_top sasc_top(clk, !rst_in,
uart_in,
uart_out,
uart_cts,
// fpga -> host
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
count_in <= 0;
count_out <= 0;
`reset