wire break;
wire uart_cts;
assign uart_cts = 0;
- assign rst_out = rst_in && !break;
-
- sasc_brg sasc_brg(clk, rst_in, 3, 65, sio_ce, sio_ce_x4);
- sasc_top sasc_top(clk, rst_in,
+ assign rst_out = rst_in || break;
+
+ // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
+ // using a 33Mhz clock,
+ // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
+ // using a 100Mhz clock,
+ // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
+ sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
+ sasc_top sasc_top(clk, !rst_in,
uart_in,
uart_out,
uart_cts,
// fpga -> host
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
count_in <= 0;
count_out <= 0;
`reset
end else begin
- `flush
`cleanup
// fpga -> host
end else if (count_out==0 && `in_full) begin
`drain_in
data_to_host_full_word <= in_d;
- count_out <= 6;
+ count_out <= 8;
end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable) begin
- data_to_host <= data_to_host_full_word[7:0];
- data_to_host_full_word <= (data_to_host_full_word >> 8);
+ data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
+ data_to_host_full_word <= (data_to_host_full_word >> 6);
data_to_host_write_enable <= 1;
count_out <= count_out-1;
end
// host -> fpga
data_to_fleet_read_enable <= 0;
if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin
- out_d <= { out_d[41:0], data_to_fleet[7:0] };
+ out_d <= { out_d[43:0], data_to_fleet[5:0] };
data_to_fleet_read_enable <= 1;
- if (count_in==7) begin
+ if (count_in==9) begin
count_in <= 0;
`fill_out
end else begin
end
end
+== UCF =================================================================
+
+Net clk_pin LOC=AH15;
+Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
+
+# 33mhz clock
+#Net clk_pin LOC=AH17;
+#Net clk_pin TNM_NET = clk_pin;
+#TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
+
+Net rst_pin LOC=E9;
+Net rst_pin PULLUP;
+Net rst_pin TIG;
+
+#Net uart_cts LOC=G6;
+#Net uart_cts IOSTANDARD = LVCMOS33;
+#Net uart_cts TIG;
+
+#Net uart_rts LOC=F6;
+#Net uart_rts IOSTANDARD = LVCMOS33;
+#Net uart_rts TIG;
+
+Net uart_in LOC=AG15;
+#Net uart_in IOSTANDARD = LVCMOS33;
+Net uart_in TIG;
+Net uart_in PULLUP;
+
+Net uart_out LOC=AG20;
+#Net uart_out IOSTANDARD = LVCMOS33;
+Net uart_out TIG;
+Net uart_out PULLUP;
+
+NET gpio_sw_c LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI
+
+NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V
+NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V
+NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V
+NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V
+
+NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_3 LOC="AD26" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET gpio_led_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_5 LOC="AD25" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+
+
+
+
+
== Test ================================================================
#expect 25